stats: updates due to recent changesets including d0934b57735a

224 files changed, 50709 insertions, 51030 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
index a7c751a3c..db58f5ad6 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -141,7 +141,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -564,7 +564,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -613,7 +613,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -747,7 +747,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index b894ed506..96524a9ce 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,92 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.886196                       # Number of seconds simulated
-sim_ticks                                1886195993000                       # Number of ticks simulated
-final_tick                               1886195993000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.887168                       # Number of seconds simulated
+sim_ticks                                1887168480000                       # Number of ticks simulated
+final_tick                               1887168480000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 256659                       # Simulator instruction rate (inst/s)
-host_op_rate                                   256659                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8626071053                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 374008                       # Number of bytes of host memory used
-host_seconds                                   218.66                       # Real time elapsed on the host
-sim_insts                                    56121694                       # Number of instructions simulated
-sim_ops                                      56121694                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 181674                       # Simulator instruction rate (inst/s)
+host_op_rate                                   181674                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6108559174                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 367844                       # Number of bytes of host memory used
+host_seconds                                   308.94                       # Real time elapsed on the host
+sim_insts                                    56125948                       # Number of instructions simulated
+sim_ops                                      56125948                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           1049728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24850240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1049920                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24850048                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             25900928                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1049728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1049728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7553600                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7553600                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16402                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388285                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst      1049920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1049920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7553472                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7553472                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              16405                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388282                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                404702                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118025                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118025                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               556532                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13174792                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::writebacks          118023                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118023                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               556347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13167901                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               509                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13731833                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          556532                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             556532                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4004674                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4004674                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4004674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              556532                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13174792                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13724757                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          556347                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             556347                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4002542                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4002542                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4002542                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              556347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13167901                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17736507                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17727299                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        404702                       # Number of read requests accepted
-system.physmem.writeReqs                       118025                       # Number of write requests accepted
+system.physmem.writeReqs                       118023                       # Number of write requests accepted
 system.physmem.readBursts                      404702                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118025                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25894272                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7551808                       # Total number of bytes written to DRAM
+system.physmem.writeBursts                     118023                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25893824                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7551936                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  25900928                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7553600                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytesWrittenSys                7553472                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          41706                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25487                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25728                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25822                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25769                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25085                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25016                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24650                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24524                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          41707                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25482                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25721                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25818                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25768                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25084                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25019                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24651                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24525                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               25293                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25190                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25398                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24986                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24522                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25563                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25828                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25737                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7820                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7688                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8067                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25189                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25397                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24988                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24521                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25565                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25830                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25740                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7815                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7682                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8062                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                7737                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7196                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7011                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6646                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6392                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7401                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6804                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7278                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6972                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7012                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6647                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6398                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7404                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6806                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7277                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6969                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               7052                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8008                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7983                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7942                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8011                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7982                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7949                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1886187226500                       # Total gap between requests
+system.physmem.numWrRetry                          29                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1887159671500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -100,10 +100,10 @@ system.physmem.writePktSize::2                      0                       # Wr
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118025                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402327                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118023                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402323                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                      2193                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        66                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        63                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -148,188 +148,187 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5494                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63594                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      525.931377                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     320.890659                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     414.200803                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14460     22.74%     22.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10997     17.29%     40.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4933      7.76%     47.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3625      5.70%     53.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2479      3.90%     57.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1827      2.87%     60.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1418      2.23%     62.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1367      2.15%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22488     35.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63594                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5295                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        76.408121                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2902.928186                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5292     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1846                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6025                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5962                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8775                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7502                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5787                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       94                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63563                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      526.182842                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     320.768050                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     414.563237                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14483     22.79%     22.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10991     17.29%     40.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4893      7.70%     47.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3583      5.64%     53.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2419      3.81%     57.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1815      2.86%     60.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1455      2.29%     62.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1407      2.21%     64.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22517     35.42%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63563                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5279                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.639515                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2907.321691                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5276     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5295                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5295                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.284608                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.797942                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.673735                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4676     88.31%     88.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             227      4.29%     92.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              77      1.45%     94.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              16      0.30%     94.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              14      0.26%     94.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               6      0.11%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               7      0.13%     94.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               9      0.17%     95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87               7      0.13%     95.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              34      0.64%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            171      3.23%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            10      0.19%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             1      0.02%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             1      0.02%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             5      0.09%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             3      0.06%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             1      0.02%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             2      0.04%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             4      0.08%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             4      0.08%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             8      0.15%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             2      0.04%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             7      0.13%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5295                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2213284250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9799496750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2022990000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5470.33                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5279                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5279                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.352529                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.833418                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.552708                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4665     88.37%     88.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             223      4.22%     92.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              69      1.31%     93.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              13      0.25%     94.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               7      0.13%     94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               8      0.15%     94.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              10      0.19%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              11      0.21%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87               9      0.17%     95.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              33      0.63%     95.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            187      3.54%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             5      0.09%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             2      0.04%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.04%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             7      0.13%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             3      0.06%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             3      0.06%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             6      0.11%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.04%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             9      0.17%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-295             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5279                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2194493000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9780574250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2022955000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5423.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24220.33                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.73                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24173.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.72                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.73                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.72                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        4.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.19                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363516                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95485                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.85                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.90                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3608360.06                       # Average gap between requests
+system.physmem.avgWrQLen                        21.87                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363582                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95445                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.86                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.87                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3610234.20                       # Average gap between requests
 system.physmem.pageHitRate                      87.83                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  233845920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  127594500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1576231800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                379449360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           123197134320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            60326866845                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1078799265750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1264640388495                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.471373                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1794467110750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     62984220000                       # Time in different power states
+system.physmem_0.actEnergy                  233596440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  127458375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1576130400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                379397520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           123260195760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            60352481790                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1079356093500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1265285353785                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.470116                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1795392967750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63016460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28744633000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28752031000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  246924720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  134730750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1579632600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                385171200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           123197134320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61494025635                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1077775442250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1264813061475                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.562919                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1792762379750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     62984220000                       # Time in different power states
+system.physmem_1.actEnergy                  246939840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134739000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1579679400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385236000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           123260195760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61300664820                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1078524362250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1265431817070                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.547722                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1794008459000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63016460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30449364000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30136553500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                15004879                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13013312                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            375549                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10036322                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5207234                       # Number of BTB hits
+system.cpu.branchPred.lookups                14997890                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13009268                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            370594                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9393435                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5198350                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             51.883887                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  808293                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              31321                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             55.340246                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  807960                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              32049                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9242647                       # DTB read hits
-system.cpu.dtb.read_misses                      17811                       # DTB read misses
+system.cpu.dtb.read_hits                      9241004                       # DTB read hits
+system.cpu.dtb.read_misses                      17472                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   766734                       # DTB read accesses
-system.cpu.dtb.write_hits                     6385782                       # DTB write hits
-system.cpu.dtb.write_misses                      2309                       # DTB write misses
+system.cpu.dtb.read_accesses                   766036                       # DTB read accesses
+system.cpu.dtb.write_hits                     6386411                       # DTB write hits
+system.cpu.dtb.write_misses                      2301                       # DTB write misses
 system.cpu.dtb.write_acv                          160                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298407                       # DTB write accesses
-system.cpu.dtb.data_hits                     15628429                       # DTB hits
-system.cpu.dtb.data_misses                      20120                       # DTB misses
+system.cpu.dtb.write_accesses                  298419                       # DTB write accesses
+system.cpu.dtb.data_hits                     15627415                       # DTB hits
+system.cpu.dtb.data_misses                      19773                       # DTB misses
 system.cpu.dtb.data_acv                           371                       # DTB access violations
-system.cpu.dtb.data_accesses                  1065141                       # DTB accesses
-system.cpu.itb.fetch_hits                     4016387                       # ITB hits
-system.cpu.itb.fetch_misses                      6834                       # ITB misses
-system.cpu.itb.fetch_acv                          689                       # ITB acv
-system.cpu.itb.fetch_accesses                 4023221                       # ITB accesses
+system.cpu.dtb.data_accesses                  1064455                       # DTB accesses
+system.cpu.itb.fetch_hits                     4013195                       # ITB hits
+system.cpu.itb.fetch_misses                      6857                       # ITB misses
+system.cpu.itb.fetch_acv                          677                       # ITB acv
+system.cpu.itb.fetch_accesses                 4020052                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -342,39 +341,39 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        180216793                       # number of cpu cycles simulated
+system.cpu.numCycles                        182043546                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56121694                       # Number of instructions committed
-system.cpu.committedOps                      56121694                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2519198                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5577                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3592175193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.211179                       # CPI: cycles per instruction
-system.cpu.ipc                               0.311412                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56125948                       # Number of instructions committed
+system.cpu.committedOps                      56125948                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2502558                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5565                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3594204473                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.243483                       # CPI: cycles per instruction
+system.cpu.ipc                               0.308311                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211471                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74788     40.94%     40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     133      0.07%     41.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1901      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105864     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182686                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73421     49.32%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1901      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73422     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148877                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1833775262000     97.22%     97.22% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                81341000      0.00%     97.23% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               679703500      0.04%     97.26% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             51658703500      2.74%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1886195010000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981722                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211461                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74782     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1902      1.04%     42.05% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105860     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182675                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73415     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1902      1.28%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73415     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148863                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1834747397000     97.22%     97.22% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                80828500      0.00%     97.23% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               680298500      0.04%     97.26% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             51658959000      2.74%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1887167483000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981720                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693550                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814934                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693510                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814906                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -413,8 +412,8 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4172      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175525     91.23%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175514     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6805      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
@@ -422,7 +421,7 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.97% # nu
 system.cpu.kern.callpal::rti                     5127      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192408                       # number of callpals executed
+system.cpu.kern.callpal::total                 192398                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5868                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
@@ -433,92 +432,92 @@ system.cpu.kern.mode_switch_good::kernel     0.324983                       # fr
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.080114                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::total      0.393034                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36513483500      1.94%      1.94% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4123557000      0.22%      2.15% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1845557959500     97.85%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel        36501486500      1.93%      1.93% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4115911000      0.22%      2.15% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1846550075500     97.85%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4173                       # number of times the context was actually changed
-system.cpu.tickCycles                        84408299                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        95808494                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1395428                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.981685                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13773051                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395940                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.866506                       # Average number of references to valid blocks.
+system.cpu.tickCycles                        86269078                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        95774468                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1395484                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.981722                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13771544                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395996                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.865031                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          90850500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.981685                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.981722                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63660654                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63660654                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7815445                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815445                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5575784                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5575784                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182800                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182800                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       198989                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       198989                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13391229                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13391229                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13391229                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13391229                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1201797                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201797                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       574153                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       574153                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17210                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17210                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1775950                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1775950                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1775950                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1775950                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32866409500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32866409500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  22318082000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  22318082000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    230873000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    230873000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  55184491500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  55184491500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  55184491500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  55184491500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9017242                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9017242                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6149937                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6149937                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200010                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200010                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       198989                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       198989                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15167179                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15167179                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15167179                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15167179                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133278                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133278                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093359                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093359                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086046                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086046                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117092                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117092                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117092                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117092                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31073.223627                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31073.223627                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63656757                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63656757                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7813939                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7813939                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5575873                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5575873                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       182717                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182717                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       198981                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       198981                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13389812                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13389812                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13389812                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13389812                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1201834                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201834                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       574561                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       574561                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17285                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17285                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1776395                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1776395                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1776395                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1776395                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32870602000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32870602000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  22298477500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  22298477500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232185000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    232185000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55169079500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55169079500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55169079500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55169079500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9015773                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9015773                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6150434                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6150434                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200002                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200002                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       198981                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       198981                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15166207                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15166207                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15166207                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15166207                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133303                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133303                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093418                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093418                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086424                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086424                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.117128                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117128                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117128                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117128                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31056.763558                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31056.763558                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -527,129 +526,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838228                       # number of writebacks
-system.cpu.dcache.writebacks::total            838228                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127318                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127318                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       269861                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269861                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       838310                       # number of writebacks
+system.cpu.dcache.writebacks::total            838310                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127379                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127379                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270264                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       270264                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       397179                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       397179                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       397179                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       397179                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074479                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074479                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304292                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304292                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17207                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17207                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378771                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378771                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378771                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378771                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16555                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16555                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29864669500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29864669500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11367980000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11367980000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    213500500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    213500500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41232649500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  41232649500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41232649500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  41232649500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1451443000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1451443000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2042111500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2042111500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3493554500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3493554500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119158                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119158                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049479                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049479                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086031                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086031                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090905                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090905                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090905                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090905                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27794.558572                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27794.558572                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37358.786955                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37358.786955                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12407.770094                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12407.770094                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29905.364633                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29905.364633                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29905.364633                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29905.364633                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209322.613210                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209322.613210                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212255.638707                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212255.638707                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211027.151918                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211027.151918                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       397643                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       397643                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       397643                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       397643                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074455                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074455                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304297                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304297                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17282                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17282                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1378752                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378752                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1378752                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378752                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9620                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9620                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16550                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16550                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29867395000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29867395000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11355989000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11355989000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    214737500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    214737500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41223384000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  41223384000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41223384000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  41223384000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450621500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450621500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2041589000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2041589000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3492210500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3492210500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119175                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119175                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049476                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049476                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086409                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086409                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090909                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090909                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090909                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090909                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27797.716051                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27797.716051                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37318.767520                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37318.767520                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12425.500521                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12425.500521                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29899.056538                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29899.056538                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29899.056538                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29899.056538                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209324.891775                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209324.891775                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212223.388773                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212223.388773                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211009.697885                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211009.697885                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1459012                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.459740                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18968780                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1459523                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.996561                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       33609211500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.459740                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995039                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995039                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1459068                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.460685                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18942908                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1459579                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.978337                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       33609235500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.460685                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995040                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995040                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          401                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          400                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21888175                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21888175                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18968783                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18968783                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18968783                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18968783                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18968783                       # number of overall hits
-system.cpu.icache.overall_hits::total        18968783                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1459696                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1459696                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1459696                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1459696                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1459696                       # number of overall misses
-system.cpu.icache.overall_misses::total       1459696                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20145975000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20145975000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20145975000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20145975000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20145975000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20145975000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20428479                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20428479                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20428479                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20428479                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20428479                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20428479                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071454                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071454                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071454                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071454                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071454                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071454                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.486748                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13801.486748                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.486748                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13801.486748                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.486748                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13801.486748                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          21862421                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21862421                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18942911                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18942911                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18942911                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18942911                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18942911                       # number of overall hits
+system.cpu.icache.overall_hits::total        18942911                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1459755                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1459755                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1459755                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1459755                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1459755                       # number of overall misses
+system.cpu.icache.overall_misses::total       1459755                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20136698000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20136698000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20136698000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20136698000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20136698000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20136698000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20402666                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20402666                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20402666                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20402666                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20402666                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20402666                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071547                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071547                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071547                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071547                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071547                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071547                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13794.573747                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13794.573747                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13794.573747                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13794.573747                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13794.573747                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13794.573747                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -658,141 +657,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1459696                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1459696                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1459696                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1459696                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1459696                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1459696                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  18686279000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  18686279000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  18686279000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  18686279000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  18686279000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  18686279000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071454                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071454                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071454                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071454                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071454                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071454                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.486748                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12801.486748                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12801.486748                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12801.486748                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12801.486748                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12801.486748                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1459755                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1459755                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1459755                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1459755                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1459755                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1459755                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  18676943000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  18676943000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  18676943000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  18676943000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  18676943000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  18676943000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071547                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071547                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071547                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071547                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071547                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071547                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12794.573747                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12794.573747                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12794.573747                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12794.573747                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12794.573747                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12794.573747                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           339196                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65318.328839                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4996938                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404358                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.357708                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           339197                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65316.861882                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4997134                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           404357                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.358223                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       6286116000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54387.720391                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5865.311953                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5065.296495                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.829891                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.089498                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.077290                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996679                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 54372.711085                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5866.673832                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5077.476965                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.829662                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.089518                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.077476                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996656                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65160                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1416                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5169                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2809                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55538                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         46373741                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        46373741                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       838228                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       838228                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2816                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55529                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994263                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         46375417                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        46375417                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       838310                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       838310                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187768                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187768                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1443233                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1443233                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819477                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       819477                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1443233                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1007245                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2450478                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1443233                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1007245                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2450478                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116534                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116534                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16403                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16403                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272179                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       272179                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        16403                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388713                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187763                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187763                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1443287                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1443287                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819540                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       819540                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1443287                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1007303                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2450590                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1443287                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1007303                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2450590                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           17                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       116544                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116544                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16406                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        16406                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272166                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       272166                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        16406                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       388710                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        405116                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        16403                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388713                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        16406                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       388710                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       405116                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       253000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       253000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8935872000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8935872000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1324497500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1324497500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19726651500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  19726651500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1324497500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  28662523500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  29987021000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1324497500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  28662523500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  29987021000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       838228                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       838228                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           20                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304302                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304302                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1459636                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1459636                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091656                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1091656                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1459636                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1395958                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2855594                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1459636                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1395958                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2855594                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.800000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.800000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382955                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.382955                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011238                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011238                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249327                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249327                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011238                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.278456                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.141868                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011238                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.278456                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.141868                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15812.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15812.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76680.385124                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76680.385124                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80747.271841                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80747.271841                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72476.757942                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72476.757942                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80747.271841                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73736.982041                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74020.826134                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80747.271841                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73736.982041                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74020.826134                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8923529500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8923529500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1314713000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1314713000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19729862500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  19729862500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1314713000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  28653392000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  29968105000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1314713000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  28653392000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  29968105000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       838310                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       838310                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           21                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304307                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304307                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1459693                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1459693                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091706                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1091706                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1459693                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1396013                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2855706                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1459693                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1396013                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2855706                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809524                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382982                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.382982                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011239                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011239                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249303                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249303                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011239                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.278443                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.141862                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011239                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.278443                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.141862                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14882.352941                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14882.352941                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76567.901393                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76567.901393                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80136.108741                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80136.108741                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72492.017739                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72492.017739                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80136.108741                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73714.059324                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73974.133335                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80136.108741                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73714.059324                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73974.133335                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -801,126 +800,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76513                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76513                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        76511                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76511                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          317                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          317                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116534                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116534                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16403                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16403                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272179                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272179                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16403                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388713                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           17                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116544                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116544                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16406                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16406                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272166                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272166                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16406                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       388710                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       405116                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16403                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388713                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16406                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       388710                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       405116                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16555                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16555                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       431000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       431000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7770532000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7770532000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1160467500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1160467500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17006826000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17006826000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1160467500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  24777358000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  25937825500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1160467500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  24777358000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  25937825500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1364748500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1364748500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1931469000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1931469000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3296217500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3296217500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9620                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9620                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16550                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16550                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       453499                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       453499                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7758089500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7758089500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1150653000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1150653000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17010167000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17010167000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1150653000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  24768256500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  25918909500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1150653000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  24768256500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  25918909500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1363977000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1363977000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1930958000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1930958000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3294935000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3294935000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.800000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382955                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382955                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011238                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011238                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249327                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249327                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011238                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278456                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.141868                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011238                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278456                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809524                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382982                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382982                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011239                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011239                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249303                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249303                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011239                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278443                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.141862                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011239                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278443                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.141862                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq           6934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2558426                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9621                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9621                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       956270                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2277118                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304302                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304302                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1459696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091829                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2558531                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9620                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9620                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       956362                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2277135                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304307                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304307                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1459755                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091879                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4377747                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219297                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8597044                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93416704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143041221                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          236457925                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      422839                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6149292                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4377903                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219455                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8597358                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93420352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143049956                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          236470308                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      422854                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6149527                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        1.068727                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.252990                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.252989                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5726669     93.13%     93.13% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             422623      6.87%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5726891     93.13%     93.13% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             422636      6.87%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6149292                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3706373000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        6149527                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3706565999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2189771045                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2189850563                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2105677995                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2105755497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -934,43 +933,43 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7107                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7107                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51173                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51173                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5104                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51172                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51172                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5096                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33110                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33100                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116560                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20416                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116550                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20384                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44357                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44324                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705965                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4712000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705932                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              4707000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -984,7 +983,7 @@ system.iobus.reqLayer23.occupancy            13484000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5167000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
@@ -992,23 +991,23 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           216063756                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216043265                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23489000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23480000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.294607                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.302220                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1729988854000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.294607                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.080913                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.080913                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1729987199000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.302220                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.081389                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.081389                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1024,8 +1023,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21637883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21637883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4907200873                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4907200873                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4908791382                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4908791382                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21637883                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21637883                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21637883                       # number of overall miss cycles
@@ -1048,17 +1047,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 125074.468208                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 125074.468208                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 125074.468208                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs             6                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1074,8 +1073,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          173
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12987883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     12987883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2829600873                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2829600873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2831191382                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2831191382                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     12987883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     12987883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     12987883                       # number of overall MSHR miss cycles
@@ -1090,61 +1089,61 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                6934                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295673                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9621                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9621                       # Transaction distribution
-system.membus.trans_dist::Writeback            118025                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262175                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              156                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             156                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116394                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116394                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288755                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295659                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9620                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9620                       # Transaction distribution
+system.membus.trans_dist::Writeback            118023                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262178                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              157                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             157                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116404                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116404                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        288745                       # Transaction distribution
 system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33110                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148635                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181774                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181767                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1306591                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44357                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30796800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30841157                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1306584                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44324                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30796672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30840996                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33498885                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33498724                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              433                       # Total snoops (count)
-system.membus.snoop_fanout::samples            843789                       # Request fanout histogram
+system.membus.snoop_fanout::samples            843798                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  843789    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  843798    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              843789                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29576000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              843798                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29290000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1318697936                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1318757186                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy               20500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2160007596                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2160035845                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           72031934                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72019946                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 2b4d92c81..08ac5b1cf 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -166,7 +166,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -513,7 +513,7 @@ opLat=3
 pipelined=false
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -671,7 +671,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -1018,7 +1018,7 @@ opLat=3
 pipelined=false
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1151,7 +1151,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -1186,7 +1186,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index e5b1b4540..7571a76a8 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,123 +1,123 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.907980                       # Number of seconds simulated
-sim_ticks                                1907980084000                       # Number of ticks simulated
-final_tick                               1907980084000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.906957                       # Number of seconds simulated
+sim_ticks                                1906956794000                       # Number of ticks simulated
+final_tick                               1906956794000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 144634                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144633                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4918211693                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 381420                       # Number of bytes of host memory used
-host_seconds                                   387.94                       # Real time elapsed on the host
-sim_insts                                    56109384                       # Number of instructions simulated
-sim_ops                                      56109384                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 101212                       # Simulator instruction rate (inst/s)
+host_op_rate                                   101212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3411514986                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 375140                       # Number of bytes of host memory used
+host_seconds                                   558.98                       # Real time elapsed on the host
+sim_insts                                    56575230                       # Number of instructions simulated
+sim_ops                                      56575230                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           744000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24138496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           236608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1227584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           862400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24773696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           117248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           514752                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26347648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       744000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       236608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          980608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7952896                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7952896                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11625                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            377164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3697                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             19181                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26269056                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       862400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       117248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          979648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7861568                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7861568                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13475                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            387089                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1832                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8043                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                411682                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124264                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               124264                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              389941                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12651335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              124010                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              643395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                410454                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          122837                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122837                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              452239                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12991220                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               61484                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              269934                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13809184                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         389941                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         124010                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             513951                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4168228                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4168228                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4168228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             389941                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12651335                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             124010                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             643395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13775381                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         452239                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          61484                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             513723                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4122573                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4122573                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4122573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             452239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12991220                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              61484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             269934                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17977412                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        411682                       # Number of read requests accepted
-system.physmem.writeReqs                       124264                       # Number of write requests accepted
-system.physmem.readBursts                      411682                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     124264                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26340672                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7951552                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26347648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7952896                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               17897953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        410454                       # Number of read requests accepted
+system.physmem.writeReqs                       122837                       # Number of write requests accepted
+system.physmem.readBursts                      410454                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     122837                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26260992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7860160                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26269056                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7861568                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      126                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          45002                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25908                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25789                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               26010                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25614                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25643                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25797                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25922                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25550                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25897                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25701                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25484                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25508                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25696                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25817                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25547                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25690                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7970                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7556                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7711                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7606                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7633                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7951                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7934                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7815                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8060                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8044                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7565                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7446                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7634                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8000                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7754                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7564                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          46373                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               26161                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25973                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               26108                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25765                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25066                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25574                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25905                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25241                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25825                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               26325                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25290                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25205                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25472                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25390                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25632                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25396                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8442                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7958                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8052                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7723                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7027                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7199                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7428                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6815                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7536                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7897                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7294                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7366                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7733                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8096                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8387                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7862                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1907975777500                       # Total gap between requests
+system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1906952476500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  411682                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  410454                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124264                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317784                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     38583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29989                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     25130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        71                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 122837                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317312                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     38231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29670                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     25010                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        81                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
@@ -158,204 +158,187 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    10048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       46                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65129                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      526.524774                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     320.940318                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     415.518091                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14691     22.56%     22.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11476     17.62%     40.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5283      8.11%     48.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3332      5.12%     53.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2563      3.94%     57.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1696      2.60%     59.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1442      2.21%     62.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1386      2.13%     64.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23260     35.71%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65129                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5620                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        73.233096                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2814.761745                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5617     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1598                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8838                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6086                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64857                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      526.098216                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     319.146393                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.677441                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14983     23.10%     23.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11330     17.47%     40.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5177      7.98%     48.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3304      5.09%     53.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2428      3.74%     57.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1616      2.49%     59.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1474      2.27%     62.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1311      2.02%     64.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        23234     35.82%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64857                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5518                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        74.361182                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2842.300525                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5515     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5620                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5620                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.107295                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.769658                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.265728                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4863     86.53%     86.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             151      2.69%     89.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             190      3.38%     92.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              20      0.36%     92.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              26      0.46%     93.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              52      0.93%     94.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              14      0.25%     94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               7      0.12%     94.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               2      0.04%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.04%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.11%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.12%     95.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               8      0.14%     95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.09%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.05%     95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.05%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               8      0.14%     95.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               8      0.14%     95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              26      0.46%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              16      0.28%     96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           144      2.56%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            12      0.21%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.04%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.04%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.02%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.07%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.04%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.04%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.05%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             6      0.11%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             3      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             7      0.12%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             2      0.04%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             5      0.09%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5620                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4128600500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11845594250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2057865000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10031.27                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5518                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5518                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.257158                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.834122                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.444866                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4906     88.91%     88.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             212      3.84%     92.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              76      1.38%     94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              18      0.33%     94.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               5      0.09%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               9      0.16%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               6      0.11%     94.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              17      0.31%     95.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              11      0.20%     95.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              35      0.63%     95.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            173      3.14%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             8      0.14%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.02%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.02%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             6      0.11%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             2      0.04%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             2      0.04%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             6      0.11%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             5      0.09%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.04%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.09%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             6      0.11%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             4      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5518                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4043689250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11737339250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2051640000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9854.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28781.27                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.81                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.81                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.17                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28604.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.12                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.21                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.72                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     370844                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99842                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.35                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3560014.96                       # Average gap between requests
-system.physmem.pageHitRate                      87.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  245019600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133691250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1608188400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                402589440                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124619576640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            57486510675                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1094357699250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1278853275255                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.267627                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1820391723000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63711440000                       # Time in different power states
+system.physmem.avgRdQLen                         2.27                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.58                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     369741                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98545                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.11                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3575819.72                       # Average gap between requests
+system.physmem.pageHitRate                      87.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  242910360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132540375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1605185400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392973120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           124552955280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            57318973425                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1093892654250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1278138192210                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.251160                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1819616623000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63677380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     23872193000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23660103250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  247287600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  134928750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1601652000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                402194160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124619576640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            57648050955                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1094215997250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1278869687355                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.276229                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1820158780750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63711440000                       # Time in different power states
+system.physmem_1.actEnergy                  247408560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134994750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1595373000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                402868080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           124552955280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            57679570530                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1093576349250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1278189519450                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.278071                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1819088073250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63677380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     24103898000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     24188666750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups               11788808                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         10301623                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           235567                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             7623393                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                4144660                       # Number of BTB hits
+system.cpu0.branchPred.lookups               16421216                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14369135                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           322041                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            10416019                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                5388507                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            54.367655                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 590548                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             12472                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            51.732884                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 814349                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             18392                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7021210                       # DTB read hits
-system.cpu0.dtb.read_misses                     28922                       # DTB read misses
+system.cpu0.dtb.read_hits                     9282981                       # DTB read hits
+system.cpu0.dtb.read_misses                     32197                       # DTB read misses
 system.cpu0.dtb.read_acv                          549                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  680178                       # DTB read accesses
-system.cpu0.dtb.write_hits                    4516223                       # DTB write hits
-system.cpu0.dtb.write_misses                     6969                       # DTB write misses
-system.cpu0.dtb.write_acv                         383                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 234540                       # DTB write accesses
-system.cpu0.dtb.data_hits                    11537433                       # DTB hits
-system.cpu0.dtb.data_misses                     35891                       # DTB misses
-system.cpu0.dtb.data_acv                          932                       # DTB access violations
-system.cpu0.dtb.data_accesses                  914718                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1192769                       # ITB hits
-system.cpu0.itb.fetch_misses                    29243                       # ITB misses
-system.cpu0.itb.fetch_acv                         632                       # ITB acv
-system.cpu0.itb.fetch_accesses                1222012                       # ITB accesses
+system.cpu0.dtb.read_accesses                  681404                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5956980                       # DTB write hits
+system.cpu0.dtb.write_misses                     7300                       # DTB write misses
+system.cpu0.dtb.write_acv                         382                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 235779                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15239961                       # DTB hits
+system.cpu0.dtb.data_misses                     39497                       # DTB misses
+system.cpu0.dtb.data_acv                          931                       # DTB access violations
+system.cpu0.dtb.data_accesses                  917183                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1451467                       # ITB hits
+system.cpu0.itb.fetch_misses                    20802                       # ITB misses
+system.cpu0.itb.fetch_acv                         603                       # ITB acv
+system.cpu0.itb.fetch_accesses                1472269                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -368,598 +351,598 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                        94258709                       # number of cpu cycles simulated
+system.cpu0.numCycles                       115722397                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          18560589                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      53027757                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   11788808                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           4735208                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     69979824                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                 806070                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                       422                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               25803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      1456351                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       296845                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          178                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  6342869                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               170274                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          90723047                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.584501                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.854201                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          26666578                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      71121267                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   16421216                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6202856                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     81967119                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1079386                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       563                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               29093                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       971886                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       464461                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8198819                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               234916                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples         110639677                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.642819                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.946891                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                80634947     88.88%     88.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  672953      0.74%     89.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1448081      1.60%     91.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  584574      0.64%     91.86% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2111688      2.33%     94.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  463915      0.51%     94.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  450869      0.50%     95.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  614781      0.68%     95.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3741239      4.12%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                97354556     87.99%     87.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  847860      0.77%     88.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1824694      1.65%     90.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  789927      0.71%     91.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2609447      2.36%     93.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  576925      0.52%     94.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  654110      0.59%     94.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  850099      0.77%     95.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 5132059      4.64%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            90723047                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.125069                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.562577                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                14977569                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             67686915                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  6257157                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1423439                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                377966                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              370983                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                25389                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              46677806                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                79994                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                377966                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                15660908                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               46083028                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      14369152                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  6948168                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              7283823                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              45068314                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               191995                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1547824                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                115834                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               4229403                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           30289226                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             55138176                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        55047778                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            82793                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             26689501                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 3599717                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1126936                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        168790                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 10038208                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             7066684                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            4739993                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1073845                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          760534                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  40346624                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1418133                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 39715880                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            51531                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        4979263                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2318512                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        978590                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     90723047                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.437771                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.168840                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           110639677                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.141902                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.614585                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                21680681                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             78105435                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8575313                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1774700                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                503547                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              522363                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                36577                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              62219552                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               111460                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                503547                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                22526069                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               50558199                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      19082823                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9419071                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              8549966                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              60053732                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               197896                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2013708                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                145060                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               4631346                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           40115150                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             72965738                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        72822559                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           133404                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             35357429                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4757713                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1490349                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        215164                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12632454                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9363221                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6214194                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1348186                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          960020                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  53527289                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1914294                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 52757497                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            50335                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6507909                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2851663                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1318911                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    110639677                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.476841                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.213091                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           74240349     81.83%     81.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            7278177      8.02%     89.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3014429      3.32%     93.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2002130      2.21%     95.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2057446      2.27%     97.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1059416      1.17%     98.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             709655      0.78%     99.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             273899      0.30%     99.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              87546      0.10%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           88942477     80.39%     80.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9398072      8.49%     88.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3917958      3.54%     92.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2747278      2.48%     94.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2855598      2.58%     97.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1392573      1.26%     98.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             913992      0.83%     99.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             361366      0.33%     99.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             110363      0.10%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       90723047                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      110639677                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 128942     17.20%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     17.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                362987     48.42%     65.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               257779     34.38%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 181613     18.32%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                474655     47.88%     66.21% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               334992     33.79%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             3788      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             27155018     68.37%     68.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               40485      0.10%     68.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              25259      0.06%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             7282480     18.34%     86.89% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            4576355     11.52%     98.41% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            630612      1.59%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             36170574     68.56%     68.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57549      0.11%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              28793      0.05%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9634233     18.26%     87.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6027526     11.42%     98.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            833151      1.58%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              39715880                       # Type of FU issued
-system.cpu0.iq.rate                          0.421350                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     749708                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.018877                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         170597233                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         46586090                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     38643243                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             358812                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            172505                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       165745                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              40269961                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 191839                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          469267                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              52757497                       # Type of FU issued
+system.cpu0.iq.rate                          0.455897                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     991260                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.018789                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         216609620                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         61691492                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     51347656                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             586645                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            275208                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       269627                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              53428897                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 316072                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          584424                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads       864378                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3380                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        14864                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       401917                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1070558                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2876                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        17548                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       473318                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        11804                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       365714                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18682                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       412098                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                377966                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               43619498                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               675796                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           44202753                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            88904                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              7066684                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             4739993                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1257449                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 23012                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               538948                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         14864                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        117466                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       265776                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              383242                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             39342618                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              7067139                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           373261                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                503547                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               47448039                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               802619                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           58859222                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           120684                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9363221                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6214194                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1691778                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 39350                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               562336                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         17548                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        158131                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       358107                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              516238                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             52248436                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9338690                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           509060                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      2437996                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    11599884                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 6171265                       # Number of branches executed
-system.cpu0.iew.exec_stores                   4532745                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.417390                       # Inst execution rate
-system.cpu0.iew.wb_sent                      38908729                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     38808988                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 20149850                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 27578035                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3417639                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15316719                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8298030                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5978029                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.451498                       # Inst execution rate
+system.cpu0.iew.wb_sent                      51729756                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     51617283                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26562977                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36791821                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.411728                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.730649                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.446044                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.721980                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        5183738                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         439543                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           349838                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     89803768                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.433386                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.354442                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6839384                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         595383                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           473671                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    109429659                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.474443                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.410223                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     76032999     84.67%     84.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      5542678      6.17%     90.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      2869062      3.19%     94.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1578965      1.76%     95.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1284314      1.43%     97.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       412798      0.46%     97.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       324191      0.36%     98.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       314453      0.35%     98.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1444308      1.61%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     91094862     83.25%     83.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7261881      6.64%     89.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3995871      3.65%     93.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2069124      1.89%     95.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1633444      1.49%     96.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       582030      0.53%     97.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       441609      0.40%     97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       443115      0.40%     98.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1907723      1.74%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     89803768                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            38919724                       # Number of instructions committed
-system.cpu0.commit.committedOps              38919724                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    109429659                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            51918164                       # Number of instructions committed
+system.cpu0.commit.committedOps              51918164                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      10540382                       # Number of memory references committed
-system.cpu0.commit.loads                      6202306                       # Number of loads committed
-system.cpu0.commit.membars                     144405                       # Number of memory barriers committed
-system.cpu0.commit.branches                   5839773                       # Number of branches committed
-system.cpu0.commit.fp_insts                    162063                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 36166381                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              471449                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2138002      5.49%      5.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        25394964     65.25%     70.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          39484      0.10%     70.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         24801      0.06%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        6346711     16.31%     87.22% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       4343267     11.16%     98.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       630612      1.62%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      14033539                       # Number of memory references committed
+system.cpu0.commit.loads                      8292663                       # Number of loads committed
+system.cpu0.commit.membars                     202804                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7846921                       # Number of branches committed
+system.cpu0.commit.fp_insts                    266538                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 48077974                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              666824                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2988262      5.76%      5.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        33767854     65.04%     70.80% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          56339      0.11%     70.90% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.90% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         28331      0.05%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.96% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8495467     16.36%     87.33% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5746879     11.07%     98.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       833149      1.60%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         38919724                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1444308                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   132264444                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   89122078                       # The number of ROB writes
-system.cpu0.timesIdled                         337516                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3535662                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3721701460                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   36785489                       # Number of Instructions Simulated
-system.cpu0.committedOps                     36785489                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.562388                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.562388                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.390261                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.390261                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                51878765                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               28204778                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    81728                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   81429                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1387632                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                636485                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           898491                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          481.994698                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            8012262                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           899003                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.912386                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         26393500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.994698                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.941396                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.941396                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         51918164                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1907723                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   166079481                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  118719518                       # The number of ROB writes
+system.cpu0.timesIdled                         511712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5082720                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3698191192                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   48933669                       # Number of Instructions Simulated
+system.cpu0.committedOps                     48933669                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.364883                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.364883                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.422854                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.422854                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                68649325                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               37335516                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   132501                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  134063                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1824055                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                833586                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          1296864                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.135915                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10665502                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1297376                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.220826                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         26097500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.135915                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988547                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988547                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          236                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          224                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         43230678                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        43230678                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5046736                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5046736                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      2679789                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       2679789                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       129628                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       129628                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149296                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149296                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7726525                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         7726525                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7726525                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        7726525                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1067598                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1067598                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1496200                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1496200                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12202                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        12202                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          769                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          769                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2563798                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2563798                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2563798                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2563798                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  32014122500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  32014122500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  69455032918                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  69455032918                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    190587000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    190587000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      5445000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      5445000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 101469155418                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 101469155418                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6114334                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6114334                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4175989                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4175989                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       141830                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       141830                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       150065                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       150065                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     10290323                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     10290323                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     10290323                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     10290323                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.174606                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.174606                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.358286                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.358286                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086033                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086033                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.005124                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.005124                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.249147                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.249147                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.249147                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.249147                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7080.624187                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7080.624187                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      4094264                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         5021                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           103728                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             94                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    39.471155                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    53.414894                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         57664711                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        57664711                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6558537                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6558537                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3738792                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3738792                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       165967                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       165967                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191452                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       191452                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10297329                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10297329                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10297329                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10297329                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1618045                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1618045                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1793563                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1793563                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21339                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21339                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2425                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2425                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3411608                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3411608                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3411608                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3411608                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  39371994500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  39371994500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  77781772548                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  77781772548                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    331348500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    331348500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20480000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     20480000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 117153767048                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 117153767048                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8176582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8176582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5532355                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5532355                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       187306                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       187306                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       193877                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       193877                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13708937                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13708937                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13708937                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13708937                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197888                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.197888                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.324195                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.324195                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.113926                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.113926                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.012508                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.012508                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248860                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.248860                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248860                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.248860                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8445.360825                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8445.360825                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      4364063                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         4809                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           121083                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             97                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    36.041913                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    49.577320                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       426068                       # number of writebacks
-system.cpu0.dcache.writebacks::total           426068                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       384761                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       384761                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1282051                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1282051                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3514                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3514                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1666812                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1666812                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1666812                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1666812                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       682837                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       682837                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       214149                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       214149                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8688                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8688                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          769                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          769                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       896986                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       896986                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       896986                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       896986                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         4777                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         4777                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         8020                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         8020                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        12797                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        12797                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25205904500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25205904500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10851652245                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10851652245                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    107603000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    107603000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      4676000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      4676000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36057556745                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  36057556745                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36057556745                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  36057556745                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1013290500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1013290500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1707574498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1707574498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2720864998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2720864998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.111678                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.111678                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051281                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051281                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061256                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061256                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.005124                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.005124                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.087168                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.087168                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.087168                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.087168                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6080.624187                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6080.624187                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       766891                       # number of writebacks
+system.cpu0.dcache.writebacks::total           766891                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       594303                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       594303                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1523628                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1523628                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5200                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5200                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2117931                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2117931                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2117931                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2117931                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1023742                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1023742                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       269935                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       269935                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16139                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16139                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2425                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2425                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1293677                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1293677                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1293677                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1293677                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7035                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7035                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10024                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10024                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17059                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17059                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  29563027500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  29563027500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  12280270109                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12280270109                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    188351000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    188351000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     18055000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     18055000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  41843297609                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  41843297609                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  41843297609                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  41843297609                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1480741500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1480741500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2153066498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2153066498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3633807998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3633807998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125204                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125204                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048792                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048792                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086164                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086164                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.012508                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.012508                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094367                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.094367                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094367                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.094367                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7445.360825                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7445.360825                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           615978                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.684225                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            5692804                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           616490                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             9.234220                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      28149663500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.684225                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.993524                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.993524                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           927295                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.382377                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            7224199                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           927807                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             7.786317                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      28149280500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.382377                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994887                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.994887                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          430                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          427                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          6959538                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         6959538                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      5692804                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        5692804                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      5692804                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         5692804                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      5692804                       # number of overall hits
-system.cpu0.icache.overall_hits::total        5692804                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       650065                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       650065                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       650065                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        650065                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       650065                       # number of overall misses
-system.cpu0.icache.overall_misses::total       650065                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9309214992                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   9309214992                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   9309214992                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   9309214992                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   9309214992                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   9309214992                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      6342869                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      6342869                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      6342869                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      6342869                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      6342869                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      6342869                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.102488                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.102488                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.102488                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.102488                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.102488                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.102488                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14320.437175                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14320.437175                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3481                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          9126911                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         9126911                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7224199                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7224199                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7224199                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7224199                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7224199                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7224199                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       974618                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       974618                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       974618                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        974618                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       974618                       # number of overall misses
+system.cpu0.icache.overall_misses::total       974618                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13621983991                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13621983991                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13621983991                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13621983991                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13621983991                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13621983991                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8198817                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8198817                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8198817                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8198817                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8198817                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8198817                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.118873                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.118873                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.118873                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.118873                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.118873                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.118873                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13976.741647                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13976.741647                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         5225                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              166                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              203                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    20.969880                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.738916                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        33396                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        33396                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        33396                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        33396                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        33396                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        33396                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       616669                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       616669                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       616669                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       616669                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       616669                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       616669                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8251915495                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8251915495                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8251915495                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8251915495                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8251915495                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8251915495                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.097222                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.097222                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.097222                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.097222                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.097222                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.097222                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        46524                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        46524                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        46524                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        46524                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        46524                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        46524                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       928094                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       928094                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       928094                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       928094                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       928094                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       928094                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12135046494                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12135046494                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12135046494                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12135046494                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12135046494                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12135046494                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.113199                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.113199                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.113199                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.113199                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.113199                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.113199                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                7710185                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          6710334                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           163097                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             4502045                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                2070765                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3314305                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2896651                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect            61906                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             1740825                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 779195                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            45.996097                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 394984                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             11166                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            44.760099                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 157645                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              4636                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     4026297                       # DTB read hits
-system.cpu1.dtb.read_misses                     14233                       # DTB read misses
-system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  293572                       # DTB read accesses
-system.cpu1.dtb.write_hits                    2497972                       # DTB write hits
-system.cpu1.dtb.write_misses                     2408                       # DTB write misses
-system.cpu1.dtb.write_acv                          37                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 109195                       # DTB write accesses
-system.cpu1.dtb.data_hits                     6524269                       # DTB hits
-system.cpu1.dtb.data_misses                     16641                       # DTB misses
-system.cpu1.dtb.data_acv                           43                       # DTB access violations
-system.cpu1.dtb.data_accesses                  402767                       # DTB accesses
-system.cpu1.itb.fetch_hits                     750930                       # ITB hits
-system.cpu1.itb.fetch_misses                     5383                       # ITB misses
-system.cpu1.itb.fetch_acv                          53                       # ITB acv
-system.cpu1.itb.fetch_accesses                 756313                       # ITB accesses
+system.cpu1.dtb.read_hits                     1755656                       # DTB read hits
+system.cpu1.dtb.read_misses                      9508                       # DTB read misses
+system.cpu1.dtb.read_acv                            5                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  286377                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1073642                       # DTB write hits
+system.cpu1.dtb.write_misses                     1995                       # DTB write misses
+system.cpu1.dtb.write_acv                          40                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 108795                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2829298                       # DTB hits
+system.cpu1.dtb.data_misses                     11503                       # DTB misses
+system.cpu1.dtb.data_acv                           45                       # DTB access violations
+system.cpu1.dtb.data_accesses                  395172                       # DTB accesses
+system.cpu1.itb.fetch_hits                     497795                       # ITB hits
+system.cpu1.itb.fetch_misses                     4809                       # ITB misses
+system.cpu1.itb.fetch_acv                          84                       # ITB acv
+system.cpu1.itb.fetch_accesses                 502604                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -972,564 +955,563 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        34369930                       # number of cpu cycles simulated
+system.cpu1.numCycles                        13378620                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          13361598                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      30714280                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    7710185                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           2465749                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     18120966                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 547594                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                        46                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               23797                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       211021                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       198154                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           54                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  3304195                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               117193                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          32189433                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.954173                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.349586                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           5528968                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      12732566                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3314305                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches            936840                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      6841586                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 246622                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles               24765                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       177717                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        60433                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1438917                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                48462                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          12756788                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.998101                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.406721                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                26750456     83.10%     83.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  307184      0.95%     84.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  618506      1.92%     85.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  382121      1.19%     87.17% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  801179      2.49%     89.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  249293      0.77%     90.43% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  334783      1.04%     91.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  403446      1.25%     92.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 2342465      7.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                10526481     82.52%     82.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  138708      1.09%     83.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  230541      1.81%     85.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  169879      1.33%     86.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  284565      2.23%     88.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  115144      0.90%     89.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  131557      1.03%     90.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  159487      1.25%     92.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1000426      7.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            32189433                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.224329                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.893638                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                11124412                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             16339992                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  3934359                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               534571                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                256098                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              250042                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                17822                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              25897409                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                55799                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                256098                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                11423416                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                4918911                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       9329125                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  4131002                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2130879                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              24789451                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 5724                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                540758                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 43054                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                820253                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           16289258                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             29487961                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        29391972                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            88964                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             13777657                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 2511601                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            753305                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         82405                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  4252225                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             4127805                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            2629581                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           507300                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          331297                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  21789875                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             948507                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 21283611                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            28389                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        3414486                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      1484281                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        680406                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     32189433                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.661199                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.387208                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            12756788                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.247731                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.951710                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 4581654                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              6264793                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  1608431                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               184437                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                117472                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved               99495                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 5921                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              10317942                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                18589                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                117472                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 4714026                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 446929                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       4987547                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  1661018                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               829794                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts               9788331                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 3632                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 64825                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 14992                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                371131                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            6443318                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             11674537                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        11622438                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            46696                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              5463726                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                  979592                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            407944                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         36440                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  1686696                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             1800249                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1144526                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           213224                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          121752                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                   8623787                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             466284                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                  8415044                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            20175                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1448509                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       669329                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        345933                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     12756788                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.659652                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.379213                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           23533399     73.11%     73.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            3630192     11.28%     84.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            1573878      4.89%     89.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            1186258      3.69%     92.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            1178148      3.66%     96.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             546160      1.70%     98.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             337865      1.05%     99.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             151957      0.47%     99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              51576      0.16%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0            9236176     72.40%     72.40% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1557417     12.21%     84.61% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             656816      5.15%     89.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             459502      3.60%     93.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             405096      3.18%     96.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             217416      1.70%     98.24% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             137120      1.07%     99.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              62655      0.49%     99.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              24590      0.19%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       32189433                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       12756788                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  80499     16.46%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     16.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                246874     50.47%     66.92% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               161807     33.08%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  22931      9.91%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.91% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                125391     54.21%     64.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                82988     35.88%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3518      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             14071465     66.11%     66.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               30174      0.14%     66.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              13456      0.06%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             4194422     19.71%     86.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            2532925     11.90%     97.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            435892      2.05%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3518      0.04%      0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              5217804     62.01%     62.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               14291      0.17%     62.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10471      0.12%     62.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             1829208     21.74%     84.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1094853     13.01%     97.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            243140      2.89%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              21283611                       # Type of FU issued
-system.cpu1.iq.rate                          0.619251                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     489180                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.022984                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          74907239                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         25989017                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     20583813                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             366985                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            171482                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       168729                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              21571772                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 197501                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          207443                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total               8415044                       # Type of FU issued
+system.cpu1.iq.rate                          0.628992                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     231310                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.027488                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          29661025                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         10457474                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses      8106737                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             177336                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             85037                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        82464                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses               8548271                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                  94565                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           87834                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       572592                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         1888                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         7837                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       247159                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       257024                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          716                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         4046                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       124034                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads         7441                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       131088                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          425                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        63290                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                256098                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                4050515                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               319306                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           24169619                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            59065                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              4127805                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             2629581                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            846465                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 33159                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               202940                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          7837                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         80858                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       187737                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              268595                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             21021510                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              4051663                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           262101                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                117472                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 288545                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               130999                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts            9554579                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            24166                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              1800249                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1144526                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            424658                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  4139                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               125975                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          4046                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         28597                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        88577                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              117174                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts              8309020                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              1771054                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           106024                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                      1431237                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     6560061                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 3322997                       # Number of branches executed
-system.cpu1.iew.exec_stores                   2508398                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.611625                       # Inst execution rate
-system.cpu1.iew.wb_sent                      20805592                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     20752542                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 10210202                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 14612629                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       464508                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     2851870                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1230259                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1080816                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.621067                       # Inst execution rate
+system.cpu1.iew.wb_sent                       8217653                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                      8189201                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  3916216                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  5553340                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.603799                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.698725                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.612111                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.705200                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        3582987                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         268101                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           243613                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     31565232                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.650241                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.623237                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1470840                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         120351                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           107539                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     12487025                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.642311                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.620138                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     24282945     76.93%     76.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      2976975      9.43%     86.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1587723      5.03%     91.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       771361      2.44%     93.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       532421      1.69%     95.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       258990      0.82%     96.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       207817      0.66%     97.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       189047      0.60%     97.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       757953      2.40%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0      9576588     76.69%     76.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1351659     10.82%     87.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       487280      3.90%     91.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       294734      2.36%     93.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       217151      1.74%     95.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        92181      0.74%     96.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6        81385      0.65%     96.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        96065      0.77%     97.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       289982      2.32%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     31565232                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            20524993                       # Number of instructions committed
-system.cpu1.commit.committedOps              20524993                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     12487025                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts             8020551                       # Number of instructions committed
+system.cpu1.commit.committedOps               8020551                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       5937635                       # Number of memory references committed
-system.cpu1.commit.loads                      3555213                       # Number of loads committed
-system.cpu1.commit.membars                      92415                       # Number of memory barriers committed
-system.cpu1.commit.branches                   3082130                       # Number of branches committed
-system.cpu1.commit.fp_insts                    166998                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 18893824                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              318960                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass      1204616      5.87%      5.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        12808497     62.40%     68.27% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          29745      0.14%     68.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     68.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         13451      0.07%     68.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     68.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     68.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     68.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          1759      0.01%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        3647628     17.77%     86.26% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       2383405     11.61%     97.88% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       435892      2.12%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       2563717                       # Number of memory references committed
+system.cpu1.commit.loads                      1543225                       # Number of loads committed
+system.cpu1.commit.membars                      37500                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1142801                       # Number of branches committed
+system.cpu1.commit.fp_insts                     80747                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  7435629                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              128494                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       382508      4.77%      4.77% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         4766897     59.43%     64.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          14118      0.18%     64.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         10465      0.13%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          1759      0.02%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        1580725     19.71%     84.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1020940     12.73%     96.97% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       243139      3.03%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         20524993                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               757953                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    54833276                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   48835744                       # The number of ROB writes
-system.cpu1.timesIdled                         276866                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2180497                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3780899978                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   19323895                       # Number of Instructions Simulated
-system.cpu1.committedOps                     19323895                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.778623                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.778623                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.562233                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.562233                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                27142723                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               14810250                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    88193                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   88824                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                1272248                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                377130                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           561653                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          496.197725                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4717582                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           561970                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs             8.394722                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      37149185000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   496.197725                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.969136                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.969136                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          317                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          317                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.619141                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         24916279                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        24916279                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2844065                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2844065                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1751257                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1751257                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        62172                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        62172                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        69860                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        69860                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      4595322                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         4595322                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      4595322                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        4595322                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       792097                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       792097                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       552973                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       552973                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14160                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        14160                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          786                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          786                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      1345070                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       1345070                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      1345070                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      1345070                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  10154789500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  10154789500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  16820667860                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  16820667860                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    217520000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    217520000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6395000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      6395000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  26975457360                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  26975457360                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  26975457360                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  26975457360                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3636162                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3636162                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2304230                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2304230                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        76332                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        76332                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        70646                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        70646                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      5940392                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      5940392                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      5940392                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      5940392                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.217839                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.217839                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.239982                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.239982                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.185505                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.185505                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.011126                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.011126                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.226428                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.226428                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.226428                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.226428                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8136.132316                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8136.132316                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       765854                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          810                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            36939                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets             18                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.732938                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets           45                       # average number of cycles each access was blocked
+system.cpu1.commit.op_class_0::total          8020551                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               289982                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    21604416                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   19248787                       # The number of ROB writes
+system.cpu1.timesIdled                         107122                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         621832                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3799884834                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    7641561                       # Number of Instructions Simulated
+system.cpu1.committedOps                      7641561                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.750771                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.750771                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.571177                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.571177                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                10694286                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                5846668                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    46070                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   45105                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 889333                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                191018                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements            88757                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          491.801602                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2280391                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs            89062                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            25.604534                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1034185237500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.801602                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960550                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.960550                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          305                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          305                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.595703                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         10633162                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        10633162                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1420631                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1420631                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       810208                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        810208                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        27933                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        27933                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        26395                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        26395                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2230839                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2230839                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2230839                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2230839                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       166361                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       166361                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       175617                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       175617                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4254                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         4254                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2523                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         2523                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       341978                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        341978                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       341978                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       341978                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2085855500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2085855500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6615792667                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   6615792667                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     40341500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     40341500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     21053500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     21053500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   8701648167                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   8701648167                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   8701648167                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   8701648167                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1586992                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1586992                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data       985825                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       985825                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        32187                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        32187                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        28918                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        28918                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      2572817                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      2572817                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      2572817                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      2572817                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.104828                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.104828                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.178142                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.178142                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.132165                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.132165                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.087247                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.087247                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.132920                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.132920                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.132920                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.132920                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9483.192290                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9483.192290                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8344.629409                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8344.629409                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       379425                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          575                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            15060                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             12                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    25.194223                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    47.916667                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       435263                       # number of writebacks
-system.cpu1.dcache.writebacks::total           435263                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       332265                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       332265                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       455576                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       455576                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         2707                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         2707                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       787841                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       787841                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       787841                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       787841                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       459832                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       459832                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        97397                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        97397                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11453                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11453                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          786                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          786                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       557229                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       557229                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       557229                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       557229                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2425                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2425                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4340                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4340                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         6765                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         6765                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   5761115500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   5761115500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2818212839                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2818212839                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    135759000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    135759000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5609000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5609000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8579328339                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   8579328339                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8579328339                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   8579328339                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    499447000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    499447000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    957710500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    957710500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1457157500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1457157500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.126461                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.126461                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.042269                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.042269                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.150042                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.150042                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.011126                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.011126                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.093803                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.093803                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.093803                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.093803                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7136.132316                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7136.132316                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238                       # average overall mshr uncacheable latency
+system.cpu1.dcache.writebacks::writebacks        56462                       # number of writebacks
+system.cpu1.dcache.writebacks::total            56462                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       100117                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       100117                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       144305                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       144305                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          473                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          473                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       244422                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       244422                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       244422                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       244422                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        66244                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        66244                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        31312                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        31312                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         3781                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         3781                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2522                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         2522                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data        97556                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total        97556                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data        97556                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total        97556                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          158                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total          158                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2884                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2884                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3042                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3042                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    801271000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    801271000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1099670460                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1099670460                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     31948000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     31948000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     18531500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     18531500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1900941460                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   1900941460                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1900941460                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   1900941460                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     29727000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     29727000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    636171000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    636171000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    665898000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    665898000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.041742                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.041742                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031762                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.031762                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.117470                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.117470                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.087212                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.087212                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.037918                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.037918                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.037918                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.037918                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8449.616504                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8449.616504                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7347.938144                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7347.938144                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           499853                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          504.618896                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            2783346                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           500364                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             5.562642                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      48744804500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   504.618896                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.985584                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.985584                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          3804626                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         3804626                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      2783351                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        2783351                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      2783351                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         2783351                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      2783351                       # number of overall hits
-system.cpu1.icache.overall_hits::total        2783351                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       520843                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       520843                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       520843                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        520843                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       520843                       # number of overall misses
-system.cpu1.icache.overall_misses::total       520843                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7005360499                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7005360499                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7005360499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7005360499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7005360499                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7005360499                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      3304194                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      3304194                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      3304194                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      3304194                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      3304194                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      3304194                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.157631                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.157631                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.157631                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.157631                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.157631                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.157631                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13450.042525                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13450.042525                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs         1720                       # number of cycles access was blocked
+system.cpu1.icache.tags.replacements           200477                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          470.242239                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1230816                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           200989                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             6.123798                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1882066156500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.242239                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.918442                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.918442                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          1639971                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         1639971                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1230816                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1230816                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1230816                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1230816                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1230816                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1230816                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       208101                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       208101                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       208101                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        208101                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       208101                       # number of overall misses
+system.cpu1.icache.overall_misses::total       208101                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2838828500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   2838828500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   2838828500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   2838828500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   2838828500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   2838828500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1438917                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1438917                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1438917                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1438917                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1438917                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1438917                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.144623                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.144623                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.144623                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.144623                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.144623                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.144623                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13641.589901                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13641.589901                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          462                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               65                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               30                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    26.461538                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.400000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        20411                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        20411                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        20411                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        20411                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        20411                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        20411                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       500432                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       500432                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       500432                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       500432                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       500432                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       500432                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6297993499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6297993499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6297993499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6297993499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6297993499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6297993499                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.151454                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.151454                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.151454                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.151454                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.151454                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.151454                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7047                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         7047                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         7047                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         7047                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         7047                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         7047                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       201054                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       201054                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       201054                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       201054                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       201054                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       201054                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2552554500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   2552554500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2552554500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   2552554500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2552554500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   2552554500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.139726                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.139726                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.139726                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.139726                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.139726                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.139726                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1543,45 +1525,45 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               53912                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              53912                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10518                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7371                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7371                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               54460                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54460                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11610                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        39124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  122578                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        42072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40202                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83460                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83460                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123662                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        46440                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1872                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        68315                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2729939                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              9868000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        72634                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661648                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661648                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2734282                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             10965000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               350000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1593,7 +1575,7 @@ system.iobus.reqLayer23.occupancy            13505000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5167000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
@@ -1601,52 +1583,52 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           216085248                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216128229                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            26764000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27294000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41956000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41701                       # number of replacements
-system.iocache.tags.tagsinuse                0.804902                       # Cycle average of tags in use
+system.iocache.tags.replacements                41698                       # number of replacements
+system.iocache.tags.tagsinuse                0.504095                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41717                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1711319254000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.804902                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.050306                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.050306                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1711315950000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.504095                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.031506                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.031506                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
-system.iocache.tags.data_accesses              375543                       # Number of data accesses
-system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               375570                       # Number of tag accesses
+system.iocache.tags.data_accesses              375570                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
-system.iocache.overall_misses::total              175                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     25392883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     25392883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4907312365                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4907312365                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     25392883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     25392883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     25392883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     25392883                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide          178                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               178                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          178                       # number of overall misses
+system.iocache.overall_misses::total              178                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     22218883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22218883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4907321346                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4907321346                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     22218883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     22218883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     22218883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     22218883                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide          178                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             178                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          178                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            178                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1655,14 +1637,14 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 145102.188571                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 145102.188571                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 145102.188571                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124825.185393                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124825.185393                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124825.185393                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1671,24 +1653,24 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41526                       # number of writebacks
-system.iocache.writebacks::total                41526                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     16642883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16642883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2829712365                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2829712365                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     16642883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16642883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     16642883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16642883                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide          178                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          178                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          178                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          178                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13318883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13318883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2829721346                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2829721346                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13318883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13318883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13318883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13318883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1697,195 +1679,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 95102.188571                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 95102.188571                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74825.185393                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74825.185393                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.725501                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.725501                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74825.185393                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74825.185393                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74825.185393                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74825.185393                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   346141                       # number of replacements
-system.l2c.tags.tagsinuse                65297.340756                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4025883                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   411324                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.787620                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7535768000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53443.709143                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4213.616295                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5688.285915                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1375.831057                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      575.898345                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.815486                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.064295                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.086796                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.020994                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008788                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996358                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65183                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         2225                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5965                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6968                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        49797                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994614                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38794162                       # Number of tag accesses
-system.l2c.tags.data_accesses                38794162                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          861331                       # number of Writeback hits
-system.l2c.Writeback_hits::total               861331                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             141                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              80                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 221                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            38                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            36                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                74                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           115055                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            78240                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               193295                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        604919                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        496677                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1101596                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       403562                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       443803                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           847365                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              604919                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              518617                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              496677                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              522043                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2142256                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             604919                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             518617                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             496677                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             522043                       # number of overall hits
-system.l2c.overall_hits::total                2142256                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          2583                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           538                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3121                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           69                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          100                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             169                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         105448                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          17488                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122936                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        11627                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         3714                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           15341                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       272098                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         2179                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         274277                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             11627                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            377546                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3714                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             19667                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                412554                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11627                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           377546                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3714                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            19667                       # number of overall misses
-system.l2c.overall_misses::total               412554                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1390000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      1722000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      3112000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       341500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       214500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       556000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   9317536000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1807849000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11125385000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst    964295500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    315495500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1279791000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  19840935500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    172644000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  20013579500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    964295500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  29158471500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    315495500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1980493000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     32418755500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    964295500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  29158471500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    315495500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1980493000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    32418755500                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks       861331                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           861331                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2724                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          618                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3342                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          107                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          136                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           243                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       220503                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        95728                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           316231                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       616546                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       500391                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1116937                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       675660                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       445982                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1121642                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          616546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          896163                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          500391                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          541710                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2554810                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         616546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         896163                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         500391                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         541710                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2554810                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.948238                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.870550                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.933872                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.644860                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.735294                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.695473                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.478216                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.182684                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.388754                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.018858                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007422                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013735                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.402714                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.004886                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.244532                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018858                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.421292                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007422                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.036305                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.161481                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018858                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.421292                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007422                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.036305                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.161481                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   538.133953                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3200.743494                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   997.116309                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4949.275362                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data         2145                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3289.940828                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88361.429330                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103376.543916                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 90497.372617                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82935.881999                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84947.630587                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 83422.918975                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72918.343758                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 79230.839835                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 72968.493530                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82935.881999                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 77231.573106                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84947.630587                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 100701.327096                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 78580.635505                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82935.881999                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 77231.573106                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84947.630587                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 100701.327096                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 78580.635505                       # average overall miss latency
+system.l2c.tags.replacements                   344930                       # number of replacements
+system.l2c.tags.tagsinuse                65239.787598                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3999339                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   410104                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.752012                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               7535462000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   53414.062989                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5366.108277                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6187.949092                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      208.288223                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       63.379017                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.815034                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.081880                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.094421                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.003178                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000967                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995480                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65174                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         2299                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6267                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5773                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        50615                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994476                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 38456225                       # Number of tag accesses
+system.l2c.tags.data_accesses                38456225                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          823353                       # number of Writeback hits
+system.l2c.Writeback_hits::total               823353                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             170                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             230                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 400                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            49                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            26                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                75                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           159888                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            19633                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               179521                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        914307                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        199175                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1113482                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       746483                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        59707                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           806190                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              914307                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              906371                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              199175                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               79340                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2099193                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             914307                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             906371                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             199175                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              79340                       # number of overall hits
+system.l2c.overall_hits::total                2099193                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          2738                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1002                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3740                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          352                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          366                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             718                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         114723                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           7302                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122025                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        13477                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         1849                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           15326                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       272988                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          841                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         273829                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst             13477                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            387711                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1849                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              8143                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                411180                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13477                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           387711                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1849                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             8143                       # number of overall misses
+system.l2c.overall_misses::total               411180                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      1902000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      5314000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      7216000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1240500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       123000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      1363500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  10174433000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    803053000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  10977486000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1122774000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    155099500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   1277873500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  19926572000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data     76887500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  20003459500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1122774000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  30101005000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    155099500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    879940500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     32258819000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1122774000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  30101005000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    155099500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    879940500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    32258819000                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       823353                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           823353                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2908                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1232                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4140                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          401                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          392                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           793                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       274611                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        26935                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           301546                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       927784                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       201024                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1128808                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      1019471                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        60548                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      1080019                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          927784                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1294082                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          201024                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           87483                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2510373                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         927784                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1294082                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         201024                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          87483                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2510373                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941541                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.813312                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.903382                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.877805                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.933673                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.905422                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.417765                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.271097                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.404665                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014526                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.009198                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.013577                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.267774                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.013890                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.253541                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014526                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.299603                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.009198                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.093081                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.163792                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014526                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.299603                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.009198                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.093081                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.163792                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   694.667641                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5303.393214                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1929.411765                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3524.147727                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   336.065574                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1899.025070                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88686.950306                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109977.129554                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 89960.958820                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 83310.380649                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83882.909681                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 83379.453217                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72994.314768                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91423.900119                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 73050.916813                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 83310.380649                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 77637.737903                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83882.909681                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 108060.972615                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 78454.251180                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 83310.380649                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 77637.737903                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83882.909681                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 108060.972615                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 78454.251180                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1894,253 +1876,249 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               82738                       # number of writebacks
-system.l2c.writebacks::total                    82738                       # number of writebacks
+system.l2c.writebacks::writebacks               81317                       # number of writebacks
+system.l2c.writebacks::total                    81317                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           17                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            1                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst             17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks          356                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total          356                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2583                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          538                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3121                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           69                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          100                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          169                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       105448                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        17488                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122936                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        11626                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         3697                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        15323                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272098                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2178                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       274276                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        11626                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       377546                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         3697                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        19666                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           412535                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        11626                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       377546                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         3697                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        19666                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          412535                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data         4777                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         2425                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total         7202                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data         8020                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4340                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        12360                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        12797                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6765                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        19562                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     53861495                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     11082500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     64943995                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1433500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2068000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      3501500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8263056000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1632969000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   9896025000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    847954500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    277279000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1125233500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17126346500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    197172000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  17323518500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    847954500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  25389402500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    277279000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1830141000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  28344777000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    847954500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  25389402500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    277279000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1830141000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  28344777000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    953578000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    469134500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1422712500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1615175500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    905955000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2521130500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2568753500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1375089500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3943843000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks          353                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total          353                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2738                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1002                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3740                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          352                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          366                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          718                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       114723                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         7302                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122025                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13476                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1832                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        15308                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272988                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          841                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       273829                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13476                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       387711                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1832                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8143                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           411162                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13476                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       387711                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1832                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         8143                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          411162                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7035                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data          158                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         7193                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10024                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2884                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        12908                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17059                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3042                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        20101                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57077500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     20724000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     77801500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7323000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      7608000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     14931000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9027203000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    730033000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   9757236000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    987919000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    135556000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1123475000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17205778500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     68477500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  17274256000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    987919000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  26232981500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    135556000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    798510500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  28154967000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    987919000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  26232981500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    135556000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    798510500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  28154967000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1392804000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     27752000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1420556000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2037629000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    601171500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2638800500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3430433000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    628923500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4059356500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.948238                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.870550                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.933872                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.644860                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.735294                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.695473                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.478216                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.182684                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.388754                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018857                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007388                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013719                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.402714                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.004884                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.244531                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018857                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.421292                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007388                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.036304                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.161474                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018857                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.421292                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007388                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.036304                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.161474                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20852.301587                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20599.442379                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20808.713553                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.362319                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        20680                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20718.934911                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78361.429330                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93376.543916                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80497.372617                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72936.048512                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75001.081958                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 68708.781073                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 68708.781073                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941541                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.813312                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.903382                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.877805                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.933673                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.905422                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.417765                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.271097                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.404665                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014525                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.009113                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013561                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.267774                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.013890                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.253541                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014525                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.299603                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009113                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.093081                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.163785                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014525                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.299603                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009113                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.093081                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.163785                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20846.420745                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20682.634731                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.540107                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.977273                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.885246                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20795.264624                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78686.950306                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99977.129554                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 79960.958820                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73309.513209                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73993.449782                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73391.363993                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63027.600114                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81423.900119                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63084.099931                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73309.513209                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67661.174174                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73993.449782                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98060.972615                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 68476.578575                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73309.513209                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67661.174174                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73993.449782                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98060.972615                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 68476.578575                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197982.089552                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175645.569620                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197491.450021                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203275.039904                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208450.589459                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204431.399132                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201092.268011                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 206746.712689                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 201947.987662                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                7202                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296546                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12360                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12360                       # Transaction distribution
-system.membus.trans_dist::Writeback            124264                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262871                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             5279                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           1481                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            3452                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            122900                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           122774                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289774                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          430                       # Transaction distribution
+system.membus.trans_dist::ReadReq                7193                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296434                       # Transaction distribution
+system.membus.trans_dist::WriteReq              12908                       # Transaction distribution
+system.membus.trans_dist::WriteResp             12908                       # Transaction distribution
+system.membus.trans_dist::Writeback            122837                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           263082                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             9353                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           4872                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4824                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122000                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           121659                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289315                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           74                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39124                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1179542                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          860                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1219526                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124833                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124833                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1344359                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        68315                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31641920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31710235                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2658624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34368859                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3872                       # Total snoops (count)
-system.membus.snoop_fanout::samples            867863                       # Request fanout histogram
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40202                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1184934                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          148                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1225284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1350114                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        72634                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31472384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31545018                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                34203258                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            10191                       # Total snoops (count)
+system.membus.snoop_fanout::samples            873294                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  867863    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  873294    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              867863                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            35224999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              873294                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            36159500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1361324691                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1354680439                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              531000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               95500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2190703579                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2187139696                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           72073655                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           72110882                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq               7202                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2275897                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12360                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12360                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           985613                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1602095                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            5338                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          1555                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           6893                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           317171                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          317171                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1117101                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1152039                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          430                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq               7193                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2235424                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             12908                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            12908                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           946207                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1643079                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            9387                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          4947                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          14334                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302784                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302784                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1129148                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1099173                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           74                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1728214                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2704934                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1334787                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1622621                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7390556                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     39458944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     84672718                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     32025024                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     62527373                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              218684059                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          464381                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5618153                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.076464                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.265739                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2591178                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3901537                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       531442                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       279415                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7303572                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     59378176                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    131958120                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     12865536                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side      9234898                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              213436730                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          458492                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5507130                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.077786                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.267834                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                5188566     92.35%     92.35% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                 429587      7.65%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                5078755     92.22%     92.22% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                 428375      7.78%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5618153                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3461836914                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5507130                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3369225418                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           240000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           243000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         925515973                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1363977262                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1393343588                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        1972546779                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         751744303                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         301679801                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         856189885                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         151036436                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -2174,32 +2152,32 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4815                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    139340                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   45519     38.89%     38.89% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    133      0.11%     39.01% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1927      1.65%     40.65% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                     16      0.01%     40.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  69446     59.33%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              117041                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    44932     48.88%     48.88% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     133      0.14%     49.02% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1927      2.10%     51.12% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                      16      0.02%     51.14% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   44917     48.86%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total                91925                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1870471244000     98.03%     98.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               61392000      0.00%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              548913500      0.03%     98.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                8511500      0.00%     98.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            36889187000      1.93%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1907979248000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.987104                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6502                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    187776                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   66469     40.53%     40.53% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.61% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1926      1.17%     41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    149      0.09%     41.88% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  95308     58.12%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              163983                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    65388     49.23%     49.23% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.10%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1926      1.45%     50.77% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     149      0.11%     50.89% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   65239     49.11%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               132833                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1864137851500     97.75%     97.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               61127000      0.00%     97.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              545976000      0.03%     97.79% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               68164000      0.00%     97.79% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            42142829000      2.21%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1906955947500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.983737                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.646790                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.785409                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.684507                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810041                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.56%      3.56% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.44%     12.00% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.78%     13.78% # number of syscalls executed
@@ -2231,60 +2209,60 @@ system.cpu0.kern.syscall::144                       2      0.89%     99.11% # nu
 system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   225                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  104      0.08%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.09% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.09% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.09% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 2293      1.85%      1.93% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      50      0.04%      1.97% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.01%      1.98% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               110963     89.30%     91.28% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6296      5.07%     96.35% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.35% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.35% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.36% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.36% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4002      3.22%     99.58% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 382      0.31%     99.89% # number of callpals executed
-system.cpu0.kern.callpal::imb                     138      0.11%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                124254                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             5723                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1342                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  249      0.14%      0.14% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.15% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.15% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.15% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3603      2.09%      2.23% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.03%      2.26% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.27% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               157157     91.07%     93.34% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6335      3.67%     97.01% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.01% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     97.02% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     97.02% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.02% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4619      2.68%     99.70% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 382      0.22%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                172559                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7164                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1343                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1341                      
-system.cpu0.kern.mode_good::user                 1342                      
+system.cpu0.kern.mode_good::kernel               1342                      
+system.cpu0.kern.mode_good::user                 1343                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.234318                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.187326                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.379759                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1905987592000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1991648000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.315622                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1904989354500     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1966585000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    2294                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3604                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    3855                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     98215                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   36112     40.36%     40.36% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1925      2.15%     42.52% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    104      0.12%     42.63% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  51325     57.37%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               89466                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    35322     48.67%     48.67% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1925      2.65%     51.33% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     104      0.14%     51.47% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   35218     48.53%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                72569                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1870768654000     98.07%     98.07% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              540231000      0.03%     98.10% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               48911000      0.00%     98.10% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            36277143500      1.90%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1907634939500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.978124                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2444                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     51472                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   15731     36.02%     36.02% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1925      4.41%     40.43% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    249      0.57%     41.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  25763     59.00%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               43668                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    15435     47.07%     47.07% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1925      5.87%     52.93% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     249      0.76%     53.69% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   15186     46.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                32795                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1874760769500     98.33%     98.33% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              538410500      0.03%     98.36% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              114320500      0.01%     98.36% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            31218212000      1.64%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1906631712500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.981184                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.686176                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.811135                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.589450                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.751008                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        11     10.89%     10.89% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      8.91%     19.80% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      0.99%     20.79% # number of syscalls executed
@@ -2300,35 +2278,35 @@ system.cpu1.kern.syscall::74                       10      9.90%     97.03% # nu
 system.cpu1.kern.syscall::132                       3      2.97%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                   101                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1949      2.12%      2.14% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      2.14% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.15% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                84230     91.49%     93.64% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2466      2.68%     96.32% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.32% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.00%     96.32% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     96.33% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3206      3.48%     99.81% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 133      0.14%     99.95% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.05%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  149      0.33%      0.33% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.33% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  911      2.02%      2.35% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      2.36% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      2.38% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                38628     85.51%     87.88% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2426      5.37%     93.25% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.25% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     93.26% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.27% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2865      6.34%     99.61% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 133      0.29%     99.90% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 92064                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2331                       # number of protection mode switches
+system.cpu1.kern.callpal::total                 45176                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1151                       # number of protection mode switches
 system.cpu1.kern.mode_switch::user                395                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2054                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                461                      
+system.cpu1.kern.mode_switch::idle               2341                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                568                      
 system.cpu1.kern.mode_good::user                  395                      
-system.cpu1.kern.mode_good::idle                   66                      
-system.cpu1.kern.mode_switch_good::kernel     0.197769                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle                  173                      
+system.cpu1.kern.mode_switch_good::kernel     0.493484                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.032132                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.192887                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       42837305000      2.25%      2.25% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           697376000      0.04%      2.28% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1863790118000     97.72%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1950                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.073900                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.292256                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        3648998000      0.19%      0.19% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           689386500      0.04%      0.23% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1901995153000     99.77%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     912                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 3eacf4507..2be1ffca4 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -166,7 +166,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -513,7 +513,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -562,7 +562,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -696,7 +696,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 156f5647f..275b5ad07 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,111 +1,111 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.861005                       # Number of seconds simulated
-sim_ticks                                1861005347500                       # Number of ticks simulated
-final_tick                               1861005347500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.860990                       # Number of seconds simulated
+sim_ticks                                1860990273000                       # Number of ticks simulated
+final_tick                               1860990273000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 149955                       # Simulator instruction rate (inst/s)
-host_op_rate                                   149955                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5267476367                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 376564                       # Number of bytes of host memory used
-host_seconds                                   353.30                       # Real time elapsed on the host
-sim_insts                                    52979113                       # Number of instructions simulated
-sim_ops                                      52979113                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 102674                       # Simulator instruction rate (inst/s)
+host_op_rate                                   102674                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3606509618                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370916                       # Number of bytes of host memory used
+host_seconds                                   516.01                       # Real time elapsed on the host
+sim_insts                                    52980740                       # Number of instructions simulated
+sim_ops                                      52980740                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            965824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24879488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            964096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24880000                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25846272                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       965824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          965824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7524416                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7524416                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15091                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388742                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25845056                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       964096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          964096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7523456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7523456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388750                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403848                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117569                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117569                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               518980                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13368843                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403829                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117554                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117554                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               518055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13369226                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13888338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          518980                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518980                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4043200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4043200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4043200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              518980                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13368843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13887797                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          518055                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             518055                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4042716                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4042716                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4042716                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              518055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13369226                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17931538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403848                       # Number of read requests accepted
-system.physmem.writeReqs                       117569                       # Number of write requests accepted
-system.physmem.readBursts                      403848                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117569                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25839488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7523328                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25846272                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7524416                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               17930514                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403829                       # Number of read requests accepted
+system.physmem.writeReqs                       117554                       # Number of write requests accepted
+system.physmem.readBursts                      403829                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117554                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25837696                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7522048                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25845056                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7523456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          41759                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25651                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25422                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          41890                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25640                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25420                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               25567                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25497                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25384                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24734                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24943                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25079                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24928                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25027                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25572                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24872                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24489                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25490                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25392                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24736                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24946                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25069                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24934                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25024                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25571                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24874                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24488                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              25240                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              25741                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25596                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7944                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7514                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7965                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7518                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7330                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6666                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6776                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6716                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7141                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6711                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7422                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6968                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7145                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25582                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7942                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7515                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7958                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7515                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7335                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6671                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6772                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6705                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7147                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6708                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7414                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6974                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7148                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7857                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8054                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7825                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8057                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7814                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          23                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1860999975500                       # Total gap between requests
+system.physmem.numWrRetry                          22                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1860985018500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403848                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403829                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117569                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    314964                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     36182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28364                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117554                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    314954                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     36116                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28406                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                     24147                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        73                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -148,116 +148,128 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7660                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1546                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4720                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8436                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      173                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::50                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       96                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       41                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61779                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      540.028683                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     331.823835                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.833229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13638     22.08%     22.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10412     16.85%     38.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4989      8.08%     47.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3229      5.23%     52.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2263      3.66%     55.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1516      2.45%     58.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1526      2.47%     60.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1289      2.09%     62.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        22917     37.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61779                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5213                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.447919                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2924.392219                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5210     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::60                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       61                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61694                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      540.722923                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     331.893410                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.338201                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13637     22.10%     22.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10472     16.97%     39.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4852      7.86%     46.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3164      5.13%     52.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2278      3.69%     55.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1550      2.51%     58.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1469      2.38%     60.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1300      2.11%     62.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22972     37.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61694                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5210                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        77.486564                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2926.418549                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5207     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5213                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5213                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.549779                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.928650                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       23.456391                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4618     88.59%     88.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             208      3.99%     92.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              74      1.42%     94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              17      0.33%     94.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               8      0.15%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               5      0.10%     94.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              10      0.19%     94.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              10      0.19%     94.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87               7      0.13%     95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              32      0.61%     95.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            168      3.22%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            10      0.19%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             2      0.04%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             5      0.10%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             2      0.04%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.02%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             2      0.04%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             3      0.06%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             2      0.04%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             5      0.10%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             3      0.06%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             4      0.08%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.02%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231            12      0.23%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5213                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3805918000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11376080500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018710000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9426.61                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5210                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5210                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.558925                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.942347                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.343325                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4470     85.80%     85.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             144      2.76%     88.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             197      3.78%     92.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              15      0.29%     92.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              22      0.42%     93.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              47      0.90%     93.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              16      0.31%     94.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.02%     94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               3      0.06%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.12%     94.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.10%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.04%     94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               4      0.08%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.04%     94.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.06%     94.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              10      0.19%     94.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               6      0.12%     95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              10      0.19%     95.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              18      0.35%     95.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              17      0.33%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           156      2.99%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             8      0.15%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.04%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.13%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.06%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.06%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.06%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             3      0.06%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             2      0.04%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.04%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.02%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             4      0.08%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231            11      0.21%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5210                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3803541750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11373179250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018570000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9421.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28176.61                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28171.38                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.89                       # Average system read bandwidth in MiByte/s
@@ -266,72 +278,72 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.30                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364169                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95345                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.20                       # Row buffer hit rate for reads
+system.physmem.avgRdQLen                         2.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364213                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95338                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.22                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  81.10                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3569120.25                       # Average gap between requests
-system.physmem.pageHitRate                      88.15                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  232515360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  126868500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577760600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                378619920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           121551434160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            56250477360                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1067257263000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1247374938900                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.271455                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1775312455750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     62142860000                       # Time in different power states
+system.physmem.avgGap                      3569324.31                       # Average gap between requests
+system.physmem.pageHitRate                      88.16                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  231343560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  126229125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1577628000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                378516240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           121550417040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            56189479095                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1067301426750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1247355039810                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.266370                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1775383293000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62142340000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     23544343000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23458453250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  234533880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  127969875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1571380200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                383117040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           121551434160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            55982569095                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1067492278500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1247343282750                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.254439                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1775708219250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     62142860000                       # Time in different power states
+system.physmem_1.actEnergy                  235063080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128258625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1571294400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                383091120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           121550417040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            55921872645                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1067536177500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1247326174410                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.250855                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1775778508500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62142340000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23148593250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23063881500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17721018                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15408782                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            378784                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12470436                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5897235                       # Number of BTB hits
+system.cpu.branchPred.lookups                17952495                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15650737                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            369298                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11540660                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5852648                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             47.289726                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  918220                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21032                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             50.713287                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  911814                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21176                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10294388                       # DTB read hits
-system.cpu.dtb.read_misses                      42024                       # DTB read misses
-system.cpu.dtb.read_acv                           506                       # DTB read access violations
-system.cpu.dtb.read_accesses                   968687                       # DTB read accesses
-system.cpu.dtb.write_hits                     6648521                       # DTB write hits
-system.cpu.dtb.write_misses                      9456                       # DTB write misses
-system.cpu.dtb.write_acv                          408                       # DTB write access violations
-system.cpu.dtb.write_accesses                  343243                       # DTB write accesses
-system.cpu.dtb.data_hits                     16942909                       # DTB hits
-system.cpu.dtb.data_misses                      51480                       # DTB misses
-system.cpu.dtb.data_acv                           914                       # DTB access violations
-system.cpu.dtb.data_accesses                  1311930                       # DTB accesses
-system.cpu.itb.fetch_hits                     1769476                       # ITB hits
-system.cpu.itb.fetch_misses                     36155                       # ITB misses
-system.cpu.itb.fetch_acv                          662                       # ITB acv
-system.cpu.itb.fetch_accesses                 1805631                       # ITB accesses
+system.cpu.dtb.read_hits                     10266725                       # DTB read hits
+system.cpu.dtb.read_misses                      41420                       # DTB read misses
+system.cpu.dtb.read_acv                           529                       # DTB read access violations
+system.cpu.dtb.read_accesses                   965767                       # DTB read accesses
+system.cpu.dtb.write_hits                     6642195                       # DTB write hits
+system.cpu.dtb.write_misses                      9809                       # DTB write misses
+system.cpu.dtb.write_acv                          405                       # DTB write access violations
+system.cpu.dtb.write_accesses                  342270                       # DTB write accesses
+system.cpu.dtb.data_hits                     16908920                       # DTB hits
+system.cpu.dtb.data_misses                      51229                       # DTB misses
+system.cpu.dtb.data_acv                           934                       # DTB access violations
+system.cpu.dtb.data_accesses                  1308037                       # DTB accesses
+system.cpu.itb.fetch_hits                     1768997                       # ITB hits
+system.cpu.itb.fetch_misses                     27603                       # ITB misses
+system.cpu.itb.fetch_acv                          655                       # ITB acv
+system.cpu.itb.fetch_accesses                 1796600                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -344,691 +356,692 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        122272854                       # number of cpu cycles simulated
+system.cpu.numCycles                        122250725                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29542399                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       77951342                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17721018                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6815455                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      84318662                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1251172                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       1032                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27002                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       1751503                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       450615                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          220                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9037094                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                274713                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116717019                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.667866                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.979948                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29590872                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       78035312                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17952495                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6764462                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      84736015                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1230846                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       3604                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       1246103                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       463506                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          270                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8988072                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                271207                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       4                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          116683770                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.668776                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.983888                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                102159840     87.53%     87.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   935001      0.80%     88.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1975635      1.69%     90.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   907890      0.78%     90.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2798283      2.40%     93.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   634657      0.54%     93.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   731012      0.63%     94.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1008696      0.86%     95.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5566005      4.77%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                102162821     87.56%     87.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   926771      0.79%     88.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1955000      1.68%     90.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   905545      0.78%     90.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2771139      2.37%     93.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   614884      0.53%     93.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   724459      0.62%     94.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1009032      0.86%     95.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5614119      4.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116717019                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.144930                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.637520                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24051579                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              80690981                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9487535                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1903773                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 583150                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               586842                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42848                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68182155                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                134674                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 583150                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24974215                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                50913599                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20868972                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10381558                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8995523                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65764072                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                201455                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2078667                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 157006                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4811107                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43858088                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79749030                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79568293                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168286                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38179356                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5678724                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1691117                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         241700                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13523739                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10414999                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6951257                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1489090                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1076371                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58557437                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2137330                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57550552                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             58383                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7715649                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3482179                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1476201                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116717019                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.493078                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.231262                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            116683770                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.146850                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.638322                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24065548                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              80700938                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9436968                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1906955                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 573360                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               582340                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42404                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               68029803                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                132508                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 573360                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24987085                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50897393                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20868454                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10337136                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               9020340                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65614260                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                203152                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2087104                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 150571                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4833262                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            43733220                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79561709                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79380946                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168313                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38180223                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5552989                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1689330                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         239361                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13544094                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10376074                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6949198                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1492318                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1087072                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58452380                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2137932                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57496742                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             57057                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7609567                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3401604                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1476871                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     116683770                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.492757                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.231576                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            93076852     79.75%     79.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10193735      8.73%     88.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4312708      3.70%     92.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3021195      2.59%     94.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3081764      2.64%     97.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1495449      1.28%     98.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1007889      0.86%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              403235      0.35%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              124192      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            93080109     79.77%     79.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10182698      8.73%     88.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4288903      3.68%     92.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3018996      2.59%     94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3082938      2.64%     97.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1488362      1.28%     98.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1011835      0.87%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              404754      0.35%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125175      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116717019                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116683770                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  208462     18.43%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 547266     48.38%     66.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                375475     33.19%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  209669     18.63%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 542046     48.17%     66.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                373622     33.20%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39056911     67.87%     67.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61891      0.11%     67.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38552      0.07%     68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10704988     18.60%     86.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6728388     11.69%     98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             948900      1.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39037181     67.89%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61834      0.11%     68.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38554      0.07%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10676723     18.57%     86.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6722717     11.69%     98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             948811      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57550552                       # Type of FU issued
-system.cpu.iq.rate                           0.470673                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1131203                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019656                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          232294841                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          68093775                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55871823                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              712867                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             336544                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       329026                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58291729                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  382740                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           634925                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57496742                       # Type of FU issued
+system.cpu.iq.rate                           0.470318                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1125337                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019572                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          232146820                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          67882277                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55834928                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              712827                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             336508                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       328971                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58232105                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  382688                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           634703                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1322411                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3516                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20331                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       573217                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1283936                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3373                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        19308                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       571381                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18302                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        483316                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18194                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        477327                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 583150                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                47678109                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                871068                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64398227                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            142430                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10414999                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6951257                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1888726                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  44438                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                623782                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20331                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         186400                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       411798                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               598198                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56961347                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10364061                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            589204                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 573360                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                47668673                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                853294                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64278853                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            140556                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10376074                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6949198                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1890343                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  43583                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                606693                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          19308                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         178271                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       409117                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               587388                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56911436                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10335818                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            585305                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3703460                       # number of nop insts executed
-system.cpu.iew.exec_refs                     17037134                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8968929                       # Number of branches executed
-system.cpu.iew.exec_stores                    6673073                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.465854                       # Inst execution rate
-system.cpu.iew.wb_sent                       56337909                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56200849                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28756133                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  39912635                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3688541                       # number of nop insts executed
+system.cpu.iew.exec_refs                     17002933                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8971597                       # Number of branches executed
+system.cpu.iew.exec_stores                    6667115                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.465530                       # Inst execution rate
+system.cpu.iew.wb_sent                       56299831                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56163899                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28741573                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  39917507                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.459635                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.720477                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.459416                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.720024                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8112704                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661129                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            547326                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    115294268                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.487187                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.430320                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7990103                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661061                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            538190                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    115283305                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.487246                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.430050                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     95501177     82.83%     82.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7867272      6.82%     89.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4280982      3.71%     93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2233083      1.94%     95.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1745854      1.51%     96.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       611445      0.53%     97.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       482985      0.42%     97.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       468960      0.41%     98.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2102510      1.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     95489644     82.83%     82.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7861367      6.82%     89.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4279666      3.71%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2238986      1.94%     95.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1753667      1.52%     96.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       610357      0.53%     97.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       475106      0.41%     97.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       479497      0.42%     98.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2095015      1.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    115294268                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56169836                       # Number of instructions committed
-system.cpu.commit.committedOps               56169836                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    115283305                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56171345                       # Number of instructions committed
+system.cpu.commit.committedOps               56171345                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15470628                       # Number of memory references committed
-system.cpu.commit.loads                       9092588                       # Number of loads committed
-system.cpu.commit.membars                      226333                       # Number of memory barriers committed
-system.cpu.commit.branches                    8440353                       # Number of branches committed
+system.cpu.commit.refs                       15469955                       # Number of memory references committed
+system.cpu.commit.loads                       9092138                       # Number of loads committed
+system.cpu.commit.membars                      226307                       # Number of memory barriers committed
+system.cpu.commit.branches                    8441356                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52019375                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740552                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3197996      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36217639     64.48%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60667      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.int_insts                  52021098                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740502                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3197878      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36220066     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60657      0.11%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9318921     16.59%     86.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6383992     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        948900      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.36% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9318445     16.59%     86.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6383767     11.36%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        948811      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56169836                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2102510                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    177224791                       # The number of ROB reads
-system.cpu.rob.rob_writes                   129983616                       # The number of ROB writes
-system.cpu.timesIdled                          573073                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5555835                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3599737842                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52979113                       # Number of Instructions Simulated
-system.cpu.committedOps                      52979113                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.307945                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.307945                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.433286                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.433286                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74622251                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40551917                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    167069                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167545                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2028916                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939321                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1404299                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994455                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11844191                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1404811                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.431163                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          26393500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994455                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total          56171345                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2095015                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    177100105                       # The number of ROB reads
+system.cpu.rob.rob_writes                   129718981                       # The number of ROB writes
+system.cpu.timesIdled                          575678                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5566955                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3599729822                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52980740                       # Number of Instructions Simulated
+system.cpu.committedOps                      52980740                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.307456                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.307456                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.433378                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.433378                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74560962                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40515010                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    167029                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167528                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2030483                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939256                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1402429                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994497                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11825966                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1402941                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.429411                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          26175500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994497                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          412                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63926076                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63926076                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7252822                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7252822                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4188714                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4188714                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186644                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186644                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215706                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215706                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11441536                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11441536                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11441536                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11441536                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1804157                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1804157                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1958890                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1958890                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23354                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23354                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           29                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3763047                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3763047                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3763047                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3763047                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  41750233000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  41750233000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  80527676066                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  80527676066                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    377889000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    377889000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       498500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       498500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 122277909066                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 122277909066                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 122277909066                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 122277909066                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9056979                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9056979                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147604                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147604                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209998                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209998                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215735                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215735                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15204583                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15204583                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15204583                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15204583                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199201                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.199201                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318643                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.318643                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111211                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111211                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000134                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000134                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.247494                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.247494                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.247494                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.247494                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23141.130733                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23141.130733                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41108.830034                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41108.830034                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16180.911193                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16180.911193                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17189.655172                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17189.655172                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32494.387943                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32494.387943                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32494.387943                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32494.387943                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      4529793                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         2677                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            135335                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              25                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.470965                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   107.080000                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          63836458                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63836458                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7233922                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7233922                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4189857                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4189857                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186093                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186093                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215697                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215697                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11423779                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11423779                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11423779                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11423779                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1801919                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1801919                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1957536                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1957536                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23327                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23327                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           28                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           28                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3759455                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3759455                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3759455                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3759455                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  41733061500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  41733061500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  80455809465                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  80455809465                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376093000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    376093000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       485000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       485000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 122188870965                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 122188870965                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 122188870965                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 122188870965                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9035841                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9035841                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147393                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147393                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209420                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209420                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215725                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215725                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15183234                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15183234                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15183234                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15183234                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199419                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.199419                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318434                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.318434                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111389                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111389                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000130                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.247606                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.247606                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.247606                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.247606                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23160.342668                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23160.342668                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41100.551645                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41100.551645                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16122.647576                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16122.647576                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17321.428571                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17321.428571                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32501.751175                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32501.751175                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32501.751175                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32501.751175                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      4515997                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         2303                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            134454                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              26                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.587673                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    88.576923                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       842762                       # number of writebacks
-system.cpu.dcache.writebacks::total            842762                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       708195                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       708195                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1668077                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1668077                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5151                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5151                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2376272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2376272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2376272                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2376272                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1095962                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1095962                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290813                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290813                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18203                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        18203                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           29                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1386775                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1386775                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1386775                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1386775                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       841625                       # number of writebacks
+system.cpu.dcache.writebacks::total            841625                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       707636                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       707636                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1666818                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1666818                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5179                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5179                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2374454                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2374454                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2374454                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2374454                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1094283                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1094283                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290718                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290718                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18148                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18148                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           28                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           28                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1385001                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1385001                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1385001                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1385001                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9597                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9597                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16527                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16527                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30575992000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30575992000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12635842717                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12635842717                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    226273500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    226273500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       469500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       469500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  43211834717                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  43211834717                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  43211834717                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  43211834717                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1451037500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1451037500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2035928998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2035928998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3486966498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3486966498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121007                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121007                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047305                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047305                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086682                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086682                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000134                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000134                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091208                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091208                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091208                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091208                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004                       # average overall mshr uncacheable latency
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9596                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9596                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16526                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16526                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30550296500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30550296500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12634151241                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12634151241                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    226327000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    226327000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       457000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       457000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  43184447741                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  43184447741                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  43184447741                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  43184447741                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450758000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450758000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2035709998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2035709998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3486467998                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3486467998                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121105                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121105                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047291                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047291                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086658                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086658                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000130                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091219                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091219                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091219                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091219                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1035158                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.238634                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7947846                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1035666                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.674140                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       28148361500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.238634                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994607                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994607                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1038549                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.170339                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7895321                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1039057                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.598545                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       28146856500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.170339                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994473                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994473                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10073023                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10073023                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7947847                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7947847                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7947847                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7947847                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7947847                       # number of overall hits
-system.cpu.icache.overall_hits::total         7947847                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1089244                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1089244                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1089244                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1089244                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1089244                       # number of overall misses
-system.cpu.icache.overall_misses::total       1089244                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15223822993                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15223822993                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15223822993                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15223822993                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15223822993                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15223822993                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9037091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9037091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9037091                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9037091                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9037091                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9037091                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120530                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.120530                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.120530                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.120530                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.120530                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.120530                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13976.503881                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.503881                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13976.503881                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.503881                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13976.503881                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5247                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10027494                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10027494                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7895322                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7895322                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7895322                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7895322                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7895322                       # number of overall hits
+system.cpu.icache.overall_hits::total         7895322                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1092746                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1092746                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1092746                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1092746                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1092746                       # number of overall misses
+system.cpu.icache.overall_misses::total       1092746                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15273300993                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15273300993                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15273300993                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15273300993                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15273300993                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15273300993                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8988068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8988068                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8988068                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8988068                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8988068                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8988068                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121577                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.121577                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.121577                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.121577                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.121577                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.121577                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13976.990987                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13976.990987                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6859                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               192                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               220                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    27.328125                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    31.177273                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53312                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        53312                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        53312                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        53312                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        53312                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        53312                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1035932                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1035932                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1035932                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1035932                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1035932                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1035932                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13551519997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13551519997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13551519997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13551519997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13551519997                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13551519997                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114631                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114631                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114631                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114631                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114631                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114631                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13081.476387                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13081.476387                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13081.476387                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13081.476387                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13081.476387                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13081.476387                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53320                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        53320                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        53320                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        53320                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        53320                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        53320                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1039426                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1039426                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1039426                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1039426                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1039426                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1039426                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13594657497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13594657497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13594657497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13594657497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13594657497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13594657497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115645                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115645                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115645                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.115645                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115645                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.115645                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13079.004659                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13079.004659                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13079.004659                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13079.004659                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13079.004659                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13079.004659                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338333                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65329.899668                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4170748                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403498                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.336478                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5937880000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53646.073919                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5370.196877                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6313.628872                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.818574                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081943                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.096338                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996855                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65165                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          490                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3506                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3328                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2403                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55438                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994339                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39732941                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39732941                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       842762                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       842762                       # number of Writeback hits
+system.cpu.l2cache.tags.replacements           338316                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65333.743960                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4173914                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403482                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.344734                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5938026000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53662.904675                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5355.130521                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6315.708764                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.818831                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081713                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.096370                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996914                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65166                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          494                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3498                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3319                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2393                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55462                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994354                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         39757135                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39757135                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       841625                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       841625                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           29                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           29                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           23                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           23                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       186220                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       186220                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1020652                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1020652                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       829426                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       829426                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1020652                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1015646                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2036298                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1020652                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1015646                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2036298                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           53                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           53                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           22                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           22                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       185982                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       185982                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1024048                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1024048                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       827700                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       827700                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1024048                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1013682                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2037730                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1024048                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1013682                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2037730                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           98                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           98                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            6                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            6                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       115405                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       115405                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15093                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        15093                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       273846                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       273846                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15093                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389251                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404344                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15093                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       389251                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404344                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       425000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       425000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data       115503                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       115503                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15066                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        15066                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       273839                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       273839                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        15066                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       389342                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        404408                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15066                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       389342                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       404408                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       454500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       454500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        61000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total        61000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10303208000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10303208000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1257093500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1257093500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19996128500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  19996128500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1257093500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30299336500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  31556430000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1257093500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30299336500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  31556430000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       842762                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       842762                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           82                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           82                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           29                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           29                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       301625                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       301625                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1035745                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1035745                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1103272                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1103272                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1035745                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1404897                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2440642                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1035745                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1404897                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2440642                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.646341                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.646341                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.206897                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.206897                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382611                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.382611                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014572                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014572                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248213                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248213                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014572                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.277067                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.165671                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014572                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.277067                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.165671                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  8018.867925                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  8018.867925                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10302938500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10302938500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1259119000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1259119000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19992285500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  19992285500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1259119000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30295224000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  31554343000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1259119000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30295224000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  31554343000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       841625                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       841625                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          127                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          127                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           28                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           28                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       301485                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       301485                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1039114                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1039114                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1101539                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1101539                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1039114                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1403024                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2442138                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1039114                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1403024                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2442138                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.771654                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.771654                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.214286                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.214286                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383114                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383114                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014499                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014499                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248597                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248597                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014499                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.277502                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.165596                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014499                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.277502                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.165596                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4637.755102                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4637.755102                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89278.696764                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89278.696764                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83289.836348                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83289.836348                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73019.611387                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73019.611387                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83289.836348                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77840.099319                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78043.522347                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83289.836348                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77840.099319                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78043.522347                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89200.613837                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89200.613837                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83573.543077                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83573.543077                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73007.444155                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73007.444155                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83573.543077                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.343241                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78026.010860                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83573.543077                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.343241                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78026.010860                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1037,141 +1050,141 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76057                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76057                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        76042                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76042                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          307                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          307                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           53                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           53                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          305                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          305                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           98                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           98                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            6                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            6                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115405                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       115405                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15092                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15092                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       273846                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       273846                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15092                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389251                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404343                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15092                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389251                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404343                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115503                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       115503                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15065                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15065                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       273839                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       273839                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15065                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389342                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404407                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15065                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389342                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404407                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9597                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9597                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16527                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16527                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1250500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1250500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       124500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       124500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9149158000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9149158000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1106078000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1106078000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17268105500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17268105500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1106078000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26417263500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  27523341500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1106078000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26417263500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  27523341500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1364412500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1364412500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1925547500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1925547500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3289960000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3289960000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9596                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9596                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16526                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16526                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2195000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2195000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       124000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       124000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9147908500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9147908500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1108373500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1108373500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17263967500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17263967500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1108373500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26411876000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27520249500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1108373500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26411876000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27520249500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1364133000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1364133000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1925339500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1925339500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3289472500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3289472500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.646341                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.646341                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.206897                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.206897                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382611                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382611                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014571                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014571                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248213                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248213                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014571                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277067                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.165671                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014571                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277067                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.165671                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        20750                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        20750                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.771654                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.771654                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.214286                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.214286                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383114                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383114                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014498                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014498                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248597                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248597                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014498                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277502                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.165595                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014498                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277502                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.165595                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2146205                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       960354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1857372                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           82                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           29                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          111                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       301625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1035932                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1103445                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           85                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2147969                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9596                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9596                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       959201                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1860011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          127                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           28                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          155                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       301485                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       301485                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1039426                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1101712                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           82                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3106451                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4246137                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7352588                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66287680                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143898860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          210186540                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      422109                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5318690                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.079299                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.270205                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3116681                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4240614                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7357295                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66503296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143706404                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          210209700                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      422216                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5321857                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.079248                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.270126                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4896924     92.07%     92.07% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             421766      7.93%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4900109     92.08%     92.08% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             421748      7.92%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5318690                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3296022500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5321857                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3296477500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1555343104                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1560615042                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2119169250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2116394230                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1187,9 +1200,9 @@ system.disk2.dma_write_bytes                     8192                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51148                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51148                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5048                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1201,11 +1214,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33054                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33052                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116504                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20200                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116502                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20192                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1217,11 +1230,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44140                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44132                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705748                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4661000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705740                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              4659000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1243,23 +1256,23 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           216065006                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           216075504                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23456000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.259177                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.259061                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1711311931000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.259177                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078699                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078699                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1711310965000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.259061                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078691                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078691                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1275,8 +1288,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21637883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21637883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4909206123                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4909206123                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4908771621                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4908771621                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21637883                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21637883                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21637883                       # number of overall miss cycles
@@ -1299,17 +1312,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 125074.468208                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 125074.468208                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 125074.468208                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs            18                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            9                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1325,8 +1338,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          173
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12987883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     12987883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2831606123                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2831606123                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2831171621                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2831171621                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     12987883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     12987883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     12987883                       # number of overall MSHR miss cycles
@@ -1341,60 +1354,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295956                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
-system.membus.trans_dist::Writeback            117569                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261797                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              204                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295925                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9596                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9596                       # Transaction distribution
+system.membus.trans_dist::Writeback            117554                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261799                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              335                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             210                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115254                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115254                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289111                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           85                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             341                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115266                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115266                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289077                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           82                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1146198                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          170                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179422                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33052                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1146409                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          164                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179625                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1304239                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30712960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30757100                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1304442                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30710784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30754916                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33414828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33412644                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              435                       # Total snoops (count)
-system.membus.snoop_fanout::samples            842203                       # Request fanout histogram
+system.membus.snoop_fanout::samples            842297                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  842203    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  842297    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              842203                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29160500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              842297                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            28891000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1313577675                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1313747676                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              109500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              109000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2139558790                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2139659662                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           72030935                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
@@ -1430,28 +1443,28 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6442                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     210978                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74652     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     210955                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74645     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105547     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182209                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73285     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1878      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105533     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182187                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73278     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73285     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148580                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1817522630000     97.66%     97.66% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                62579500      0.00%     97.67% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               533633500      0.03%     97.70% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             42885651500      2.30%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1861004494500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981688                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1878      1.26%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73278     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148565                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1817526707500     97.66%     97.66% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                62603000      0.00%     97.67% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               536431500      0.03%     97.70% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             42863705000      2.30%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1860989447000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981687                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694335                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815437                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694361                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815453                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1490,29 +1503,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175094     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175074     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6783      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5103      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191938                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5850                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1907                      
-system.cpu.kern.mode_good::user                  1737                      
+system.cpu.kern.callpal::total                 191916                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5848                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1909                      
+system.cpu.kern.mode_good::user                  1739                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.325983                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326436                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393886                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29174464500      1.57%      1.57% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2684090500      0.14%      1.71% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1829145931500     98.29%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394259                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29189899500      1.57%      1.57% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2667621500      0.14%      1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1829131918000     98.29%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index d49d26c09..df18f1206 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -98,7 +98,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -138,7 +138,7 @@ eventq_index=0
 size=64
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -750,7 +750,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -785,7 +785,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
index ae9247519..1b889d7a1 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
@@ -7,10 +7,6 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8155, Bank: 7
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -19,8 +15,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11185, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -54,6 +48,6 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 11369, Bank: 3
+Command: 0, Timestamp: 11394, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
index 29e1e9099..930df34c1 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:35:45
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 20:54:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
 
 Global frequency set at 1000000000000 ticks per second
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 8b67c053c..296ab434c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,131 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.841548                       # Number of seconds simulated
-sim_ticks                                1841548033500                       # Number of ticks simulated
-final_tick                               1841548033500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.841535                       # Number of seconds simulated
+sim_ticks                                1841535479500                       # Number of ticks simulated
+final_tick                               1841535479500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 218310                       # Simulator instruction rate (inst/s)
-host_op_rate                                   218310                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5702515722                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 375536                       # Number of bytes of host memory used
-host_seconds                                   322.94                       # Real time elapsed on the host
-sim_insts                                    70500110                       # Number of instructions simulated
-sim_ops                                      70500110                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 156573                       # Simulator instruction rate (inst/s)
+host_op_rate                                   156573                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3970842510                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 369896                       # Number of bytes of host memory used
+host_seconds                                   463.76                       # Real time elapsed on the host
+sim_insts                                    72613172                       # Number of instructions simulated
+sim_ops                                      72613172                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           465600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20057408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           147136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2156416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           307456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2656704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           466112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20058112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           147008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2156288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           305728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2656832                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25791680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       465600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       147136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       307456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          920192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7484672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7484672                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7275                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            313397                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2299                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             33694                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4804                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             41511                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25791040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       466112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       147008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       305728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          918848                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7482432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7482432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7283                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            313408                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2297                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             33692                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4777                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             41513                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                402995                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116948                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116948                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              252831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10891602                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               79898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1170980                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              166955                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1442647                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                402985                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116913                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116913                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              253111                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10892058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               79829                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1170919                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              166018                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1442726                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14005434                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         252831                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          79898                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         166955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             499684                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4064337                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4064337                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4064337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             252831                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10891602                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              79898                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1170980                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             166955                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1442647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                14005182                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         253111                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          79829                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         166018                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             498958                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4063148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4063148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4063148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             253111                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10892058                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              79829                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1170919                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             166018                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1442726                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18069771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         82323                       # Number of read requests accepted
-system.physmem.writeReqs                        47461                       # Number of write requests accepted
-system.physmem.readBursts                       82323                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      47461                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5267264                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   3035584                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5268672                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                3037504                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       22                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               18068331                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         82294                       # Number of read requests accepted
+system.physmem.writeReqs                        47398                       # Number of write requests accepted
+system.physmem.readBursts                       82294                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      47398                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5265472                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1344                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   3032512                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5266816                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                3033472                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       21                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          17348                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4998                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5047                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4951                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                4902                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5135                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5137                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5321                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5238                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5355                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4827                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5539                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5124                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4881                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5044                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5631                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5171                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2712                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2869                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2967                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                2927                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2992                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2769                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                3293                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2918                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3398                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2634                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               3325                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2913                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2642                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2800                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3388                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2884                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          17325                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5126                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5048                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4814                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                4971                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5248                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5169                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5184                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5149                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5417                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                4756                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5535                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5117                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4885                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5047                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5632                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5175                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2819                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2870                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2836                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                2977                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3104                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2797                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                3160                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2831                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3459                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2567                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               3319                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2907                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2644                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2801                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3392                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2900                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1840536161000                       # Total gap between requests
+system.physmem.totGap                    1840523607000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   82323                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   82294                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  47461                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     64278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5619                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  47398                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     64239                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7821                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5630                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                      4551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -153,140 +153,137 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        44                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        41                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        41                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        38                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       37                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                       37                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     2856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     3843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     2960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     3003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        21805                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      380.777253                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     217.097266                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     378.211296                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7203     33.03%     33.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4880     22.38%     55.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2010      9.22%     64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1038      4.76%     69.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          857      3.93%     73.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          538      2.47%     75.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          425      1.95%     77.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          372      1.71%     79.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4482     20.55%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          21805                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2075                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        39.654458                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      980.113813                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2073     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::13                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      932                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     2452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     2795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     2907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     3952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     3624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     3062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     3399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     2706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     3062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       27                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        21780                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      380.991001                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     216.949703                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     378.684450                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7216     33.13%     33.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4887     22.44%     55.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1962      9.01%     64.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1034      4.75%     69.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          848      3.89%     73.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          523      2.40%     75.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          452      2.08%     77.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          368      1.69%     79.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4490     20.62%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21780                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2078                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        39.592397                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      979.363215                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2076     99.90%     99.90% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2075                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2075                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.858313                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.353134                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.870235                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                34      1.64%      1.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.34%      1.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.10%      2.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               5      0.24%      2.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            1736     83.66%     85.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              36      1.73%     87.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              80      3.86%     91.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              17      0.82%     92.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              12      0.58%     92.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              17      0.82%     93.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               5      0.24%     94.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               1      0.05%     94.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.05%     94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.10%     94.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               3      0.14%     94.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.05%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.19%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.05%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.10%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.05%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.14%     94.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               9      0.43%     95.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               4      0.19%     95.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            65      3.13%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.14%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.14%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.05%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             2      0.10%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.05%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.05%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.05%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             2      0.10%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             2      0.10%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.10%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.05%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             3      0.14%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.05%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             4      0.19%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2075                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      914891250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2458035000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    411505000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11116.41                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            2078                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2078                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.802214                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.584158                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.825875                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                29      1.40%      1.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 6      0.29%      1.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.05%      1.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               6      0.29%      2.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            1724     82.96%     84.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              39      1.88%     86.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              91      4.38%     91.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              19      0.91%     92.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               9      0.43%     92.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              19      0.91%     93.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               4      0.19%     93.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               2      0.10%     93.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.14%     93.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.05%     93.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               2      0.10%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.14%     94.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.05%     94.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.14%     94.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               4      0.19%     94.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               8      0.38%     95.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.19%     95.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            76      3.66%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             6      0.29%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.10%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.05%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             3      0.14%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.10%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.05%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.05%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.10%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.05%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             2      0.10%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2078                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      922774500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2465393250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    411365000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11216.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29866.41                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29966.01                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.86                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.65                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.86                       # Average system read bandwidth in MiByte/s
@@ -295,63 +292,63 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         2.86                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      70476                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     37451                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.63                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.91                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14181533.63                       # Average gap between requests
-system.physmem.pageHitRate                      83.17                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   81194400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   44195250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 317686200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                151936560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            89056992960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            35637705585                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           799850646000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             925140356955                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.881529                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1309035077000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     45530160000                       # Time in different power states
+system.physmem.avgRdQLen                         1.55                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        16.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      70442                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     37434                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14191496.83                       # Average gap between requests
+system.physmem.pageHitRate                      83.19                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   81065880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   44121000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 317530200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                151593120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            89055975840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            35745647625                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           800947233750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             926343167415                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.792687                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1308857547000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     45529640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9110965500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9287627500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   83651400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   45474000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 324261600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                155416320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            89056992960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            35441943930                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           803933138250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             929040878460                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.556246                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1309294919000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     45530160000                       # Time in different power states
+system.physmem_1.actEnergy                   83590920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   45449250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 324199200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                155448720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            89055975840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            35447161140                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           801537520500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             926649345570                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.749891                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1309278655250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     45529640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      8868165750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      8857363000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4775602                       # DTB read hits
-system.cpu0.dtb.read_misses                      5966                       # DTB read misses
+system.cpu0.dtb.read_hits                     4774172                       # DTB read hits
+system.cpu0.dtb.read_misses                      5959                       # DTB read misses
 system.cpu0.dtb.read_acv                          109                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  428378                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3387346                       # DTB write hits
-system.cpu0.dtb.write_misses                      667                       # DTB write misses
+system.cpu0.dtb.read_accesses                  427834                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3388527                       # DTB write hits
+system.cpu0.dtb.write_misses                      664                       # DTB write misses
 system.cpu0.dtb.write_acv                          80                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 163776                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8162948                       # DTB hits
-system.cpu0.dtb.data_misses                      6633                       # DTB misses
+system.cpu0.dtb.write_accesses                 164366                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8162699                       # DTB hits
+system.cpu0.dtb.data_misses                      6623                       # DTB misses
 system.cpu0.dtb.data_acv                          189                       # DTB access violations
-system.cpu0.dtb.data_accesses                  592154                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2717036                       # ITB hits
-system.cpu0.itb.fetch_misses                     3019                       # ITB misses
+system.cpu0.dtb.data_accesses                  592200                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2715643                       # ITB hits
+system.cpu0.itb.fetch_misses                     3015                       # ITB misses
 system.cpu0.itb.fetch_acv                          97                       # ITB acv
-system.cpu0.itb.fetch_accesses                2720055                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2718658                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -364,67 +361,67 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       930055234                       # number of cpu cycles simulated
+system.cpu0.numCycles                       928469977                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31475732                       # Number of instructions committed
-system.cpu0.committedOps                     31475732                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             29412106                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                162586                       # Number of float alu accesses
-system.cpu0.num_func_calls                     792411                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4104277                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    29412106                       # number of integer instructions
-system.cpu0.num_fp_insts                       162586                       # number of float instructions
-system.cpu0.num_int_register_reads           40967178                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          21562005                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               84110                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              85570                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8192042                       # number of memory refs
-system.cpu0.num_load_insts                    4796241                       # Number of load instructions
-system.cpu0.num_store_insts                   3395801                       # Number of store instructions
-system.cpu0.num_idle_cycles              907058327.289346                       # Number of idle cycles
-system.cpu0.num_busy_cycles              22996906.710654                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.024726                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.975274                       # Percentage of idle cycles
-system.cpu0.Branches                          5151040                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1559860      4.95%      4.95% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 21040910     66.83%     71.79% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31347      0.10%     71.89% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.89% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12827      0.04%     71.93% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1598      0.01%     71.93% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.93% # Class of executed instruction
-system.cpu0.op_class::MemRead                 4926196     15.65%     87.58% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3398883     10.80%     98.38% # Class of executed instruction
-system.cpu0.op_class::IprAccess                510933      1.62%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   30414467                       # Number of instructions committed
+system.cpu0.committedOps                     30414467                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             28351523                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                162419                       # Number of float alu accesses
+system.cpu0.num_func_calls                     792250                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3751370                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    28351523                       # number of integer instructions
+system.cpu0.num_fp_insts                       162419                       # number of float instructions
+system.cpu0.num_int_register_reads           39201854                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          20853832                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               84043                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              85470                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8191763                       # number of memory refs
+system.cpu0.num_load_insts                    4794790                       # Number of load instructions
+system.cpu0.num_store_insts                   3396973                       # Number of store instructions
+system.cpu0.num_idle_cycles              905786099.867998                       # Number of idle cycles
+system.cpu0.num_busy_cycles              22683877.132002                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024431                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975569                       # Percentage of idle cycles
+system.cpu0.Branches                          4797930                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1559380      5.13%      5.13% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 19980835     65.68%     70.81% # Class of executed instruction
+system.cpu0.op_class::IntMult                   31353      0.10%     70.91% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     70.91% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12822      0.04%     70.95% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     70.95% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     70.95% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     70.95% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1598      0.01%     70.96% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.96% # Class of executed instruction
+system.cpu0.op_class::MemRead                 4924664     16.19%     87.15% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3400050     11.18%     98.32% # Class of executed instruction
+system.cpu0.op_class::IprAccess                510577      1.68%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  31482554                       # Class of executed instruction
+system.cpu0.op_class::total                  30421279                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6422                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211358                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6420                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211362                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
@@ -435,11 +432,11 @@ system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # nu
 system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1818800243000     98.76%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               38808500      0.00%     98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              357216000      0.02%     98.79% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22351032000      1.21%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1841547299500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1818807757000     98.77%     98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               38797500      0.00%     98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              357175000      0.02%     98.79% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22331016000      1.21%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1841534745500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -503,429 +500,429 @@ system.cpu0.kern.mode_switch_good::kernel     0.321851                       # f
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      0.080745                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     0.390894                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29750547000      1.62%      1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2575384000      0.14%      1.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1809221366500     98.24%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel       29743380000      1.62%      1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2567925500      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1809223438000     98.25%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
-system.cpu0.dcache.tags.replacements          1393348                       # number of replacements
+system.cpu0.dcache.tags.replacements          1392924                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997816                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13255372                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393860                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.509830                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           13249026                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393436                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.508170                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   177.816582                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   164.221248                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   169.959986                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.347298                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.320745                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.331953                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   177.335991                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   163.453449                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   171.208376                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.346359                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.319245                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.334391                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63362265                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63362265                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      3956098                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1080024                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2536463                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7572585                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3101293                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       830391                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1367001                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5298685                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113681                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19703                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51298                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184682                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122268                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21809                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55240                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199317                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7057391                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1910415                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3903464                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12871270                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7057391                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1910415                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3903464                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12871270                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       706776                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        97332                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       562527                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1366635                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       162364                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        44132                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       644654                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       851150                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9134                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2235                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7668                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19037                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data           10                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       869140                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       141464                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1207181                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2217785                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       869140                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       141464                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1207181                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2217785                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2268250000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8231829500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  10500079500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1752940000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19634310548                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  21387250548                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     29559000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    124972000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    154531000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       170500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       170500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4021190000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27866140048                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31887330048                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4021190000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27866140048                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31887330048                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4662874                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1177356                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3098990                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8939220                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3263657                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       874523                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2011655                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6149835                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       122815                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21938                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58966                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203719                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122268                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21809                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55250                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses         63330121                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63330121                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      3955641                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1077876                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2532941                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7566458                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3102475                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       828519                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1367883                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5298877                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113517                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19685                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51083                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184285                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122198                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21798                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55320                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199316                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7058116                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1906395                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3900824                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12865335                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7058116                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1906395                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3900824                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12865335                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       705857                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        97562                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       561486                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1364905                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       162429                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        43967                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       644644                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       851040                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9228                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2243                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7808                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19279                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data           11                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       868286                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       141529                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1206130                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2215945                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       868286                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       141529                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1206130                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2215945                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2272668500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8215053500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  10487722000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1750811500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19626601777                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  21377413277                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     29663000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    127096500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    156759500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       184000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       184000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   4023480000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  27841655277                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  31865135277                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   4023480000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  27841655277                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  31865135277                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4661498                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1175438                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3094427                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8931363                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3264904                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       872486                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2012527                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6149917                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       122745                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21928                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58891                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       203564                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122198                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21798                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55331                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       199327                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      7926531                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2051879                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5110645                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15089055                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      7926531                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2051879                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5110645                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15089055                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151575                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082670                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181519                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.152881                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049749                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050464                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.320460                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.138402                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.074372                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.101878                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130041                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.093447                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000181                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000050                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109649                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.068944                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.236209                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.146980                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109649                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.068944                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.236209                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.146980                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23304.257593                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14633.661140                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  7683.163025                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39720.384302                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30457.129791                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25127.475237                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13225.503356                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16297.861242                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8117.402952                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        17050                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        17050                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28425.535825                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.646983                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14378.007809                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28425.535825                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.646983                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14378.007809                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1019885                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         1764                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            60259                       # number of cycles access was blocked
+system.cpu0.dcache.demand_accesses::cpu0.data      7926402                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2047924                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5106954                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15081280                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      7926402                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2047924                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5106954                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15081280                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151423                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083001                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181451                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.152822                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049750                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050393                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.320316                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.138382                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075180                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.102289                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.132584                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094707                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000199                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000055                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109544                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069109                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.236174                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.146933                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109544                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069109                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.236174                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.146933                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23294.607532                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14630.914217                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  7683.847594                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39821.036232                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30445.644072                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25119.163937                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13224.699064                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16277.727971                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8131.101198                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16727.272727                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16727.272727                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28428.661264                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.461382                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14379.930584                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28428.661264                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.461382                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14379.930584                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1023083                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         1722                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            60080                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets             18                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.925024                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets           98                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    17.028678                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    95.666667                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835740                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835740                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       292598                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       292598                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       548626                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       548626                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1690                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1690                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       841224                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       841224                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       841224                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       841224                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        97332                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       269929                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       367261                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44132                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        96028                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       140160                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2235                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5978                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8213                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           10                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       141464                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       365957                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       507421                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       141464                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       365957                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       507421                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1108                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1559                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2667                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1387                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.writebacks::writebacks       835650                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835650                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       291568                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       291568                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       548541                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       548541                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1641                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1641                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       840109                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       840109                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       840109                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       840109                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        97562                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       269918                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       367480                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43967                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        96103                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       140070                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2243                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6167                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8410                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           11                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       141529                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       366021                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       507550                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       141529                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       366021                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       507550                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1107                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1558                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2665                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1386                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2128                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3515                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2495                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3687                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6182                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2170918000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4426676000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6597594000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1708808000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3106661815                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4815469815                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     27324000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     74701500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102025500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       160500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       160500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3879726000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7533337815                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11413063815                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3879726000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7533337815                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11413063815                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    226454500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    334463500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    560918000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298425500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    450956500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    749382000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    524880000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    785420000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1310300000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082670                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087102                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041084                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050464                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047736                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022791                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.101878                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.101380                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040315                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000181                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000050                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.068944                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071607                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.033628                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.068944                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071607                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.033628                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        16050                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        16050                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175                       # average overall mshr uncacheable latency
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3514                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2493                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3686                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6179                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2175106500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4426228500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6601335000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1706844500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3108596312                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4815440812                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     27420000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     77097500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104517500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       173000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       173000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3881951000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7534824812                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11416775812                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3881951000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7534824812                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11416775812                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    226227500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    334192500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    560420000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298200000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    450969000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    749169000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    524427500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    785161500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1309589000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083001                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087227                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041145                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050393                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047752                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022776                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.102289                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.104719                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.041314                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000199                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000055                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069109                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071671                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033654                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069109                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071671                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.033654                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22294.607532                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16398.419150                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17963.793948                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38821.036232                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32346.506477                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34378.816392                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12224.699064                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12501.621534                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12427.764566                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15727.272727                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15727.272727                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27428.661264                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.771887                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22493.893827                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27428.661264                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.771887                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22493.893827                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204360.885276                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214500.962773                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210288.930582                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215151.515152                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211921.522556                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.503699                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210360.008022                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213011.801411                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211941.899984                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           965393                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.914113                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           41264625                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           965904                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            42.721249                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10188445500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   146.904249                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   135.394605                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   228.615259                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.286922                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.264443                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.446514                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997879                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           963177                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.919668                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           40183368                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           963688                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            41.697487                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10187899500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   148.948748                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   136.141622                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   225.829298                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.290916                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.265902                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.441073                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997890                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43213951                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43213951                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     30975792                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7803098                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2485735                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       41264625                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     30975792                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7803098                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2485735                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        41264625                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     30975792                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7803098                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2485735                       # number of overall hits
-system.cpu0.icache.overall_hits::total       41264625                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       506762                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       129019                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       347436                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       983217                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       506762                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       129019                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       347436                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        983217                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       506762                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       129019                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       347436                       # number of overall misses
-system.cpu0.icache.overall_misses::total       983217                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1839982500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4838575988                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6678558488                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1839982500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4838575988                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6678558488                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1839982500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4838575988                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6678558488                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     31482554                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7932117                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2833171                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     42247842                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     31482554                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7932117                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2833171                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     42247842                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     31482554                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7932117                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2833171                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     42247842                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016097                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016265                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122631                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023273                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016097                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016265                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122631                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023273                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016097                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016265                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122631                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023273                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14261.329727                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13926.524563                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6792.557989                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14261.329727                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13926.524563                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6792.557989                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14261.329727                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13926.524563                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6792.557989                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3935                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42127818                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42127818                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29914547                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7792823                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2475998                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       40183368                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29914547                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7792823                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2475998                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        40183368                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29914547                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7792823                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2475998                       # number of overall hits
+system.cpu0.icache.overall_hits::total       40183368                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       506732                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       128884                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       344958                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       980574                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       506732                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       128884                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       344958                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        980574                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       506732                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       128884                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       344958                       # number of overall misses
+system.cpu0.icache.overall_misses::total       980574                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1840159000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4813824984                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6653983984                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1840159000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4813824984                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6653983984                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1840159000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4813824984                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6653983984                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30421279                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7921707                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2820956                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     41163942                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30421279                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7921707                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2820956                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     41163942                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30421279                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7921707                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2820956                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     41163942                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016657                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016270                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122284                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.023821                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016657                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016270                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122284                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.023821                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016657                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016270                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122284                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.023821                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14277.637255                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13954.814743                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6785.805033                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14277.637255                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13954.814743                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6785.805033                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14277.637255                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13954.814743                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6785.805033                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4577                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              210                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              237                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.738095                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.312236                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        17108                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        17108                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        17108                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        17108                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        17108                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        17108                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       129019                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       330328                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       459347                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       129019                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       330328                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       459347                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       129019                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       330328                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       459347                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1710963500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4315526491                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6026489991                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1710963500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4315526491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6026489991                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1710963500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4315526491                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6026489991                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016265                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116593                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010873                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016265                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116593                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010873                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016265                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116593                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010873                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13261.329727                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13064.367813                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13119.689453                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16698                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16698                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16698                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16698                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16698                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16698                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       128884                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       328260                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       457144                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       128884                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       328260                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       457144                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       128884                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       328260                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       457144                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1711275000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4293223488                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6004498488                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1711275000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4293223488                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6004498488                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1711275000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4293223488                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6004498488                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016270                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116365                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011105                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016270                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116365                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.011105                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016270                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116365                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.011105                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13277.637255                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13078.728715                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13134.807605                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13277.637255                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13078.728715                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13134.807605                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13277.637255                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13078.728715                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13134.807605                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1196955                       # DTB read hits
+system.cpu1.dtb.read_hits                     1195033                       # DTB read hits
 system.cpu1.dtb.read_misses                      1325                       # DTB read misses
 system.cpu1.dtb.read_acv                           35                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  141268                       # DTB read accesses
-system.cpu1.dtb.write_hits                     896481                       # DTB write hits
+system.cpu1.dtb.write_hits                     894434                       # DTB write hits
 system.cpu1.dtb.write_misses                      169                       # DTB write misses
 system.cpu1.dtb.write_acv                          22                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  57742                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2093436                       # DTB hits
+system.cpu1.dtb.write_accesses                  56923                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2089467                       # DTB hits
 system.cpu1.dtb.data_misses                      1494                       # DTB misses
 system.cpu1.dtb.data_acv                           57                       # DTB access violations
-system.cpu1.dtb.data_accesses                  199010                       # DTB accesses
-system.cpu1.itb.fetch_hits                     858438                       # ITB hits
+system.cpu1.dtb.data_accesses                  198191                       # DTB accesses
+system.cpu1.itb.fetch_hits                     856224                       # ITB hits
 system.cpu1.itb.fetch_misses                      659                       # ITB misses
 system.cpu1.itb.fetch_acv                          35                       # ITB acv
-system.cpu1.itb.fetch_accesses                 859097                       # ITB accesses
+system.cpu1.itb.fetch_accesses                 856883                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -938,64 +935,64 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953273349                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953248779                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7930565                       # Number of instructions committed
-system.cpu1.committedOps                      7930565                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7389333                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 45920                       # Number of float alu accesses
-system.cpu1.num_func_calls                     207460                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1022605                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7389333                       # number of integer instructions
-system.cpu1.num_fp_insts                        45920                       # number of float instructions
-system.cpu1.num_int_register_reads           10362144                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5369975                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24736                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              25085                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2100568                       # number of memory refs
-system.cpu1.num_load_insts                    1201762                       # Number of load instructions
-system.cpu1.num_store_insts                    898806                       # Number of store instructions
-system.cpu1.num_idle_cycles              922154358.750069                       # Number of idle cycles
-system.cpu1.num_busy_cycles              31118990.249931                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.032644                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.967356                       # Percentage of idle cycles
-system.cpu1.Branches                          1296677                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               410840      5.18%      5.18% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  5240708     66.07%     71.25% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8731      0.11%     71.36% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     71.36% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   5176      0.07%     71.42% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     71.42% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     71.42% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     71.42% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    810      0.01%     71.43% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.43% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1230901     15.52%     86.95% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 900034     11.35%     98.30% # Class of executed instruction
-system.cpu1.op_class::IprAccess                134916      1.70%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                    7920155                       # Number of instructions committed
+system.cpu1.committedOps                      7920155                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              7379126                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 45865                       # Number of float alu accesses
+system.cpu1.num_func_calls                     207333                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1021718                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     7379126                       # number of integer instructions
+system.cpu1.num_fp_insts                        45865                       # number of float instructions
+system.cpu1.num_int_register_reads           10346831                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5362502                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               24725                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              25053                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2096589                       # number of memory refs
+system.cpu1.num_load_insts                    1199833                       # Number of load instructions
+system.cpu1.num_store_insts                    896756                       # Number of store instructions
+system.cpu1.num_idle_cycles              922000099.418594                       # Number of idle cycles
+system.cpu1.num_busy_cycles              31248679.581406                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.032781                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.967219                       # Percentage of idle cycles
+system.cpu1.Branches                          1295631                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               410705      5.18%      5.18% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  5234650     66.08%     71.26% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8605      0.11%     71.37% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     71.37% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5163      0.07%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     71.44% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    810      0.01%     71.45% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.45% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1228944     15.51%     86.96% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 897985     11.34%     98.30% # Class of executed instruction
+system.cpu1.op_class::IprAccess                134844      1.70%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7932116                       # Class of executed instruction
+system.cpu1.op_class::total                   7921706                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1013,35 +1010,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups               10402334                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9657881                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           126933                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             8330137                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                6272162                       # Number of BTB hits
+system.cpu2.branchPred.lookups               11475270                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         10735483                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           123474                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             9110272                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                7311084                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            75.294824                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 302639                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect              7723                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            80.250996                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 301261                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect              7742                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3549115                       # DTB read hits
-system.cpu2.dtb.read_misses                     12776                       # DTB read misses
-system.cpu2.dtb.read_acv                          157                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  225358                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2157791                       # DTB write hits
-system.cpu2.dtb.write_misses                     2831                       # DTB write misses
-system.cpu2.dtb.write_acv                         142                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  84650                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5706906                       # DTB hits
-system.cpu2.dtb.data_misses                     15607                       # DTB misses
-system.cpu2.dtb.data_acv                          299                       # DTB access violations
-system.cpu2.dtb.data_accesses                  310008                       # DTB accesses
-system.cpu2.itb.fetch_hits                     538598                       # ITB hits
-system.cpu2.itb.fetch_misses                     5991                       # ITB misses
-system.cpu2.itb.fetch_acv                         159                       # ITB acv
-system.cpu2.itb.fetch_accesses                 544589                       # ITB accesses
+system.cpu2.dtb.read_hits                     3542926                       # DTB read hits
+system.cpu2.dtb.read_misses                     12527                       # DTB read misses
+system.cpu2.dtb.read_acv                          162                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  225242                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2156991                       # DTB write hits
+system.cpu2.dtb.write_misses                     2860                       # DTB write misses
+system.cpu2.dtb.write_acv                         147                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  84372                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5699917                       # DTB hits
+system.cpu2.dtb.data_misses                     15387                       # DTB misses
+system.cpu2.dtb.data_acv                          309                       # DTB access violations
+system.cpu2.dtb.data_accesses                  309614                       # DTB accesses
+system.cpu2.itb.fetch_hits                     534150                       # ITB hits
+system.cpu2.itb.fetch_misses                     5562                       # ITB misses
+system.cpu2.itb.fetch_acv                         158                       # ITB acv
+system.cpu2.itb.fetch_accesses                 539712                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1054,304 +1051,304 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        30759536                       # number of cpu cycles simulated
+system.cpu2.numCycles                        31796057                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9338114                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      39735788                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   10402334                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6574801                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     19282744                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 413720                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                       277                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                9678                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1944                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       234903                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       108900                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          473                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2833173                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                93993                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          29183655                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.361577                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.367035                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9294739                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      42846452                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   11475270                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           7612345                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     20400927                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 406592                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                       934                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                9632                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1958                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       201207                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       109893                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          558                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2820959                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                91095                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          30222906                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.417681                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.345063                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                20063773     68.75%     68.75% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  307542      1.05%     69.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  477296      1.64%     71.44% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4654234     15.95%     87.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  859104      2.94%     90.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  198525      0.68%     91.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  235442      0.81%     91.82% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  432653      1.48%     93.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1955086      6.70%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                20065674     66.39%     66.39% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  304778      1.01%     67.40% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  474119      1.57%     68.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 5709833     18.89%     87.86% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  849889      2.81%     90.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  195244      0.65%     91.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  232616      0.77%     92.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  433559      1.43%     93.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1957194      6.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            29183655                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.338182                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.291820                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7672062                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             13049396                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  7739525                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               528158                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                193789                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              177139                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                13443                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36353966                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                42512                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                193789                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7950274                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4574250                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       6325048                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  7961138                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2178432                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35523870                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                60190                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                394243                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 57916                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               1115509                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           23763436                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             44289897                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        44229633                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            56339                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             21842362                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1921074                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            535035                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         63809                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3839801                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3528507                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2250963                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           468940                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          330687                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32977065                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             683079                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 32678030                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            15337                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2566331                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1147551                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        488786                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     29183655                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.119737                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.624192                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            30222906                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.360902                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.347540                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7641311                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             13078900                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  8781400                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               530431                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                190274                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              176731                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13389                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              39469462                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                42545                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                190274                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7916618                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4614900                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6334560                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  9009266                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2156706                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              38654408                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                61763                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                395728                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 57668                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               1091797                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           25842385                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             48471958                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        48411597                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            56430                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             23967156                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1875229                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            535043                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         63361                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3828496                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3518120                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2250866                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           468779                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          334709                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  36116015                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             683906                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 35834403                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            15167                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2521371                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1120007                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        489344                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     30222906                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.185670                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.632890                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           17436459     59.75%     59.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2753806      9.44%     69.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1377159      4.72%     73.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            5375832     18.42%     92.32% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1030141      3.53%     95.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             601956      2.06%     97.92% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             392573      1.35%     99.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             169204      0.58%     99.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              46525      0.16%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           17428882     57.67%     57.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2748935      9.10%     66.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1369590      4.53%     71.29% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            6435558     21.29%     92.59% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1033977      3.42%     96.01% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             595062      1.97%     97.98% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             394555      1.31%     99.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             169710      0.56%     99.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              46637      0.15%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       29183655                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       30222906                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  85386     21.51%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.51% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                184726     46.54%     68.05% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               126802     31.95%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  86081     21.74%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                183352     46.31%     68.05% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               126504     31.95%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             26465043     80.99%     80.99% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21101      0.06%     81.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              20515      0.06%     81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3679518     11.26%     92.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2182790      6.68%     99.07% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            305379      0.93%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             29630335     82.69%     82.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21208      0.06%     82.75% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.75% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              20533      0.06%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3671135     10.24%     93.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2181666      6.09%     99.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            305842      0.85%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              32678030                       # Type of FU issued
-system.cpu2.iq.rate                          1.062371                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     396914                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.012146                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          94697637                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         36112111                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     32047154                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             254329                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            120282                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       117366                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              32936079                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 136409                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          206083                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              35834403                       # Type of FU issued
+system.cpu2.iq.rate                          1.127008                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     395937                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.011049                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         102047941                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         39206340                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     35210799                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             254875                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            120668                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       117568                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              36091226                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 136658                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          206130                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       440040                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1257                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         6058                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       180485                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       426126                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1149                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5847                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       179431                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         5073                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       225988                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         5057                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       224722                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                193789                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                3993186                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               173385                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           35054322                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            55127                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3528507                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2250963                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            608084                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 13021                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               119091                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          6058                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         64339                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       136180                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              200519                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             32475558                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3570784                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           202472                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                190274                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                4003128                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               196899                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           38192826                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            53825                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3518120                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2250866                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            608609                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 12914                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               142416                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5847                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         60692                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       135198                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              195890                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             35634663                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3564372                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           199740                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1394178                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5736169                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 7344406                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2165385                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.055788                       # Inst execution rate
-system.cpu2.iew.wb_sent                      32207740                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     32164520                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 18733989                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 22461298                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1392905                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5729004                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 8402054                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2164632                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.120726                       # Inst execution rate
+system.cpu2.iew.wb_sent                      35371199                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     35328367                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 20848782                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 24577214                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.045676                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.834056                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.111093                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.848297                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2690484                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         194293                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           182480                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     28713100                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.125605                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.869287                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2641573                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         194562                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           179155                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     29759977                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.193046                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.869762                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     18196306     63.37%     63.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2254505      7.85%     71.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1188955      4.14%     75.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      5110402     17.80%     93.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       563606      1.96%     95.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       199238      0.69%     95.82% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       165515      0.58%     96.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       164290      0.57%     96.97% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       870283      3.03%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18187552     61.11%     61.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2254342      7.58%     68.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1186941      3.99%     72.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      6165862     20.72%     93.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       562678      1.89%     95.29% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       198394      0.67%     95.95% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       165216      0.56%     96.51% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       166703      0.56%     97.07% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       872289      2.93%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     28713100                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            32319619                       # Number of instructions committed
-system.cpu2.commit.committedOps              32319619                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     29759977                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            35505021                       # Number of instructions committed
+system.cpu2.commit.committedOps              35505021                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5158945                       # Number of memory references committed
-system.cpu2.commit.loads                      3088467                       # Number of loads committed
-system.cpu2.commit.membars                      68233                       # Number of memory barriers committed
-system.cpu2.commit.branches                   7171529                       # Number of branches committed
-system.cpu2.commit.fp_insts                    115750                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 30796114                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              241665                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1228262      3.80%      3.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        25515212     78.95%     82.75% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20642      0.06%     82.81% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     82.81% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         20078      0.06%     82.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     82.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     82.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     82.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1228      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     82.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3156700      9.77%     92.64% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2072118      6.41%     99.06% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       305379      0.94%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5163429                       # Number of memory references committed
+system.cpu2.commit.loads                      3091994                       # Number of loads committed
+system.cpu2.commit.membars                      68344                       # Number of memory barriers committed
+system.cpu2.commit.branches                   8230032                       # Number of branches committed
+system.cpu2.commit.fp_insts                    115972                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 33980571                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              241816                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1228927      3.46%      3.46% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        28694755     80.82%     84.28% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20756      0.06%     84.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     84.34% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         20096      0.06%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1228      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     84.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3160338      8.90%     93.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2073079      5.84%     99.14% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       305842      0.86%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         32319619                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               870283                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                    62775514                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   70489103                       # The number of ROB writes
-system.cpu2.timesIdled                         177769                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1575881                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1745050657                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   31093813                       # Number of Instructions Simulated
-system.cpu2.committedOps                     31093813                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.989249                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.989249                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.010867                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.010867                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                42649325                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               22654905                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    71051                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   71293                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5005090                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                273836                       # number of misc regfile writes
+system.cpu2.commit.op_class_0::total         35505021                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               872289                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                    66956679                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   76754434                       # The number of ROB writes
+system.cpu2.timesIdled                         177058                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1573151                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1744013124                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   34278550                       # Number of Instructions Simulated
+system.cpu2.committedOps                     34278550                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              0.927579                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.927579                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.078075                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.078075                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                46864030                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               24760821                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    71108                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   71427                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                6062934                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                274246                       # number of misc regfile writes
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1406,7 +1403,7 @@ system.iobus.reqLayer1.occupancy               105000                       # La
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5370000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5366000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             1863000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
@@ -1416,21 +1413,21 @@ system.iobus.reqLayer27.occupancy                7000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy            89820170                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy            89821669                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             8849000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             8844000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            17468000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254241                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.254132                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1693892852000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254241                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078390                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078390                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1693892766000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.254132                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078383                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078383                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1446,8 +1443,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide      9418962                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total      9418962                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   2040792208                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2040792208                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   2040972707                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2040972707                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide      9418962                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total      9418962                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide      9418962                       # number of overall miss cycles
@@ -1470,8 +1467,8 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 54444.867052                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49118.519133                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 49118.519133                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 54444.867052                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052                       # average overall miss latency
@@ -1496,8 +1493,8 @@ system.iocache.overall_mshr_misses::tsunami.ide           70
 system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5918962                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total      5918962                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1176792208                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1176792208                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1176972707                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1176972707                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide      5918962                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total      5918962                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide      5918962                       # number of overall MSHR miss cycles
@@ -1512,219 +1509,219 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624
 system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68111.846470                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68111.846470                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 84556.600000                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 84556.600000                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   337481                       # number of replacements
-system.l2c.tags.tagsinuse                65419.198683                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4010491                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402643                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.960414                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337470                       # number of replacements
+system.l2c.tags.tagsinuse                65419.393999                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4005329                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402632                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.947866                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54563.896309                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2274.571035                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2764.017947                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      537.574504                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      599.716909                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2426.240023                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2253.181956                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.832579                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.034707                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.042176                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008203                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009151                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.037021                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.034381                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998218                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   54633.992785                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2282.515139                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2705.284872                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      536.585010                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      602.481810                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2408.251048                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2250.283336                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.833649                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.034828                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.041279                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.008188                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009193                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.036747                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.034337                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998221                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1020                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5977                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2679                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55308                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          997                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6046                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2595                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55346                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38452030                       # Number of tag accesses
-system.l2c.tags.data_accesses                38452030                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          835740                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835740                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 38409794                       # Number of tag accesses
+system.l2c.tags.data_accesses                38409794                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          835650                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835650                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data               9                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  13                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             8                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            89227                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            26157                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            71638                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187022                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        499466                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        126720                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        325465                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            951651                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       475379                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        83798                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       258654                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           817831                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              499466                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              564606                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              126720                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              109955                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              325465                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              330292                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1956504                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             499466                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             564606                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             126720                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             109955                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             325465                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             330292                       # number of overall hits
-system.l2c.overall_hits::total                1956504                       # number of overall hits
+system.l2c.UpgradeReq_hits::cpu2.data              10                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  14                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data             9                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 9                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            89264                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            25987                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            71674                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               186925                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        499428                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        126587                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst        323447                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total            949462                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       474572                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        84042                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data       258892                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           817506                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              499428                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              563836                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              126587                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              110029                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              323447                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              330566                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1953893                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             499428                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             563836                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             126587                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             110029                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             323447                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             330566                       # number of overall hits
+system.l2c.overall_hits::total                1953893                       # number of overall hits
 system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            22                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                30                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            11                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                19                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu2.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          73126                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          17974                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          24645                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115745                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         7275                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         2299                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         4804                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           14378                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       240531                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        15769                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data        16968                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         273268                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst              7275                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            313657                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2299                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             33743                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              4804                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             41613                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                403391                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst             7275                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           313657                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2299                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            33743                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             4804                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            41613                       # number of overall misses
-system.l2c.overall_misses::total               403391                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu2.data       332500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       332500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu2.data        61500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        61500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1367951000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2193367000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3561318000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    186458500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    394826500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total    581285000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   1169012500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   1264906000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   2433918500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    186458500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2536963500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    394826500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3458273000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      6576521500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    186458500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2536963500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    394826500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3458273000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     6576521500                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks       835740                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835740                       # number of Writeback accesses(hits+misses)
+system.l2c.ReadExReq_misses::cpu0.data          73154                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          17979                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          24640                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115773                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst         7283                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         2297                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst         4777                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           14357                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       240513                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data        15763                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data        16963                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         273239                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst              7283                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            313667                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2297                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             33742                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              4777                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             41603                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                403369                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst             7283                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           313667                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2297                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            33742                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             4777                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            41603                       # number of overall misses
+system.l2c.overall_misses::total               403369                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu2.data       364000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       364000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu2.data        62000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total        62000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1368020000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   2194273500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   3562293500                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    188368000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst    396841000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total    585209000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   1170378000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data   1263948500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total   2434326500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    188368000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2538398000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    396841000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   3458222000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      6581829000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    188368000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   2538398000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    396841000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   3458222000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     6581829000                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       835650                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835650                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           31                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              43                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data           10                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       162353                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        44131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        96283                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           302767                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       506741                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       129019                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst       330269                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total        966029                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       715910                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        99567                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data       275622                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1091099                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          506741                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          878263                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          129019                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          143698                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          330269                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          371905                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2359895                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         506741                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         878263                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         129019                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         143698                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         330269                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         371905                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2359895                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              33                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu2.data           11                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            11                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       162418                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        43966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        96314                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           302698                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       506711                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       128884                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst       328224                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total        963819                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       715085                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        99805                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data       275855                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      1090745                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          506711                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          877503                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          128884                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          143771                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          328224                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          372169                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2357262                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         506711                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         877503                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         128884                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         143771                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         328224                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         372169                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2357262                       # number of overall (read+write) accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.709677                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.697674                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.200000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.200000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.450414                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.407287                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.255964                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.382291                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014356                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.017819                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014546                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.014884                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.335979                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.158376                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.061563                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.250452                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014356                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.357133                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.017819                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.234819                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.014546                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.111891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.170936                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014356                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.357133                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.017819                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.234819                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.014546                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.111891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.170936                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15113.636364                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 11083.333333                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        30750                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        30750                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76107.210415                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88998.458105                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 30768.655233                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81104.175729                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82187.031640                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 40428.780081                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 74133.584882                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 74546.558227                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total  8906.708799                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81104.175729                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 75184.882791                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 82187.031640                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 83105.592002                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 16303.094268                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81104.175729                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 75184.882791                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 82187.031640                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 83105.592002                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 16303.094268                       # average overall miss latency
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.523810                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.575758                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.181818                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.181818                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.450406                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.408930                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.255830                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.382470                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014373                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.017822                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014554                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.014896                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.336342                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.157938                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.061492                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.250507                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014373                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.357454                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.017822                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.234693                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.014554                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.111785                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.171118                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014373                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.357454                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.017822                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.234693                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.014554                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.111785                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.171118                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 33090.909091                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 19157.894737                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        31000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        31000                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76089.882641                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 89053.307630                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 30769.639726                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82006.094906                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83073.267741                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 40761.231455                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 74248.429867                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 74512.085126                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total  8909.147303                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 82006.094906                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 75229.624800                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 83073.267741                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 83124.341995                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 16317.141377                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82006.094906                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 75229.624800                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 83073.267741                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 83124.341995                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 16317.141377                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1733,222 +1730,222 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75436                       # number of writebacks
-system.l2c.writebacks::total                    75436                       # number of writebacks
+system.l2c.writebacks::writebacks               75401                       # number of writebacks
+system.l2c.writebacks::total                    75401                       # number of writebacks
 system.l2c.CleanEvict_mshr_misses::writebacks          185                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total          185                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           22                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           22                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           11                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        17974                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        24645                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        17979                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        24640                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total         42619                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2299                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4804                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total         7103                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        15769                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        16968                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total        32737                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2299                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        33743                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4804                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        41613                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            82459                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2299                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        33743                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4804                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        41613                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           82459                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         1108                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         1559                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total         2667                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         1387                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2297                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4777                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         7074                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data        15763                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        16963                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total        32726                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2297                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        33742                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         4777                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        41603                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            82419                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2297                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        33742                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4777                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        41603                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           82419                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         1107                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         1558                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         2665                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         1386                       # number of WriteReq MSHR uncacheable
 system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2128                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total         3515                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2495                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data         3687                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total         6182                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       607000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       607000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        41500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        41500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1188211000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1946917000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   3135128000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    163468500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    346786500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    510255000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   1011322500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1095840500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   2107163000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    163468500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   2199533500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    346786500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3042757500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5752546000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    163468500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   2199533500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    346786500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3042757500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5752546000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    212604500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    314976000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    527580500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    282475000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    426484500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total    708959500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    495079500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    741460500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1236540000                       # number of overall MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable::total         3514                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2493                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data         3686                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total         6179                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       377000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       377000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        42000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        42000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1188230000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1947873500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3136103500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    165398000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    349071000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    514469000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   1012748000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1095055000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   2107803000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    165398000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2200978000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    349071000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3042928500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   5758375500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    165398000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2200978000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    349071000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3042928500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   5758375500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    212390000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    314717500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    527107500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    282261000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    426497000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    708758000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    494651000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    741214500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1235865500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.709677                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.511628                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.407287                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.255964                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.140765                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017819                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014546                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007353                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.158376                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.061563                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.030004                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017819                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.234819                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014546                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.111891                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.034942                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017819                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.234819                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014546                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.111891                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034942                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        20750                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        20750                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69762.500152                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69762.500152                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.523810                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.181818                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.181818                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.408930                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.255830                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.140797                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017822                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014554                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007340                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.157938                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.061492                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.030003                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017822                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.234693                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014554                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.111785                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034964                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017822                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.234693                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014554                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.111785                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034964                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 34272.727273                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 34272.727273                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        21000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        21000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66089.882641                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79053.307630                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 73584.633614                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72006.094906                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73073.267741                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72726.745830                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64248.429867                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64555.503154                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64407.596407                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72006.094906                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65229.624800                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73073.267741                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73142.045045                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 69867.087686                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72006.094906                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65229.624800                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73073.267741                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73142.045045                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69867.087686                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191860.885276                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202000.962773                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197788.930582                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203651.515152                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200421.522556                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.503699                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198415.964701                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201089.120998                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 200010.600421                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
-system.membus.trans_dist::ReadResp             294958                       # Transaction distribution
+system.membus.trans_dist::ReadResp             294907                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9810                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9810                       # Transaction distribution
-system.membus.trans_dist::Writeback            116948                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262295                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              165                       # Transaction distribution
+system.membus.trans_dist::Writeback            116913                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262319                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              141                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             167                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115610                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115610                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        287819                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            5                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             143                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115651                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115651                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        287769                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1144349                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           10                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1178267                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1144270                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1178190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125023                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       125023                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1303290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1303213                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30629632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30675200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30626752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30672320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2664320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33339520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33336640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              157                       # Total snoops (count)
-system.membus.snoop_fanout::samples            841413                       # Request fanout histogram
+system.membus.snoop_fanout::samples            841369                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  841413    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  841369    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              841413                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            11052000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              841369                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            11017000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           394258327                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           393892331                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy                7000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          441332932                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          441141955                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           29902743                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.trans_dist::ReadReq               7144                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2064402                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2061814                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq              9810                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp             9810                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           883212                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1574760                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              43                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             53                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302767                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302767                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        966109                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1091169                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            5                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           883059                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1572257                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              33                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             44                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302698                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302698                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        963876                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1090815                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        17280                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2897413                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4214892                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7112305                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61827200                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142743552                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              204570752                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          141567                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4877075                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.028983                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.167759                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2890767                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4213603                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7104370                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61685760                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142710656                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              204396416                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          141516                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4871742                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.029009                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.167832                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                4735723     97.10%     97.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 141352      2.90%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                4730418     97.10%     97.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 141324      2.90%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4877075                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1372572500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4871742                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1371248000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy            82500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         689392754                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         686121188                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         777864461                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         778360963                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index 1ce6d2d3e..d32706f99 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -179,7 +179,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -638,7 +638,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -748,7 +748,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -909,7 +909,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1368,7 +1368,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1478,7 +1478,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -1591,7 +1591,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1626,7 +1626,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -2041,9 +2041,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
index 7ec39e811..8e8bcf240 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:47:25
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:15:22
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2846057099000 because m5_exit instruction encountered
+Exiting @ tick 2846117015000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 934713496..535c26a20 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,162 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.846057                       # Number of seconds simulated
-sim_ticks                                2846057099000                       # Number of ticks simulated
-final_tick                               2846057099000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.846117                       # Number of seconds simulated
+sim_ticks                                2846117015000                       # Number of ticks simulated
+final_tick                               2846117015000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 157157                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190318                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3507683540                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 605024                       # Number of bytes of host memory used
-host_seconds                                   811.38                       # Real time elapsed on the host
-sim_insts                                   127513349                       # Number of instructions simulated
-sim_ops                                     154419501                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 113156                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137057                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2513496102                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 647580                       # Number of bytes of host memory used
+host_seconds                                  1132.33                       # Real time elapsed on the host
+sim_insts                                   128130877                       # Number of instructions simulated
+sim_ops                                     155193960                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         7744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         7296                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1469184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1233972                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8227712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         2752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           383104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           711064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       574528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1474816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1242668                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8247680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         2432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           378112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           721620                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       564672                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12611084                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1469184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       383104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1852288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8917568                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12640384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1474816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       378112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1852928                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8933696                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8935132                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          121                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8951260                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          114                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22956                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19804                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       128558                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           43                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11132                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         8977                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             23044                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             19938                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       128870                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           38                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             11296                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         8823                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197593                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          139337                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                198048                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          139589                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143728                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2721                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               143980                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2563                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              516217                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              433572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2890916                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              134609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              249842                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       201868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              518185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              436619                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2897871                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           854                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              132852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              253545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       198401                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4431072                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         516217                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         134609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             650826                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3133306                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4441273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         518185                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         132852                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             651037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3138907                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3139477                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3133306                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2721                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3145078                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3138907                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2563                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             516217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             439730                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2890916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             134609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             249856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       201868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             518185                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             442776                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2897871                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             132852                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             253559                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       198401                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7570549                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197593                       # Number of read requests accepted
-system.physmem.writeReqs                       143728                       # Number of write requests accepted
-system.physmem.readBursts                      197593                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     143728                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12635520                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10432                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8947648                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12611084                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8935132                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      163                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          51189                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12157                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12292                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12950                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12405                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15321                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12434                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12677                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13084                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12267                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12426                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11655                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11073                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11997                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11769                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11320                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11603                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8631                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8804                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9518                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8865                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8658                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8780                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9135                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9275                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8996                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8951                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8409                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8136                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8895                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8304                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8310                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8140                       # Per bank write bursts
+system.physmem.bw_total::total                7586351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        198048                       # Number of read requests accepted
+system.physmem.writeReqs                       143980                       # Number of write requests accepted
+system.physmem.readBursts                      198048                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     143980                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12666176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8963584                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12640384                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8951260                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          51245                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12439                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12567                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12508                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12584                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14823                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11920                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               13135                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13383                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12319                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12338                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11698                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11134                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11462                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11917                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11661                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              12021                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8771                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9038                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9230                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8945                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8307                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8620                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9591                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9703                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8875                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8727                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8430                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8199                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8380                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8472                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8531                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8237                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2846056522500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2846116455500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     555                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  197010                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  197468                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 139337                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     84527                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     62953                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     11439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9638                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7653                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       746                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      149                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 139589                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     85140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     62378                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11568                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7750                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5246                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4552                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3838                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       742                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      263                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      161                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -184,159 +188,155 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    10231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9581                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      140                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      106                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        90385                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      238.790065                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     135.540737                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     300.321787                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          48391     53.54%     53.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17645     19.52%     73.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6369      7.05%     80.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3664      4.05%     84.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2743      3.03%     87.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1397      1.55%     88.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          884      0.98%     89.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1036      1.15%     90.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8256      9.13%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          90385                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6985                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.264567                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      537.756673                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6984     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6985                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6985                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.015319                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.579154                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.029266                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5867     83.99%     83.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             359      5.14%     89.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             198      2.83%     91.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              50      0.72%     92.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              72      1.03%     93.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             159      2.28%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              19      0.27%     96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.17%     96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.16%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.11%     96.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.07%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             162      2.32%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.09%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              10      0.14%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.01%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.03%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            14      0.20%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6985                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5478181174                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9179993674                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    987150000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27747.46                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::53                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       33                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        91138                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.329061                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     134.886171                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     298.768529                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          49038     53.81%     53.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17709     19.43%     73.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6298      6.91%     80.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3704      4.06%     84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2913      3.20%     87.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1386      1.52%     88.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          897      0.98%     89.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1023      1.12%     91.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8170      8.96%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          91138                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6991                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.308683                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      556.324450                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6990     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6991                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6991                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.033758                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.625060                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.557866                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5837     83.49%     83.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             357      5.11%     88.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             222      3.18%     91.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              60      0.86%     92.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              64      0.92%     93.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             166      2.37%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              20      0.29%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.09%     96.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              14      0.20%     96.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.14%     96.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.07%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.13%     96.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             167      2.39%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               8      0.11%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.11%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               7      0.10%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.04%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.04%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.04%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.20%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6991                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5451252873                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9162046623                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    989545000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27544.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46497.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.43                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.14                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46294.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.45                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.15                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.99                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     164056                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82794                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8338357.51                       # Average gap between requests
-system.physmem.pageHitRate                      73.19                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  356771520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  194667000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 805888200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                464395680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185890376880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83219414895                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1634632736250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1905564250425                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.546132                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2719229075521                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95035980000                       # Time in different power states
+system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     164305                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82521                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.02                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8321296.66                       # Average gap between requests
+system.physmem.pageHitRate                      73.03                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  359440200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  196123125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 806200200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                467888400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185894445360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83210904225                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634677575750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1905612577260                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.548459                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2719308511052                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95038060000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31791929979                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31769437698                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  326539080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  178171125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 734050200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                441553680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185890376880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82136174355                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1635582947250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1905289812570                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.449705                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2720812978493                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95035980000                       # Time in different power states
+system.physmem_1.actEnergy                  329563080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179821125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 737482200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                439674480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185894445360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82251132525                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635519480750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1905351599520                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.456762                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2720714979061                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95038060000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30205644507                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30363879439                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
@@ -362,15 +362,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               19599196                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         12768904                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           991514                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            12558764                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                8839837                       # Number of BTB hits
+system.cpu0.branchPred.lookups               34784409                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         16478031                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1480168                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            19725615                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               14342133                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            70.387795                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3295346                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            199810                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.708167                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               11162624                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            702720                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -401,58 +401,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    67395                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               67395                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44710                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22685                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        67395                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          67395    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        67395                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6692                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9352.624092                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5969.180600                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6501     97.15%     97.15% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          173      2.59%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           11      0.16%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.07%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6692                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                    65972                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               65972                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        43486                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22486                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        65972                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          65972    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        65972                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6612                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10372.504537                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9312.931281                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6218.139441                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6425     97.17%     97.17% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          170      2.57%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151            7      0.11%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.08%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687            4      0.06%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6612                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    327753000                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      327753000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    327753000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5137     76.76%     76.76% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1555     23.24%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6692                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67395                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5105     77.21%     77.21% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1507     22.79%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6612                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65972                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67395                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6692                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65972                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6612                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6692                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        74087                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6612                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        72584                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    16492967                       # DTB read hits
-system.cpu0.dtb.read_misses                     61485                       # DTB read misses
-system.cpu0.dtb.write_hits                   13879033                       # DTB write hits
-system.cpu0.dtb.write_misses                     5910                       # DTB write misses
+system.cpu0.dtb.read_hits                    23562231                       # DTB read hits
+system.cpu0.dtb.read_misses                     59962                       # DTB read misses
+system.cpu0.dtb.write_hits                   17431474                       # DTB write hits
+system.cpu0.dtb.write_misses                     6010                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3512                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1104                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1584                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3494                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1076                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1600                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      553                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                16554452                       # DTB read accesses
-system.cpu0.dtb.write_accesses               13884943                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      577                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                23622193                       # DTB read accesses
+system.cpu0.dtb.write_accesses               17437484                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         30372000                       # DTB hits
-system.cpu0.dtb.misses                          67395                       # DTB misses
-system.cpu0.dtb.accesses                     30439395                       # DTB accesses
+system.cpu0.dtb.hits                         40993705                       # DTB hits
+system.cpu0.dtb.misses                          65972                       # DTB misses
+system.cpu0.dtb.accesses                     41059677                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -482,36 +482,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3867                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3867                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3560                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3867                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3867    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3867                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2421                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9615.276250                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  7885.681727                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767         2419     99.92%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     3855                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3855                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          305                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3550                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3855                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3855    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3855                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2424                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10979.785479                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9797.993767                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  8035.967164                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767         2422     99.92%     99.92% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::32768-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2421                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2424                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    327059500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      327059500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    327059500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2121     87.61%     87.61% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          300     12.39%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2421                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         2124     87.62%     87.62% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          300     12.38%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2424                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3867                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3867                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3855                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3855                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2421                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2421                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6288                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    36759532                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3867                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2424                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2424                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6279                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    68397916                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3855                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -520,131 +520,131 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2224                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2226                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7295                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7522                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                36763399                       # ITB inst accesses
-system.cpu0.itb.hits                         36759532                       # DTB hits
-system.cpu0.itb.misses                           3867                       # DTB misses
-system.cpu0.itb.accesses                     36763399                       # DTB accesses
-system.cpu0.numCycles                       154883476                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                68401771                       # ITB inst accesses
+system.cpu0.itb.hits                         68397916                       # DTB hits
+system.cpu0.itb.misses                           3855                       # DTB misses
+system.cpu0.itb.accesses                     68401771                       # DTB accesses
+system.cpu0.numCycles                       225406925                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   75627253                       # Number of instructions committed
-system.cpu0.committedOps                     91033342                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      4957970                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     2062                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5537267530                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.047985                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.488285                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  107236402                       # Number of instructions committed
+system.cpu0.committedOps                    129680129                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      8567834                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     2087                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5466862375                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.101963                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.475746                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2064                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      121009607                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       33873869                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           680149                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          489.017964                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           28930962                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           680661                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            42.504216                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    2088                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      187552407                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       37854518                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           678280                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          485.010035                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           39540240                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           678792                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            58.250893                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        345600000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   489.017964                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.955113                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.955113                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.010035                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947285                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.947285                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         60723709                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        60723709                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15008806                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       15008806                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     12795540                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      12795540                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306691                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       306691                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       356713                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       356713                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352309                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       352309                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     27804346                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        27804346                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     28111037                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       28111037                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       442745                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       442745                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       557072                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       557072                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131875                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       131875                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21262                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21262                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21236                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21236                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       999817                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        999817                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1131692                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1131692                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5845429500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5845429500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8925410000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   8925410000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    323710500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    323710500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    479970000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    479970000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       445000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       445000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  14770839500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  14770839500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  14770839500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  14770839500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15451551                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     15451551                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13352612                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13352612                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       438566                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       438566                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       377975                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       377975                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373545                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       373545                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     28804163                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     28804163                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     29242729                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     29242729                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028654                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028654                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041720                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.041720                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300696                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300696                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056252                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056252                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056850                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056850                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034711                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.034711                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038700                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.038700                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         81933612                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        81933612                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     22071197                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       22071197                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     16340314                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      16340314                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       307086                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       307086                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       357744                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       357744                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352756                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       352756                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     38411511                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        38411511                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     38718597                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       38718597                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       442022                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       442022                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       555005                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       555005                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131972                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       131972                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20768                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20768                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21303                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        21303                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       997027                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        997027                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1128999                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1128999                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5846536500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5846536500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8888918500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8888918500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    319234500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    319234500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    481221000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    481221000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       684000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       684000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  14735455000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  14735455000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  14735455000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  14735455000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     22513219                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     22513219                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     16895319                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     16895319                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       439058                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       439058                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378512                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       378512                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       374059                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       374059                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     39408538                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     39408538                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     39847596                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     39847596                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019634                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.019634                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032850                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.032850                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300580                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300580                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054867                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054867                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056951                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056951                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025300                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.025300                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028333                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.028333                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13226.799797                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13226.799797                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16015.925082                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 16015.925082                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15371.460901                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15371.460901                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22589.353612                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22589.353612                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14779.394139                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14779.394139                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.787468                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13051.787468                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -653,149 +653,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       493052                       # number of writebacks
-system.cpu0.dcache.writebacks::total           493052                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69962                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        69962                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       244118                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       244118                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15072                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15072                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       314080                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       314080                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       314080                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       314080                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372783                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       372783                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312954                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       312954                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99314                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        99314                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6190                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6190                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21236                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21236                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       685737                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       685737                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       785051                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       785051                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18001                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16756                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34757                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4391149500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4391149500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4970740000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4970740000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1612906500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1612906500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94756000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94756000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    458745000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    458745000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       434000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       434000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9361889500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9361889500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10974796000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10974796000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3751362500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3751362500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2725552500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2725552500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6476915000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6476915000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024126                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024126                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023438                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023438                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226452                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226452                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016377                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016377                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056850                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056850                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023807                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023807                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026846                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026846                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       490245                       # number of writebacks
+system.cpu0.dcache.writebacks::total           490245                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69954                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        69954                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       243081                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       243081                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14749                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14749                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       313035                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       313035                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       313035                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       313035                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372068                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       372068                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       311924                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       311924                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99410                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        99410                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6019                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6019                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21303                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        21303                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       683992                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       683992                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       783402                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       783402                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29426                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29426                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26162                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26162                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55588                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55588                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4399139000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4399139000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4959161000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4959161000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1608557500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1608557500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     92509500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     92509500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459936000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459936000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       666000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       666000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9358300000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9358300000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10966857500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10966857500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5696567000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5696567000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4315116500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4315116500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10011683500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10011683500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016527                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016527                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018462                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018462                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226417                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226417                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.015902                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056951                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056951                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017356                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.017356                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019660                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.019660                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11823.481192                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11823.481192                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15898.619536                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15898.619536                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16181.043155                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16181.043155                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15369.579664                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15369.579664                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21590.198564                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21590.198564                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13681.885168                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13681.885168                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13999.016469                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13999.016469                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193589.580643                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193589.580643                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164938.326581                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 164938.326581                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180105.121609                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 180105.121609                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1879741                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.785261                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           34871642                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1880253                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            18.546250                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6165545000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.785261                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999581                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999581                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1886353                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.780174                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           66503170                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1886865                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.245325                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6541312000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.780174                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999571                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999571                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          216                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         75384087                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        75384087                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     34871642                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34871642                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     34871642                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34871642                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     34871642                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34871642                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1880268                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1880268                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1880268                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1880268                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1880268                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1880268                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17494991000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  17494991000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  17494991000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  17494991000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  17494991000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  17494991000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     36751910                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     36751910                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     36751910                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     36751910                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     36751910                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     36751910                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051161                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.051161                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051161                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.051161                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051161                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.051161                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9304.519888                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9304.519888                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9304.519888                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9304.519888                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9304.519888                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9304.519888                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        138666991                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       138666991                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     66503170                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       66503170                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     66503170                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        66503170                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     66503170                       # number of overall hits
+system.cpu0.icache.overall_hits::total       66503170                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1886884                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1886884                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1886884                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1886884                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1886884                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1886884                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17552107500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  17552107500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  17552107500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  17552107500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  17552107500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  17552107500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     68390054                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     68390054                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     68390054                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     68390054                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     68390054                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     68390054                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.027590                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.027590                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.027590                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.027590                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.027590                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.027590                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9302.165634                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9302.165634                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9302.165634                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9302.165634                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9302.165634                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9302.165634                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -804,463 +804,463 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1880268                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1880268                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1880268                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1880268                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1880268                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1880268                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1886884                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1886884                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1886884                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1886884                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1886884                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1886884                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3426                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3426                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16554857500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16554857500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16554857500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16554857500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16554857500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16554857500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16608666000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  16608666000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16608666000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  16608666000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16608666000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  16608666000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    314279000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    314279000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051161                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.051161                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051161                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.051161                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8804.520154                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8804.520154                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8804.520154                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8804.520154                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027590                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027590                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027590                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027590                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027590                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027590                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8802.165899                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8802.165899                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8802.165899                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  8802.165899                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8802.165899                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  8802.165899                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1762988                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1763146                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          137                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1753692                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1753724                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       223158                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          285163                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16064.441291                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           4801094                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          301400                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           15.929310                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       222140                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          284631                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16080.562269                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           4811395                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          300867                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           15.991767                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  8613.892017                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    45.679204                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.072727                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4663.239886                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1620.721287                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1120.836170                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.525750                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002788                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks  8557.843574                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    57.688699                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.065125                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4677.760567                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1660.845415                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1126.358889                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.522329                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003521                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.284622                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.098921                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068410                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.980496                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1029                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15199                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          305                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          401                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          310                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4239                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7941                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2698                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062805                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927673                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        85389688                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       85389688                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        78899                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4233                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         83132                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       493050                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       493050                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28200                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28200                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1701                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1701                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212815                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       212815                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1816263                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1816263                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       377267                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       377267                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        78899                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4233                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1816263                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       590082                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2489477                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        78899                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4233                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1816263                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       590082                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2489477                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          767                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          105                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          872                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27843                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27843                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19534                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19534                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44100                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        44100                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        64005                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        64005                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101018                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       101018                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          767                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          105                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        64005                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       145118                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       209995                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          767                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          105                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        64005                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       145118                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       209995                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     26175500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2558000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     28733500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    514961000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    514961000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    395123500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    395123500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       417500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       417500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2206381000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2206381000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2858183000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2858183000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2907472497                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2907472497                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     26175500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2558000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2858183000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5113853497                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   8000769997                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     26175500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2558000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2858183000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5113853497                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   8000769997                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        79666                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4338                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        84004                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       493050                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       493050                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56043                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        56043                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21235                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        21235                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       256915                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       256915                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1880268                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1880268                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       478285                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       478285                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        79666                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4338                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1880268                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       735200                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2699472                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        79666                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4338                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1880268                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       735200                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2699472                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.010380                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.496815                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.496815                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.919896                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.919896                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.285508                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.101370                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068747                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.981480                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1014                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15208                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          351                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          393                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          258                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          273                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4117                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7919                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2851                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061890                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.928223                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        85529410                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       85529410                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77804                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4292                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         82096                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       490243                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       490243                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28207                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28207                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1765                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1765                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212310                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       212310                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1823174                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1823174                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376441                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       376441                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77804                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4292                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1823174                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       588751                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        2494021                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77804                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4292                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1823174                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       588751                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       2494021                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          777                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          131                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          908                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27955                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        27955                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19533                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        19533                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43457                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        43457                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        63710                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        63710                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101052                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       101052                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          777                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          131                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        63710                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       144509                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       209127                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          777                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          131                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        63710                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       144509                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       209127                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     26295000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3189000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     29484000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    514165000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    514165000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    396282000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    396282000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       637497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       637497                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2195149500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2195149500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2860433500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2860433500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2915473994                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2915473994                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     26295000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3189000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2860433500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   5110623494                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   8000540994                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     26295000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3189000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2860433500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   5110623494                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   8000540994                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78581                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4423                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        83004                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       490243                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       490243                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56162                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        56162                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21298                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        21298                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       255767                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       255767                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1886884                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1886884                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       477493                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       477493                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78581                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4423                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1886884                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       733260                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2703148                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78581                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4423                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1886884                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       733260                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2703148                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009888                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.029618                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.010939                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.497756                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.497756                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.917128                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.917128                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171652                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171652                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034040                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034040                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211209                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211209                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034040                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197386                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.077791                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009628                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.024205                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034040                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197386                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.077791                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32951.261468                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.169342                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.169342                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20227.475171                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20227.475171                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       417500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       417500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50031.315193                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50031.315193                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44655.620655                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44655.620655                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28781.726989                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28781.726989                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44655.620655                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35239.277671                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 38099.811886                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34127.118644                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24361.904762                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44655.620655                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35239.277671                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 38099.811886                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           60                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.169909                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.169909                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.033765                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.033765                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211630                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211630                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009888                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.029618                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.033765                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197077                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.077364                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009888                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.029618                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.033765                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197077                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.077364                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.698842                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24343.511450                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32471.365639                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18392.595242                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18392.595242                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20287.820611                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20287.820611                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 127499.400000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 127499.400000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50513.139425                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50513.139425                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44897.716214                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44897.716214                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28851.225052                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28851.225052                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.698842                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24343.511450                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44897.716214                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35365.433945                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 38256.853462                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.698842                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24343.511450                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44897.716214                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35365.433945                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 38256.853462                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           59                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    29.500000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       195910                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          195910                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2609                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         2609                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           70                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           70                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          363                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          363                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           70                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         2972                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         3042                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           70                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         2972                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         3042                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          767                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          105                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          872                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9288                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total         9288                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       233934                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       233934                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27843                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27843                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19534                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19534                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41491                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41491                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        63935                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        63935                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100655                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100655                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          767                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          105                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        63935                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142146                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       206953                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          767                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          105                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        63935                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142146                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       233934                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       440887                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       195819                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          195819                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2770                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         2770                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           71                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           71                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          354                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          354                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           71                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3124                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         3195                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           71                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3124                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         3195                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          777                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          131                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          908                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9247                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total         9247                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       232905                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       232905                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27955                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27955                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19533                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19533                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40687                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        40687                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        63639                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        63639                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100698                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100698                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          777                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          131                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        63639                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       141385                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       205932                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          777                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          131                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        63639                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       141385                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       232905                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       438837                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        21427                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16756                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29426                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        32852                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26162                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26162                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        38183                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     23501500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13851204796                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13851204796                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    554776500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    554776500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298118500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298118500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       351500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       351500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1669946000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1669946000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2472260000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2472260000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2283319997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2283319997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2472260000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3953265997                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   6449027497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     21573500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1928000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2472260000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3953265997                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13851204796                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  20300232293                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        55588                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        59014                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     21633000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2403000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     24036000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13888716397                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13888716397                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    558509999                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    558509999                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298853000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298853000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       529497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       529497                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1645934000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1645934000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2476915500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2476915500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2292009994                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2292009994                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     21633000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2403000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2476915500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3937943994                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   6438895494                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     21633000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2403000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2476915500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3937943994                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13888716397                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  20327611891                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3607256500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   3894127000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2599622000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2599622000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5461072000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5747942500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4118636500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4118636500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6206878500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6493749000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010380                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9579708500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9866579000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009888                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.029618                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010939                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.496815                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.496815                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.919896                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.919896                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.497756                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.497756                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.917128                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.917128                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.161497                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.161497                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034003                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210450                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.210450                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.193343                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076664                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009628                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.024205                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034003                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.193343                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159078                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159078                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.033727                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033727                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210889                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.210889                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009888                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.029618                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.033727                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076182                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009888                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.029618                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.033727                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163323                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       351500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       351500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162343                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26471.365639                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59632.538576                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19978.894616                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19978.894616                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15299.902729                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15299.902729                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 105899.400000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 105899.400000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40453.560105                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40453.560105                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38921.345401                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38921.345401                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22761.226578                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22761.226578                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38921.345401                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27852.629303                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31267.095420                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38921.345401                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27852.629303                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46321.554224                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185586.624074                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174964.766224                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157428.197386                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157428.197386                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172334.109880                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167190.480225                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        136175                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2526619                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        31161                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16756                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       865136                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2178805                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       280675                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        92865                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43660                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114593                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       285252                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       271172                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1880268                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       604912                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq        134550                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2542059                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        26162                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       862676                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2186135                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       279695                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        92964                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43745                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114531                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       284097                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       270085                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1886884                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       603437                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5613549                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2467613                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11765                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       169746                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          8262673                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120556352                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82765674                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17352                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       318664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         203658042                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1202366                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      6476462                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.183069                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.386723                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5633887                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2503276                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11828                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       167039                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          8316030                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120979776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82538715                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       314324                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         203850507                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1178802                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      6482684                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.179159                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.383485                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           5290820     81.69%     81.69% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2           1185642     18.31%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           5321256     82.08%     82.08% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2           1161428     17.92%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       6476462                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    3195593995                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       6482684                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    3211889987                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    113765999                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113481999                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2825774529                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   2835744437                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1168364927                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1181675942                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7430992                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7408493                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     90084491                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     88460994                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               20439224                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          7037667                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           906738                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            10483361                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                7695105                       # Number of BTB hits
+system.cpu1.branchPred.lookups                5445699                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3358034                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           328537                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             3334781                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                2260975                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.403034                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                8822837                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            629691                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            67.799805                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 969415                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             68088                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1290,58 +1290,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    30282                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               30282                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        22625                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7657                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        30282                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          30282    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        30282                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2657                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9441.717442                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7245.373074                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         2512     94.54%     94.54% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          130      4.89%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151            7      0.26%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-98303            5      0.19%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-114687            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2657                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1594102264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1594102264    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1594102264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1972     74.22%     74.22% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          685     25.78%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2657                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30282                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                    29420                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               29420                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        21788                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7632                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        29420                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          29420    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        29420                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2708                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10739.844904                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9761.358244                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6619.660152                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         2565     94.72%     94.72% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          128      4.73%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.30%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            1      0.04%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-98303            4      0.15%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-114687            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2708                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1720699264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1720699264    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1720699264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         2021     74.63%     74.63% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          687     25.37%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2708                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        29420                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30282                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2657                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        29420                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2708                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2657                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        32939                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2708                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        32128                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12124185                       # DTB read hits
-system.cpu1.dtb.read_misses                     27903                       # DTB read misses
-system.cpu1.dtb.write_hits                    7716793                       # DTB write hits
-system.cpu1.dtb.write_misses                     2379                       # DTB write misses
+system.cpu1.dtb.read_hits                     5163963                       # DTB read hits
+system.cpu1.dtb.read_misses                     27269                       # DTB read misses
+system.cpu1.dtb.write_hits                    4235498                       # DTB write hits
+system.cpu1.dtb.write_misses                     2151                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2053                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      374                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   549                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2054                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      296                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   518                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      291                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12152088                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7719172                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      294                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 5191232                       # DTB read accesses
+system.cpu1.dtb.write_accesses                4237649                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         19840978                       # DTB hits
-system.cpu1.dtb.misses                          30282                       # DTB misses
-system.cpu1.dtb.accesses                     19871260                       # DTB accesses
+system.cpu1.dtb.hits                          9399461                       # DTB hits
+system.cpu1.dtb.misses                          29420                       # DTB misses
+system.cpu1.dtb.accesses                      9428881                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1371,41 +1372,39 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     2290                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                2290                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          182                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2108                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         2290                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           2290    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         2290                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks                     2244                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2244                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2063                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2244                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2244    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2244                       # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkCompletionTime::samples         1123                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  9754.511529                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5025.096618                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          329     29.30%     29.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          526     46.84%     76.14% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          229     20.39%     96.53% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.18%     96.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           14      1.25%     97.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           21      1.87%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10959.928762                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10069.580655                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5627.290327                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          289     25.73%     25.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383          792     70.53%     96.26% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575            4      0.36%     96.62% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           34      3.03%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            3      0.27%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::total         1123                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1593536764                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1593536764    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1593536764                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::samples   1720133764                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1720133764    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1720133764                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walkPageSizes::4K          954     84.95%     84.95% # Table walker page sizes translated
 system.cpu1.itb.walker.walkPageSizes::1M          169     15.05%    100.00% # Table walker page sizes translated
 system.cpu1.itb.walker.walkPageSizes::total         1123                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2290                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2290                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2244                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2244                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1123                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1123                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         3413                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    41919801                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2290                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin::total         3367                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    10150571                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2244                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1418,126 +1417,126 @@ system.cpu1.itb.flush_entries                    1161                       # Nu
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1868                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1947                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                41922091                       # ITB inst accesses
-system.cpu1.itb.hits                         41919801                       # DTB hits
-system.cpu1.itb.misses                           2290                       # DTB misses
-system.cpu1.itb.accesses                     41922091                       # DTB accesses
-system.cpu1.numCycles                       125017818                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                10152815                       # ITB inst accesses
+system.cpu1.itb.hits                         10150571                       # DTB hits
+system.cpu1.itb.misses                           2244                       # DTB misses
+system.cpu1.itb.accesses                     10152815                       # DTB accesses
+system.cpu1.numCycles                        54273174                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   51886096                       # Number of instructions committed
-system.cpu1.committedOps                     63386159                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      5353179                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2738                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5566469050                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.409467                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.415030                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   20894475                       # Number of instructions committed
+system.cpu1.committedOps                     25513831                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1850967                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2736                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5637336830                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.597489                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.384987                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2740                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      105304281                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       19713537                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           231375                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          483.037999                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           19321104                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           231701                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            83.388091                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      90467560500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   483.037999                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.943434                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.943434                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          326                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          253                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           73                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.636719                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         39693132                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        39693132                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     11664966                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       11664966                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      7379255                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       7379255                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        66113                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        66113                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88582                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        88582                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80498                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        80498                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     19044221                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        19044221                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     19110334                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       19110334                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       184342                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       184342                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       167268                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       167268                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34982                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        34982                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17676                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17676                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23450                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23450                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       351610                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        351610                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       386592                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       386592                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2719374500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2719374500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4153510500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   4153510500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325753000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    325753000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    548137000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    548137000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       684500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       684500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6872885000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6872885000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6872885000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6872885000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11849308                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11849308                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7546523                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7546523                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101095                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       101095                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       106258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       103948                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       103948                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     19395831                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     19395831                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     19496926                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     19496926                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.015557                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.015557                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.022165                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.022165                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.346031                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.346031                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.166350                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.166350                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225594                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225594                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.018128                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.018128                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.019828                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.019828                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2738                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       38589177                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       15683997                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           232297                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          482.192292                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            8906174                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           232671                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            38.277972                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      90623150500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   482.192292                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.941782                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.941782                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          374                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          316                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           58                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.730469                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         18859700                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        18859700                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      4719301                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        4719301                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3908024                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3908024                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65371                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        65371                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88156                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        88156                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80067                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        80067                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      8627325                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         8627325                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      8692696                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        8692696                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       183894                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       183894                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       168264                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       168264                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35705                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        35705                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17716                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17716                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23526                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23526                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       352158                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        352158                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       387863                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       387863                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2718275000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2718275000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4151672000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4151672000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    326404500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    326404500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    549519500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    549519500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       392000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       392000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6869947000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6869947000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6869947000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6869947000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      4903195                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      4903195                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4076288                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4076288                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101076                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       101076                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105872                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       105872                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       103593                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       103593                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      8979483                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      8979483                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      9080559                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      9080559                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037505                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.037505                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.041279                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.041279                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.353249                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.353249                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.167334                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.167334                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.227100                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.227100                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.039218                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.039218                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.042714                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.042714                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14781.749269                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14781.749269                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24673.560595                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24673.560595                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18424.277489                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18424.277489                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23357.965655                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23357.965655                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19508.138392                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19508.138392                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17712.303055                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17712.303055                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1546,148 +1545,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       138377                       # number of writebacks
-system.cpu1.dcache.writebacks::total           138377                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18221                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        18221                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62038                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        62038                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12225                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12225                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        80259                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        80259                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        80259                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        80259                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166121                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       166121                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105230                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       105230                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33463                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        33463                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5451                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5451                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23450                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23450                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       271351                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       271351                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       304814                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       304814                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17128                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17128                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14405                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31533                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31533                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2295109000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2295109000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2517034000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2517034000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    544638000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    544638000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     92810500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     92810500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524700000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524700000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       671500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       671500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4812143000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4812143000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5356781000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5356781000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2934873000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2934873000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2446602500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2446602500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5381475500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5381475500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014019                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014019                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013944                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013944                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.331005                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.331005                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051300                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051300                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225594                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225594                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013990                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.013990                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015634                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.015634                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       139329                       # number of writebacks
+system.cpu1.dcache.writebacks::total           139329                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18066                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        18066                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62670                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        62670                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12262                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12262                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        80736                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        80736                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        80736                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        80736                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       165828                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       165828                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105594                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       105594                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        34258                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        34258                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5454                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5454                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23526                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23526                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       271422                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       271422                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       305680                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       305680                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5722                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5722                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5009                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5009                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10731                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10731                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2294657000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2294657000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2511298500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2511298500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    559951000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    559951000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93173500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93173500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    526001500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    526001500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       384000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       384000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4805955500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4805955500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5365906500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5365906500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    990469500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    990469500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    857774500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    857774500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1848244000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1848244000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033820                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033820                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025904                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025904                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.338933                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.338933                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051515                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051515                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.227100                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.227100                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030227                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.030227                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033663                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033663                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13837.572666                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13837.572666                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23782.587079                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23782.587079                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16345.116469                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16345.116469                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17083.516685                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17083.516685                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22358.305704                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22358.305704                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17706.580528                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17706.580528                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17553.999280                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17553.999280                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173098.479553                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173098.479553                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171246.656019                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171246.656019                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172234.088156                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 172234.088156                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          1042125                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.329120                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           40875126                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          1042637                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.203602                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      72106351500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.329120                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975252                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975252                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          1036067                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.306675                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            9111880                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          1036579                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             8.790338                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      72226761500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.306675                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975208                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975208                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          457                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           55                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         84878163                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        84878163                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     40875126                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       40875126                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     40875126                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        40875126                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     40875126                       # number of overall hits
-system.cpu1.icache.overall_hits::total       40875126                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      1042637                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      1042637                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      1042637                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       1042637                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      1042637                       # number of overall misses
-system.cpu1.icache.overall_misses::total      1042637                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9237616500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   9237616500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   9237616500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   9237616500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   9237616500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   9237616500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     41917763                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     41917763                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     41917763                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     41917763                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     41917763                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     41917763                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024873                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024873                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024873                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024873                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024873                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024873                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8859.858704                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8859.858704                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8859.858704                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8859.858704                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8859.858704                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8859.858704                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         21333497                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        21333497                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      9111880                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        9111880                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      9111880                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         9111880                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      9111880                       # number of overall hits
+system.cpu1.icache.overall_hits::total        9111880                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      1036579                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      1036579                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      1036579                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       1036579                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      1036579                       # number of overall misses
+system.cpu1.icache.overall_misses::total      1036579                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9180202500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   9180202500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   9180202500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   9180202500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   9180202500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   9180202500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     10148459                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     10148459                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     10148459                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     10148459                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     10148459                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     10148459                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.102142                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.102142                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.102142                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.102142                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.102142                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.102142                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8856.249741                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8856.249741                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8856.249741                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8856.249741                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8856.249741                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8856.249741                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1696,453 +1695,453 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1042637                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      1042637                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      1042637                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      1042637                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      1042637                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      1042637                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1036579                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      1036579                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      1036579                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      1036579                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      1036579                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      1036579                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          113                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          113                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8716298000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   8716298000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8716298000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   8716298000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8716298000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   8716298000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10126000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10126000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10126000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10126000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024873                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024873                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024873                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024873                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8359.858704                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8359.858704                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8359.858704                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8359.858704                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8661913000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8661913000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8661913000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8661913000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8661913000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8661913000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10059500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10059500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10059500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10059500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.102142                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.102142                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.102142                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.102142                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.102142                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.102142                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8356.249741                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8356.249741                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8356.249741                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8356.249741                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8356.249741                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8356.249741                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89022.123894                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89022.123894                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       270674                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       270706                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       272165                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       272190                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           22                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        70190                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           69559                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15624.003278                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           2421583                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           84278                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           28.733276                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        68922                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           69326                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15661.573061                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           2410564                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           84006                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           28.695141                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6091.947681                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    59.671167                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.103493                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5612.930096                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2321.677903                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1537.672938                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.371823                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003642                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks  6188.157881                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    52.165341                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.100614                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5579.436781                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2277.975966                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1563.736478                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.377695                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003184                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.342586                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.141704                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.093852                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.953613                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1225                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.340542                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.139037                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.095443                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.955907                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1195                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13444                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          697                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          522                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          327                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5775                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7342                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074768                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13435                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          666                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          525                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           21                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          301                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5728                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7406                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.072937                       # Percentage of cache occupancy per task id
 system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003052                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.820557                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        42869923                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       42869923                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        33040                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2583                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         35623                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       138377                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       138377                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2042                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         2042                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1012                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total         1012                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37732                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        37732                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1015029                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      1015029                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131048                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       131048                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        33040                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2583                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      1015029                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       168780                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        1219432                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        33040                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2583                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      1015029                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       168780                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       1219432                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          727                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          221                       # number of ReadReq misses
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.820007                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        42699170                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       42699170                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        32497                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2653                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         35150                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       139329                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       139329                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2011                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         2011                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1071                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total         1071                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38166                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        38166                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1009291                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      1009291                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131481                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total       131481                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        32497                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2653                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      1009291                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       169647                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        1214088                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        32497                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2653                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      1009291                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       169647                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       1214088                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          719                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          229                       # number of ReadReq misses
 system.cpu1.l2cache.ReadReq_misses::total          948                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29373                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29373                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22436                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22436                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36088                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        36088                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27608                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        27608                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73984                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        73984                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          727                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          221                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        27608                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       110072                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       138628                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          727                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          221                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        27608                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       110072                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       138628                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     18603000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4457500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     23060500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    554124000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    554124000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449909000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449909000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       652000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       652000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1418232500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1418232500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1071283000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1071283000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1763586495                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1763586495                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     18603000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4457500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1071283000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3181818995                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4276162495                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     18603000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4457500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1071283000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3181818995                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4276162495                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33767                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2804                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        36571                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       138377                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       138377                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31415                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31415                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23448                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23448                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73820                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        73820                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1042637                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      1042637                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205032                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       205032                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33767                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2804                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      1042637                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       278852                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1358060                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33767                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2804                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      1042637                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       278852                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1358060                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.025922                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.934999                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.934999                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.956841                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.956841                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29485                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29485                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22454                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22454                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        35935                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        35935                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27288                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        27288                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        74058                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        74058                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          719                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          229                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        27288                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       109993                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       138229                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          719                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          229                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        27288                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       109993                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       138229                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     17830000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4703000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     22533000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    557854000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    557854000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449261000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449261000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       372000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       372000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1407590499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1407590499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1060250500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1060250500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1775396994                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1775396994                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     17830000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4703000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1060250500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3182987493                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4265770993                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     17830000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4703000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1060250500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3182987493                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4265770993                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33216                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2882                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        36098                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       139329                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       139329                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31496                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        31496                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23525                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23525                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74101                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        74101                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1036579                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      1036579                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205539                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       205539                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33216                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2882                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      1036579                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       279640                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      1352317                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33216                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2882                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      1036579                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       279640                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1352317                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021646                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.079459                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.026262                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.936151                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.936151                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.954474                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.954474                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.488865                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.488865                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026479                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026479                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.360841                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.360841                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026479                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.394733                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.102078                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021530                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.078816                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026479                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.394733                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.102078                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24325.421941                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18865.080176                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18865.080176                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20052.995186                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20052.995186                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       326000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       326000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39299.282310                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39299.282310                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38803.354100                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38803.354100                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23837.403966                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23837.403966                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38803.354100                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28906.706474                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 30846.311676                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25588.720770                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.683258                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38803.354100                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28906.706474                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 30846.311676                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.484946                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.484946                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026325                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026325                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.360311                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.360311                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021646                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.079459                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026325                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.393338                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.102216                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021646                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.079459                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026325                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.393338                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.102216                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 24798.331015                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20537.117904                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23768.987342                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18919.925386                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18919.925386                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20008.060925                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20008.060925                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       372000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       372000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39170.460526                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39170.460526                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38854.093374                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38854.093374                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23973.061573                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23973.061573                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 24798.331015                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20537.117904                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38854.093374                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28938.091451                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 30860.174008                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 24798.331015                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20537.117904                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38854.093374                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28938.091451                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 30860.174008                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           56                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        36799                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           36799                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          302                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          302                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           26                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          134                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          134                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           26                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          436                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          462                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           26                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          436                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          462                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          727                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          221                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        37014                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           37014                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          288                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          288                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           20                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          127                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          127                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           20                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          415                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          435                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           20                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          415                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          435                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          719                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          229                       # number of ReadReq MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_misses::total          948                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3205                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total         3205                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35196                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        35196                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29373                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29373                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22436                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22436                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35786                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        35786                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        27582                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        27582                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73850                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73850                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          727                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          221                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27582                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109636                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       138166                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          727                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          221                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27582                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109636                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35196                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       173362                       # number of overall MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3215                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total         3215                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35422                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        35422                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29485                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29485                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22454                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22454                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35647                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        35647                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        27268                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        27268                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73931                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73931                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          719                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          229                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27268                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109578                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       137794                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          719                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          229                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27268                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109578                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35422                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       173216                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17128                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17241                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14405                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5722                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5835                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         5009                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         5009                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31533                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31646                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     17372500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1238467331                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1238467331                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    502709499                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    502709499                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348029000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348029000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       574000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       574000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1167759000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1167759000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    904893000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    904893000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1316095995                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1316095995                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    904893000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2483854995                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3406120495                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     14241000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3131500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    904893000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2483854995                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1238467331                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4644587826                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9222000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2797805500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2807027500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2338455000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2338455000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9222000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5136260500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5145482500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025922                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10731                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10844                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     13516000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3329000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     16845000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1189902692                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1189902692                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    503727499                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    503727499                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348590500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348590500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       324000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       324000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1162178500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1162178500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    895970500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    895970500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1327142494                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1327142494                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3329000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    895970500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2489320994                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3402136494                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13516000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3329000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    895970500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2489320994                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1189902692                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4592039186                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9155500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    944653500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    953809000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    820084500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    820084500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9155500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1764738000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1773893500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021646                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.079459                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026262                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.934999                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.934999                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.956841                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.956841                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.936151                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.936151                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.954474                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.954474                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.484774                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.484774                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026454                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.360188                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.360188                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.393169                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101738                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021530                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.078816                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026454                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.393169                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.481060                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.481060                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026306                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026306                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.359693                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.359693                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021646                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.079459                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026306                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.391854                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101895                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021646                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.079459                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026306                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.391854                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.127654                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       287000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       287000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.128088                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17768.987342                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33592.193891                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17084.195320                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17084.195320                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15524.650396                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15524.650396                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       324000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       324000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32602.420961                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32602.420961                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32857.947044                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32857.947044                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17951.096211                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17951.096211                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32857.947044                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22717.342843                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24690.019115                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32857.947044                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22717.342843                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26510.479321                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165091.488990                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163463.410454                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163722.200040                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163722.200040                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164452.334358                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163582.949096                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq         81005                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1348099                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        31161                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        14405                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       510462                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      1265020                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        43516                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        77320                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42972                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89288                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        97251                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        79776                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1042637                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       559861                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq         80046                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1329975                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         5009                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       511761                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1258534                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        43565                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        76909                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43045                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        89356                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        97332                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        80052                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1036579                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       560078                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3108261                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1040223                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7202                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        71706                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          4227392                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66736000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29812791                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       135068                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          96695075                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    1172897                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      3809713                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.296141                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.456554                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3090316                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1000986                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7189                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70268                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          4168759                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66348288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29828599                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       132864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          96321279                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    1191896                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      3797471                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.302048                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.459146                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2681500     70.39%     70.39% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2           1128213     29.61%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2650451     69.80%     69.80% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2           1147020     30.20%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       3809713                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1507501992                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       3797471                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1487742991                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     87443999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     87115499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1564193862                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1555110854                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    470956198                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    456039835                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4398499                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4307000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     37948980                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     37064974                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31013                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31013                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                30994                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30994                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
@@ -2150,7 +2149,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          844                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2166,16 +2165,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107910                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180870                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72920                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72920                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180832                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          446                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2191,10 +2190,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162793                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484073                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2483914                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
@@ -2205,7 +2204,7 @@ system.iobus.reqLayer3.occupancy                12000                       # La
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               503000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               504000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2235,52 +2234,52 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           187545199                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187482956                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84712000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36744000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36462                       # number of replacements
-system.iocache.tags.tagsinuse               14.479963                       # Cycle average of tags in use
+system.iocache.tags.replacements                36426                       # number of replacements
+system.iocache.tags.tagsinuse                1.010803                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36478                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36442                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270370198000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.479963                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.904998                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.904998                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270452648000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.010803                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.063175                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.063175                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328320                       # Number of tag accesses
-system.iocache.tags.data_accesses              328320                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          256                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              256                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328140                       # Number of tag accesses
+system.iocache.tags.data_accesses              328140                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          236                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              236                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          256                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               256                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          256                       # number of overall misses
-system.iocache.overall_misses::total              256                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32688877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32688877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4277206322                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4277206322                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32688877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32688877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32688877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32688877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          236                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               236                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          236                       # number of overall misses
+system.iocache.overall_misses::total              236                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     30330877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30330877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4273955079                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4273955079                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     30330877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     30330877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     30330877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     30330877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          236                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            236                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          256                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             256                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          256                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            256                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          236                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             236                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          236                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            236                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2289,40 +2288,40 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 127690.925781                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 127690.925781                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 127690.925781                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 127690.925781                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 127690.925781                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            21                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 128520.665254                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 128520.665254                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117986.834116                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117986.834116                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 128520.665254                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 128520.665254                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 128520.665254                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 128520.665254                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            17                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.500000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36206                       # number of writebacks
-system.iocache.writebacks::total                36206                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          236                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          236                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          256                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          256                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          256                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19888877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19888877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2466006322                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2466006322                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19888877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19888877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19888877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19888877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide          236                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          236                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          236                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          236                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18530877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18530877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2462755079                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2462755079                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18530877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18530877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18530877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18530877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2331,576 +2330,603 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 77690.925781                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 77690.925781                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78520.665254                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 78520.665254                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67986.834116                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67986.834116                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 78520.665254                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 78520.665254                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 78520.665254                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 78520.665254                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   134724                       # number of replacements
-system.l2c.tags.tagsinuse                64068.233504                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     443602                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   199053                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.228562                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   135428                       # number of replacements
+system.l2c.tags.tagsinuse                64138.208301                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     442739                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   199807                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.215833                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12835.902941                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    68.531822                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.025215                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7257.127456                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2101.817094                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    30.126345                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4045.876721                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1535.093827                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4184.707478                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.195860                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001046                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   12941.285088                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    69.276334                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.031468                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7274.373268                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2166.846690                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 31945.045858                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    24.318023                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.851962                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4022.114049                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1496.265741                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4197.799819                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.197468                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001057                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.110735                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.032071                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.488419                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000460                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061735                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.023424                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.063854                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.977604                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        29296                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        34966                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          113                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5383                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        23800                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.110998                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.033063                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.487443                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000371                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000013                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061373                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.022831                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.064053                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.978671                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        29250                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        35037                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          144                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         5264                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        23842                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           66                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          313                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2923                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        31711                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.447021                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001022                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.533539                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5827626                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5827626                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          232709                       # number of Writeback hits
-system.l2c.Writeback_hits::total               232709                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            3025                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             939                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3964                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           257                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            83                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               340                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4055                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             2183                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 6238                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          387                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           52                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        44381                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        47292                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46189                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          171                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           33                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        21681                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        11241                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8230                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           179657                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           387                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            52                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               44381                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               51347                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        46189                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker           171                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            33                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               21681                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               13424                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         8230                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  185895                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          387                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           52                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              44381                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              51347                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        46189                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker          171                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           33                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              21681                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              13424                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         8230                       # number of overall hits
-system.l2c.overall_hits::total                 185895                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          8753                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4074                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12827                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          797                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1213                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2010                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          10969                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8454                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19423                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq misses
+system.l2c.tags.age_task_id_blocks_1023::4           91                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         3030                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        31679                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.446320                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.001404                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.534622                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5824693                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5824693                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks          232832                       # number of Writeback hits
+system.l2c.Writeback_hits::total               232832                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            3079                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             930                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                4009                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           233                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            92                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               325                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data             4022                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data             2114                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                 6136                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          393                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker           81                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst        44006                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data        47229                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46346                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          166                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker           37                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst        21446                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        11079                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8110                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           178893                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker           393                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker            81                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst               44006                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data               51251                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher        46346                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker           166                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker            37                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               21446                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               13193                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher         8110                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  185029                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker          393                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker           81                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst              44006                       # number of overall hits
+system.l2c.overall_hits::cpu0.data              51251                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher        46346                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker          166                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker           37                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              21446                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              13193                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher         8110                       # number of overall hits
+system.l2c.overall_hits::total                 185029                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          8747                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4112                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             12859                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          835                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         1227                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            2062                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          10918                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8428                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              19346                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          114                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        19546                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         8542                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       128715                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           43                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst         5890                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         2696                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         8977                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         174531                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker          121                       # number of demand (read+write) misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        19630                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         8718                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       129027                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           38                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst         5812                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         2889                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         8839                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         175069                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker          114                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             19546                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             19511                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       128715                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           43                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5890                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             11150                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         8977                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                193954                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker          121                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst             19630                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             19636                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       129027                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           38                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5812                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             11317                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher         8839                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                194415                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker          114                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            19546                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            19511                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       128715                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           43                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5890                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            11150                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         8977                       # number of overall misses
-system.l2c.overall_misses::total               193954                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      9167000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      5104000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     14271000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1330000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1451500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2781500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1087997000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    696148000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1784145000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10392000                       # number of ReadSharedReq miss cycles
+system.l2c.overall_misses::cpu0.inst            19630                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            19636                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       129027                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           38                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5812                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            11317                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher         8839                       # number of overall misses
+system.l2c.overall_misses::total               194415                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data      8346500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      5785000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     14131500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1392500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1414500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2807000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1077000000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    690485000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1767485000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10253000                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       303000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1558395000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    749223000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3962000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst    483846500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    240245000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  17184117504                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker     10392000                       # number of demand (read+write) miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1569061500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data    759147500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13107894109                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3343000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        83000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    479575000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    252543500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1024779080                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  17206982689                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker     10253000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       303000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1558395000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   1837220000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      3962000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    483846500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    936393000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     18968262504                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker     10392000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1569061500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   1836147500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13107894109                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      3343000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker        83000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    479575000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    943028500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1024779080                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     18974467689                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker     10253000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       303000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1558395000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1837220000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13067901493                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      3962000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    483846500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    936393000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1069849511                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    18968262504                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks       232709                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           232709                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        11778                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5013                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           16791                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1054                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         1296                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2350                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15024                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        10637                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25661                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          508                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           53                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst        63927                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data        55834                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       174904                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          214                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           33                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst        27571                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        13937                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        17207                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       354188                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          508                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           53                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           63927                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           70858                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       174904                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker          214                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           33                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           27571                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           24574                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        17207                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              379849                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          508                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           53                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          63927                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          70858                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       174904                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker          214                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           33                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          27571                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          24574                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        17207                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             379849                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.743165                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.812687                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.763921                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.756167                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.935957                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.855319                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.730099                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.794773                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.756907                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.305755                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.152989                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.213630                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.193442                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.492764                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.305755                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.275354                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.213630                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.453732                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.510608                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.238189                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.018868                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.305755                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.275354                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.200935                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.213630                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.453732                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.510608                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1047.298069                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1252.822779                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1112.575037                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1668.757842                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1196.619951                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1383.830846                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99188.348983                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82345.398628                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 91857.334088                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   1569061500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   1836147500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13107894109                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      3343000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker        83000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    479575000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    943028500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1024779080                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    18974467689                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks       232832                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           232832                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        11826                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5042                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           16868                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         1068                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         1319                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2387                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        14940                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        10542                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25482                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          507                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           82                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        63636                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        55947                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       175373                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          204                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           38                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        27258                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        13968                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        16949                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       353962                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          507                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           82                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           63636                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           70887                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       175373                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker          204                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           38                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           27258                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           24510                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        16949                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              379444                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          507                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           82                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          63636                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          70887                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       175373                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker          204                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           38                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          27258                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          24510                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        16949                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             379444                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.739641                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.815549                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.762331                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.781835                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.930250                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.863846                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.730790                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.799469                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.759203                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.224852                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.012195                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.308473                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.155826                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.186275                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.026316                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.213222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.206830                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.494598                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.224852                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012195                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.308473                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.277004                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.186275                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.026316                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.213222                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.461730                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.512368                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.224852                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012195                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.308473                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.277004                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.186275                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.026316                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.213222                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.461730                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.512368                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   954.212873                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1406.857977                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1098.957928                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1667.664671                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1152.811736                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  1361.299709                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 98644.440374                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81927.503560                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 91361.780213                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89938.596491                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       303000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79729.612197                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87710.489347                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82147.113752                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89111.646884                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 98458.826822                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79931.813551                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87078.171599                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87973.684211                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        83000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82514.624914                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 87415.541710                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 98286.862260                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89938.596491                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 79729.612197                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 94163.292502                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82147.113752                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83981.434978                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 97797.738144                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85884.297521                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 79931.813551                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 93509.243227                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87973.684211                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 82514.624914                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 83328.488115                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 97597.755775                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89938.596491                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 79729.612197                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 94163.292502                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92139.534884                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82147.113752                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83981.434978                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 97797.738144                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               442                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 79931.813551                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 93509.243227                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87973.684211                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82514.624914                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 83328.488115                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 97597.755775                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           221                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              103131                       # number of writebacks
-system.l2c.writebacks::total                   103131                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
+system.l2c.writebacks::writebacks              103399                       # number of writebacks
+system.l2c.writebacks::total                   103399                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                  5                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3812                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3812                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8753                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4074                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12827                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          797                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1213                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2010                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        10969                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8454                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19423                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq MSHR misses
+system.l2c.overall_mshr_hits::total                 5                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3802                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3802                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8747                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4112                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12859                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          835                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1227                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         2062                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        10918                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8428                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19346                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          114                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19541                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8542                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           43                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5886                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2696                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       174522                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker          121                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19629                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8718                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       129027                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           38                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5808                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2889                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         8839                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       175064                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker          114                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        19541                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        19511                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           43                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5886                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        11150                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           193945                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker          121                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        19629                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        19636                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       129027                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           38                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5808                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        11317                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         8839                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           194410                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker          114                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        19541                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        19511                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       128715                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           43                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5886                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        11150                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         8977                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          193945                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        19629                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        19636                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       129027                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           38                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5808                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        11317                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         8839                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          194410                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        18001                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29426                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17124                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        38664                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16756                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14405                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        31161                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5718                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        38683                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26162                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5009                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        31171                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34757                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        55588                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31529                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        69825                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    181795500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     84589501                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    266385001                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     16646000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25174500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     41820500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    978307000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    611608000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1589915000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10727                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        69854                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    181705001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     86116001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    267821002                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     17444000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25472500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     42916500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    967820000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    606205000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1574025000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      9113000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       293000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1362728000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    663803000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    424750500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    213285000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  15438404504                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1372734500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    671967500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11817624109                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      2963000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        73000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    421007000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    223653500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    936389080                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  15455817689                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9113000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       293000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1362728000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1642110000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    424750500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    824893000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  17028319504                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9182000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1372734500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   1639787500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11817624109                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      2963000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    421007000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    829858500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    936389080                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  17029842689                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9113000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       293000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1362728000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1642110000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11780751493                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      3532000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    424750500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    824893000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    980079511                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  17028319504                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1372734500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   1639787500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11817624109                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2963000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    421007000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    829858500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    936389080                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  17029842689                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3283233500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6848500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2489515500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5994522000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2314676500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2093562500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4408239000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4931392500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6782000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    841666000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5994765000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3673788500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    734928500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4408717000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5597910000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6848500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4583078000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10402761000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8605181000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6782000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1576594500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10403482000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.743165                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.812687                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.763921                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.756167                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935957                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.855319                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.730099                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.794773                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.756907                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.152989                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.193442                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.492738                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.275354                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.453732                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.510584                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.238189                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.018868                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.305677                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.275354                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735918                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.200935                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.213485                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.453732                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521706                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.510584                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.739641                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.815549                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.762331                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.781835                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.930250                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.863846                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.730790                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.799469                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.759203                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.224852                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.012195                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.308457                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.155826                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.186275                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.026316                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.213075                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.206830                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.494584                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.224852                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012195                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.308457                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.277004                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.186275                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.026316                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.213075                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.461730                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.512355                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.224852                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012195                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.308457                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.277004                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.186275                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.026316                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.213075                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.461730                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.512355                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.408140                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20942.607247                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20827.513959                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20891.017964                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.983700                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20813.045587                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 88644.440374                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71927.503560                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 81361.780213                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69934.000713                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77078.171599                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        73000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72487.431129                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 77415.541710                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88286.670526                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 87799.734481                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69934.000713                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83509.243227                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72487.431129                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73328.488115                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 87597.565398                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 87799.734481                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69934.000713                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83509.243227                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72487.431129                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73328.488115                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 87597.565398                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167586.233263                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147195.872683                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154971.563736                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140424.604388                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146721.601118                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141436.495461                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154802.853134                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146974.410366                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 148931.800613                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               38664                       # Transaction distribution
-system.membus.trans_dist::ReadResp             213442                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31161                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31161                       # Transaction distribution
-system.membus.trans_dist::Writeback            139337                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            18210                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            78893                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41609                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14967                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39746                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19293                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        174778                       # Transaction distribution
+system.membus.trans_dist::ReadReq               38683                       # Transaction distribution
+system.membus.trans_dist::ReadResp             213983                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31171                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31171                       # Transaction distribution
+system.membus.trans_dist::Writeback            139589                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            18226                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            78324                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          41642                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15039                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39751                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19228                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        175300                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107910                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       681524                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       804190                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108938                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108938                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 913128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162793                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14776                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       682330                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       805060                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108902                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108902                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 913962                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29428                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19228072                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19421637                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21739781                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           126569                       # Total snoops (count)
-system.membus.snoop_fanout::samples            598906                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19274524                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19468214                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21785334                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           126049                       # Total snoops (count)
+system.membus.snoop_fanout::samples            599148                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  598906    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  599148    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              598906                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            91147500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              599148                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            91414000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               24328                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12904500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12977999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1003618732                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1005422091                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1163956699                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1166590180                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64493538                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64371509                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2933,56 +2959,56 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq              38668                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            519865                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31161                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31161                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           372085                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           99404                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           82727                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41949                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         124676                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           24                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           24                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51768                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51768                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       481212                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              38687                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            518927                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31171                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31171                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           372432                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           99547                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           82215                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41967                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         124182                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           26                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51561                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51561                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       480255                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1091980                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       404567                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1496547                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32727326                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6930535                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               39657861                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          466410                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1287380                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.161360                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.367862                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1133004                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       361504                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1494508                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32818575                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6820071                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               39638646                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          465665                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1285667                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.162057                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.368503                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1079649     83.86%     83.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 207731     16.14%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                1077316     83.79%     83.79% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 208351     16.21%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1287380                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          861414818                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            1285667                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          860205550                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           361500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           331500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         631551677                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         646726661                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         286263459                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         269148617                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
index 46b536a54..37b26c84c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -179,7 +179,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -638,7 +638,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -748,7 +748,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -836,7 +836,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1251,9 +1251,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
index 174785dd4..f4a19412e 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:47:25
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:06:44
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2852648357500 because m5_exit instruction encountered
+Exiting @ tick 2852654988500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index b263a31ec..954a8904e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.852648                       # Number of seconds simulated
-sim_ticks                                2852648357500                       # Number of ticks simulated
-final_tick                               2852648357500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.852655                       # Number of seconds simulated
+sim_ticks                                2852654988500                       # Number of ticks simulated
+final_tick                               2852654988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 154527                       # Simulator instruction rate (inst/s)
-host_op_rate                                   186842                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3929586318                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 575824                       # Number of bytes of host memory used
-host_seconds                                   725.94                       # Real time elapsed on the host
-sim_insts                                   112177181                       # Number of instructions simulated
-sim_ops                                     135636113                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 116178                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140471                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2957977243                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 618900                       # Number of bytes of host memory used
+host_seconds                                   964.39                       # Real time elapsed on the host
+sim_insts                                   112040950                       # Number of instructions simulated
+sim_ops                                     135468925                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         8192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1670464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9187820                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         8064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1669952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9187372                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10867564                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1670464                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1670464                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7983168                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10866412                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1669952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1669952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7981376                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8000692                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          128                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26101                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             144081                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7998900                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          126                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26093                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144074                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170327                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124737                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170309                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124709                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129118                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2872                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               585584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3220804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129090                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2827                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               585403                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3220639                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3809640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          585584                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             585584                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2798511                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3809228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          585403                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             585403                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2797876                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6143                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2804654                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2798511                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2872                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              585584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3226947                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2804019                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2797876                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2827                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              585403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3226782                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6614294                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170327                       # Number of read requests accepted
-system.physmem.writeReqs                       129118                       # Number of write requests accepted
-system.physmem.readBursts                      170327                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129118                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10891072                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8012864                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10867564                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8000692                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6613247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170309                       # Number of read requests accepted
+system.physmem.writeReqs                       129090                       # Number of write requests accepted
+system.physmem.readBursts                      170309                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129090                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10890880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8010944                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10866412                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7998900                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          40818                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10912                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10835                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10722                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10734                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13360                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10814                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11148                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10988                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10136                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10280                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10233                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9195                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10314                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10738                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10036                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9728                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8115                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8199                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8378                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8308                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7548                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7862                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8189                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8102                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7754                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7814                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7662                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7060                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7768                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7969                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7379                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7094                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          40828                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10905                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10842                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10713                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10735                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13349                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10818                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11158                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10982                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10119                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10274                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10247                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9187                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10322                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10753                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10041                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9725                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8109                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8208                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8370                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8304                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7540                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7865                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8185                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8104                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7740                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7807                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7671                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7052                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7765                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7977                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7383                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7091                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2852647955000                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2852654585000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169770                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169752                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124737                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    163101                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      6778                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       282                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124709                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      6752                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       288                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,116 +159,116 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       19                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        60792                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      310.959863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.660922                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.542835                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22288     36.66%     36.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14645     24.09%     60.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6538     10.75%     71.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3485      5.73%     77.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2623      4.31%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1593      2.62%     84.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1118      1.84%     86.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1065      1.75%     87.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7437     12.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          60792                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6289                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.056766                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      539.634570                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6287     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8521                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60691                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.442553                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     184.035683                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.553660                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22186     36.56%     36.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14675     24.18%     60.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6464     10.65%     71.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3592      5.92%     77.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2485      4.09%     81.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1671      2.75%     84.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1111      1.83%     85.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1120      1.85%     87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7387     12.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60691                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6290                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.051669                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      539.627643                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6288     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6289                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6289                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.907934                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.344478                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.522535                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5503     87.50%     87.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              53      0.84%     88.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             178      2.83%     91.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              46      0.73%     91.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              61      0.97%     92.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             176      2.80%     95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              19      0.30%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.10%     96.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              12      0.19%     96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              10      0.16%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.13%     96.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.08%     96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             165      2.62%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.03%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               5      0.08%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.06%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.27%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.05%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6289                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1698489250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4889233000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850865000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9980.96                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6290                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6290                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.900000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.361154                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.375647                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5497     87.39%     87.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              61      0.97%     88.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             183      2.91%     91.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              46      0.73%     92.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              63      1.00%     93.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             171      2.72%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              19      0.30%     96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               8      0.13%     96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              10      0.16%     96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.16%     96.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.05%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.03%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             171      2.72%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.03%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               5      0.08%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.05%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.06%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            15      0.24%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6290                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1692148250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4882835750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    850850000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9943.87                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28730.96                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28693.87                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
@@ -277,41 +277,41 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.43                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     140383                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94198                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     140376                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94273                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.49                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9526450.45                       # Average gap between requests
-system.physmem.pageHitRate                      79.41                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  240748200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  131360625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 698201400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                419262480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186320618640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83613121875                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1638239679750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1909662992970                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.436876                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2725220726500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95255940000                       # Time in different power states
+system.physmem.writeRowHitRate                  75.30                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9527936.25                       # Average gap between requests
+system.physmem.pageHitRate                      79.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  240143400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  131030625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 698115600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                419158800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186321127200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83459244105                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1638379332000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1909648151730                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.429846                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2725453951250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95256200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32164219750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31938521250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  218839320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  119406375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 629140200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                392040000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186320618640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82051531065                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1639609496250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1909341071850                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.324025                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2727521283250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95255940000                       # Time in different power states
+system.physmem_1.actEnergy                  218680560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  119319750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 629202600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                391949280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186321127200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82079606700                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1639589540250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1909349426340                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.325127                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2727485699500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95256200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     29871038250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     29912992000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
@@ -331,15 +331,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31035995                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16848460                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2529330                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18616538                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13364370                       # Number of BTB hits
+system.cpu.branchPred.lookups                31017301                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16826801                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2510748                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18518050                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13329905                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.787622                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7827743                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1524480                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             71.983308                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7858653                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1517345                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -370,56 +370,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     66851                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                66851                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44044                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22807                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        66851                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           66851    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        66851                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7848                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11969.673802                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9947.704899                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  7432.490287                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383         6134     78.16%     78.16% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767         1708     21.76%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303            5      0.06%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     65935                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                65935                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43131                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22804                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        65935                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           65935    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        65935                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7817                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11967.954458                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9949.329384                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7404.205030                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383         6115     78.23%     78.23% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         1696     21.70%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7848                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7817                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples    260813000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0       260813000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total    260813000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6448     82.16%     82.16% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1400     17.84%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7848                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66851                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K          6422     82.15%     82.15% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1395     17.85%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7817                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        65935                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66851                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7848                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        65935                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7817                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7848                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        74699                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7817                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        73752                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24795366                       # DTB read hits
-system.cpu.dtb.read_misses                      59924                       # DTB read misses
-system.cpu.dtb.write_hits                    19459513                       # DTB write hits
-system.cpu.dtb.write_misses                      6927                       # DTB write misses
+system.cpu.dtb.read_hits                     24760096                       # DTB read hits
+system.cpu.dtb.read_misses                      58949                       # DTB read misses
+system.cpu.dtb.write_hits                    19444061                       # DTB write hits
+system.cpu.dtb.write_misses                      6986                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4353                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1315                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1793                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                      1337                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1780                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       738                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24855290                       # DTB read accesses
-system.cpu.dtb.write_accesses                19466440                       # DTB write accesses
+system.cpu.dtb.perms_faults                       739                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24819045                       # DTB read accesses
+system.cpu.dtb.write_accesses                19451047                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44254879                       # DTB hits
-system.cpu.dtb.misses                           66851                       # DTB misses
-system.cpu.dtb.accesses                      44321730                       # DTB accesses
+system.cpu.dtb.hits                          44204157                       # DTB hits
+system.cpu.dtb.misses                           65935                       # DTB misses
+system.cpu.dtb.accesses                      44270092                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -449,37 +450,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                      5476                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5476                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5156                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5476                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5476    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5476                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3185                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12111.930926                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10073.036735                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7077.069157                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191         1309     41.10%     41.10% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383         1163     36.51%     77.61% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575          712     22.35%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                      5452                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5452                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          318                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5134                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5452                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5452    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5452                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3184                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12119.032663                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10076.122020                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7085.501487                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1309     41.11%     41.11% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383         1160     36.43%     77.54% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          714     22.42%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3185                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3184                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples    260408500                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0       260408500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total    260408500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2875     90.27%     90.27% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           310      9.73%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3185                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K          2874     90.26%     90.26% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.74%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3184                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5476                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5476                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5452                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5452                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3185                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3185                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         8661                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57644793                       # ITB inst hits
-system.cpu.itb.inst_misses                       5476                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3184                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3184                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         8636                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57598025                       # ITB inst hits
+system.cpu.itb.inst_misses                       5452                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -488,274 +489,274 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2975                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2973                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8375                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8340                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57650269                       # ITB inst accesses
-system.cpu.itb.hits                          57644793                       # DTB hits
-system.cpu.itb.misses                            5476                       # DTB misses
-system.cpu.itb.accesses                      57650269                       # DTB accesses
-system.cpu.numCycles                        315472495                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57603477                       # ITB inst accesses
+system.cpu.itb.hits                          57598025                       # DTB hits
+system.cpu.itb.misses                            5452                       # DTB misses
+system.cpu.itb.accesses                      57603477                       # DTB accesses
+system.cpu.numCycles                        315393196                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112177181                       # Number of instructions committed
-system.cpu.committedOps                     135636113                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7815514                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   112040950                       # Number of instructions committed
+system.cpu.committedOps                     135468925                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7774524                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5389884731                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.812270                       # CPI: cycles per instruction
-system.cpu.ipc                               0.355585                       # IPC: instructions per cycle
+system.cpu.quiesceCycles                   5389977386                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.814981                       # CPI: cycles per instruction
+system.cpu.ipc                               0.355242                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
-system.cpu.tickCycles                       227521960                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        87950535                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            843739                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.948229                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42652951                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            844251                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.521647                       # Average number of references to valid blocks.
+system.cpu.tickCycles                       227419103                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        87974093                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            843754                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.948230                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42602633                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            844266                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.461150                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         310642500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.948229                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.948230                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999899                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999899                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176384491                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176384491                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23097762                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23097762                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18292469                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18292469                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       356103                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        356103                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443541                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443541                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460142                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460142                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41390231                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41390231                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41746334                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41746334                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       493938                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        493938                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       548534                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       548534                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       170153                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       170153                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22409                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22409                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176183318                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176183318                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23061882                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23061882                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18277764                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18277764                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       356325                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        356325                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443565                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443565                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460145                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460145                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41339646                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41339646                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41695971                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41695971                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       494235                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        494235                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       548281                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       548281                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       170165                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       170165                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22392                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22392                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1042472                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1042472                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1212625                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1212625                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   7285426000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   7285426000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  23290524980                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  23290524980                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    282897500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    282897500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  30575950980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  30575950980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  30575950980                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  30575950980                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23591700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23591700                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18841003                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18841003                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526256                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526256                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465950                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465950                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460144                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460144                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42432703                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42432703                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42958959                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42958959                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020937                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020937                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029114                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029114                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323327                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.323327                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048093                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048093                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      1042516                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1042516                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1212681                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1212681                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   7291153500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7291153500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  23268838480                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  23268838480                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    283155000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    283155000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  30559991980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  30559991980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  30559991980                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  30559991980                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23556117                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23556117                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18826045                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18826045                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       526490                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       526490                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465957                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465957                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460147                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460147                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42382162                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42382162                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42908652                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42908652                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020981                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.020981                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029124                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029124                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.323207                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.323207                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048056                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048056                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024568                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024568                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028228                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028228                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14749.677085                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14749.677085                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42459.583143                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42459.583143                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12624.280423                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12624.280423                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29330.237148                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29330.237148                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25214.679707                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25214.679707                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          276                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024598                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024598                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028262                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028262                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14752.402197                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14752.402197                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42439.622165                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42439.622165                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12645.364416                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12645.364416                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29313.691090                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29313.691090                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25200.355229                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25200.355229                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          269                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.545455                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.809524                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       699258                       # number of writebacks
-system.cpu.dcache.writebacks::total            699258                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        75585                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        75585                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249712                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       249712                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14175                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14175                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       325297                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       325297                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       325297                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       325297                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       418353                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       418353                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298822                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298822                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121703                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121703                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8234                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8234                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       699241                       # number of writebacks
+system.cpu.dcache.writebacks::total            699241                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        75816                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        75816                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249572                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       249572                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14161                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14161                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       325388                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       325388                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       325388                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       325388                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       418419                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       418419                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298709                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298709                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121784                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121784                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8231                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8231                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       717175                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       717175                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       838878                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       838878                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       717128                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       717128                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       838912                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       838912                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5919321500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5919321500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12456778000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12456778000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1615525000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1615525000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109204500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109204500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18376099500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18376099500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19991624500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  19991624500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5909109000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5909109000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4568792500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4568792500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10477901500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10477901500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017733                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017733                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015860                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015860                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231262                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231262                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017671                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017671                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5922558000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5922558000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12450120000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12450120000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1618736500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1618736500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109455500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109455500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18372678000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18372678000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19991414500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  19991414500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5909069000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5909069000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4568816000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4568816000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10477885000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10477885000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017763                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017763                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015867                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015867                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.231313                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.231313                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017665                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017665                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016901                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016901                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019527                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019527                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14149.107333                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14149.107333                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41686.281465                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41686.281465                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13274.323558                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13274.323558                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13262.630556                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13262.630556                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25622.894691                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25622.894691                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23831.384897                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23831.384897                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189832.594449                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189832.594449                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165637.983541                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165637.983541                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.730442                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.730442                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016921                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016921                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019551                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019551                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14154.610570                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14154.610570                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41679.761909                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41679.761909                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13291.865105                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13291.865105                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13297.958936                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13297.958936                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25619.802880                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25619.802880                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23830.168719                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23830.168719                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189831.309432                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189831.309432                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165638.835515                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165638.835515                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.449405                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.449405                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2894405                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.404377                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54741020                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2894917                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.909357                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       15461690500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.404377                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements           2895998                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.404759                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54692690                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2896510                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.882272                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       15448784500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.404759                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998837                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998837                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          196                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60530877                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60530877                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54741020                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54741020                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54741020                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54741020                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54741020                       # number of overall hits
-system.cpu.icache.overall_hits::total        54741020                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2894929                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2894929                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2894929                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2894929                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2894929                       # number of overall misses
-system.cpu.icache.overall_misses::total       2894929                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  39235778500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  39235778500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  39235778500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  39235778500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  39235778500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  39235778500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57635949                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57635949                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57635949                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57635949                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57635949                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57635949                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050228                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050228                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050228                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050228                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050228                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050228                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.278336                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13553.278336                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.278336                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13553.278336                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.278336                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13553.278336                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60485733                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60485733                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     54692690                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54692690                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54692690                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54692690                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     54692690                       # number of overall hits
+system.cpu.icache.overall_hits::total        54692690                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      2896522                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       2896522                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      2896522                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        2896522                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      2896522                       # number of overall misses
+system.cpu.icache.overall_misses::total       2896522                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  39250501500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  39250501500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  39250501500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  39250501500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  39250501500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  39250501500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57589212                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57589212                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57589212                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57589212                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57589212                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57589212                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050296                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050296                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050296                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050296                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050296                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050296                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.907433                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13550.907433                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.907433                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13550.907433                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.907433                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13550.907433                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -764,212 +765,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894929                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2894929                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2894929                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2894929                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2894929                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2894929                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2896522                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      2896522                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      2896522                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      2896522                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      2896522                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      2896522                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3191                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3191                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3191                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36340850500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  36340850500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36340850500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  36340850500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36340850500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  36340850500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36353980500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  36353980500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36353980500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  36353980500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36353980500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  36353980500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    248718500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    248718500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    248718500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    248718500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050228                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050228                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050228                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050228                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12553.278681                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12553.278681                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12553.278681                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.278681                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050296                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050296                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050296                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.050296                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050296                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.050296                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.907778                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.907778                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.907778                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.907778                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.907778                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.907778                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77943.748041                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            97027                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65057.378732                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7025854                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162288                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            43.292505                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            97004                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65057.313836                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7028000                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162262                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            43.312667                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 47465.165488                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.060465                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.009465                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 12271.489149                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5249.654166                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.724261                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001084                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 47442.808035                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.645866                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000381                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12256.178987                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5286.680567                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.723920                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001093                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187248                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.080103                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992697                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187014                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.080668                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.992696                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           62                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65196                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           65                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2298                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55841                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000992                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           62                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2294                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6931                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000946                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         60441725                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        60441725                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        70902                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4431                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          75333                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       699258                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       699258                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         60457516                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        60457516                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        70014                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4411                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          74425                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       699241                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       699241                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           51                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           51                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       164486                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       164486                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2871960                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      2871960                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534033                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       534033                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        70902                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         4431                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      2871960                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       698519                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         3645812                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        70902                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         4431                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      2871960                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       698519                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        3645812                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          128                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          130                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2782                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2782                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data       164459                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       164459                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2873562                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      2873562                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534090                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       534090                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        70014                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         4411                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      2873562                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       698549                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         3646536                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        70014                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         4411                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      2873562                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       698549                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        3646536                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          126                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          127                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2798                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2798                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       131508                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       131508                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22945                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        22945                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14252                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        14252                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker          128                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        22945                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       145760                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        168835                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker          128                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        22945                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       145760                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       168835                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     11086500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       371000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     11457500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1074500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      1074500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10184937000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10184937000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1831389500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1831389500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1184928500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1184928500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     11086500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       371000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1831389500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11369865500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13212712500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     11086500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       371000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1831389500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11369865500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13212712500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        71030                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4433                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        75463                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       699258                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       699258                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2833                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2833                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data       131405                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       131405                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22938                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        22938                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14340                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        14340                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker          126                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        22938                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       145745                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        168810                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker          126                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        22938                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       145745                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       168810                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     11282500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        82500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     11365000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1076000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      1076000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10178186000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10178186000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1825056000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1825056000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1190867500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1190867500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     11282500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        82500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1825056000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11369053500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13205474500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     11282500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        82500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1825056000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11369053500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13205474500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        70140                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4412                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        74552                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       699241                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       699241                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2849                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2849                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       295994                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       295994                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2894905                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      2894905                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548285                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       548285                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        71030                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         4433                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      2894905                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       844279                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      3814647                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        71030                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         4433                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2894905                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       844279                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      3814647                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000451                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001723                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.981998                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.981998                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       295864                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       295864                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2896500                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      2896500                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548430                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       548430                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        70140                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         4412                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      2896500                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       844294                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      3815346                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        70140                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         4412                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2896500                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       844294                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      3815346                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001796                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000227                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001704                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982099                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982099                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.444293                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.444293                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007926                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007926                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.025994                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.025994                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000451                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007926                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172644                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.044260                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001802                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000451                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007926                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.172644                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.044260                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       185500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 88134.615385                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   386.232926                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   386.232926                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77447.280774                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77447.280774                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79816.495969                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79816.495969                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83141.208251                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83141.208251                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       185500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79816.495969                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78004.016877                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78258.136642                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86613.281250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       185500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79816.495969                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78004.016877                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78258.136642                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.444140                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.444140                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007919                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007919                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026147                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026147                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001796                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000227                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007919                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.172624                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.044245                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001796                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000227                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007919                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.172624                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.044245                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89543.650794                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        82500                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 89488.188976                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   384.560400                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   384.560400                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77456.611240                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77456.611240                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79564.739733                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79564.739733                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83045.153417                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83045.153417                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89543.650794                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        82500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79564.739733                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78006.473635                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78226.849713                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89543.650794                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        82500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79564.739733                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78006.473635                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78226.849713                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -978,41 +979,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88547                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88547                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           24                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           24                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          141                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          141                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          141                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.writebacks::writebacks        88519                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88519                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          140                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          140                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          141                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          140                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          128                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          130                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2782                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2782                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          126                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          127                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2798                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2798                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131508                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       131508                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22921                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22921                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14111                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14111                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          128                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        22921                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       145619                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168670                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          128                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        22921                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       145619                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168670                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131405                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131405                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22913                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22913                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14200                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14200                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          126                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        22913                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       145605                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168645                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          126                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        22913                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       145605                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168645                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3191                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34319                       # number of ReadReq MSHR uncacheable
@@ -1021,139 +1022,139 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3191                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61902                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       351000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     10157500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     57758000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     57758000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8869857000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8869857000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1601051500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1601051500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1033348500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1033348500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       351000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1601051500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9903205500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11514414500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      9806500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       351000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1601051500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9903205500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11514414500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     10022500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        72500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     10095000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     58085500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     58085500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8864136000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8864136000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1594702500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1594702500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1038186000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1038186000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     10022500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        72500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1594702500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9902322000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11507119500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     10022500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        72500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1594702500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9902322000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11507119500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    199170000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519970000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5719140000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4251529500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4251529500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5519931000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5719101000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4251556500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4251556500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    199170000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771499500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9970669500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001723                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.981998                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.981998                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9771487500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9970657500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001796                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000227                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001704                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982099                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982099                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.444293                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444293                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007918                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025737                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025737                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172477                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044216                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001802                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000451                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007918                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172477                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044216                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78134.615385                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20761.322789                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20761.322789                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67447.280774                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67447.280774                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69850.857292                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73229.997874                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73229.997874                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68007.646667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68265.930515                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76613.281250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       175500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69850.857292                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68007.646667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68265.930515                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.444140                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.444140                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007911                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007911                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025892                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025892                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001796                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000227                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007911                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172458                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044202                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001796                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000227                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007911                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172458                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044202                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        72500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79488.188976                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20759.649750                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.649750                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67456.611240                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67456.611240                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69598.153886                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69598.153886                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73111.690141                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73111.690141                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        72500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69598.153886                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68008.117853                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68232.793738                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        72500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69598.153886                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68008.117853                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68232.793738                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177331.341557                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166646.464058                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154135.862669                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154135.862669                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177330.088666                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166645.327661                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154136.841533                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154136.841533                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.879512                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.847436                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.675121                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.653581                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         134609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3577964                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         133644                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3578737                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       824000                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2989342                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2833                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       823959                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2990642                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2849                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2835                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894929                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       548519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2851                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295864                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295864                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2896522                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       548664                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8639925                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2647968                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15065                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160688                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          11463646                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185478080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98978525                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17732                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       284120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          284758457                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194907                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      7812293                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.034587                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.182731                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8644384                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2648037                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14998                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       158879                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11466298                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185580160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98978397                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       280560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          284856765                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      194832                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      7814541                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.034451                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.182385                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            7542089     96.54%     96.54% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             270204      3.46%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            7545321     96.55%     96.55% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             269220      3.45%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        7812293                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4534239000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        7814541                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4535355500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4347433988                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4349852430                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1312866777                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1312899273                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10632499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      10586000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      89658000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      88739000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
@@ -1249,7 +1250,7 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           187463964                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187477706                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
@@ -1258,14 +1259,14 @@ system.iobus.respLayer0.utilization               0.0                       # La
 system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.030996                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.030922                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270425383000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.030996                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064437                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064437                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270445541000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.030922                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064433                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064433                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1281,8 +1282,8 @@ system.iocache.overall_misses::realview.ide          234                       #
 system.iocache.overall_misses::total              234                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     29161877                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     29161877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4271869087                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4271869087                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4273547829                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4273547829                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ide     29161877                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     29161877                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ide     29161877                       # number of overall miss cycles
@@ -1305,17 +1306,17 @@ system.iocache.overall_miss_rate::realview.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 124623.405983                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117929.248206                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 117929.248206                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117975.591569                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117975.591569                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 124623.405983                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ide 124623.405983                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 124623.405983                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs             9                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     4.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1331,8 +1332,8 @@ system.iocache.overall_mshr_misses::realview.ide          234
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     17461877                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     17461877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2460669087                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2460669087                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2462347829                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2462347829                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ide     17461877                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     17461877                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ide     17461877                       # number of overall MSHR miss cycles
@@ -1347,66 +1348,66 @@ system.iocache.overall_mshr_miss_rate::realview.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67929.248206                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67929.248206                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67975.591569                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67975.591569                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 74623.405983                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               34319                       # Transaction distribution
-system.membus.trans_dist::ReadResp              71715                       # Transaction distribution
+system.membus.trans_dist::ReadResp              71793                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
-system.membus.trans_dist::Writeback            124737                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8493                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
+system.membus.trans_dist::Writeback            124709                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8498                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4604                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4596                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129696                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129696                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         37396                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4606                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129599                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129599                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37474                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455889                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       563451                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455849                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       563411                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 672351                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 672311                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16551136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16714909                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16548192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16711965                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19032029                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              507                       # Total snoops (count)
-system.membus.snoop_fanout::samples            403270                       # Request fanout histogram
+system.membus.pkt_size::total                19029085                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              506                       # Total snoops (count)
+system.membus.snoop_fanout::samples            403242                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  403270    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  403242    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              403270                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87538000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              403242                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87534500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1706000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1700500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           881842801                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           881620222                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          999291900                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          999181641                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64464474                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64440498                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -1439,13 +1440,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 4a6c72a8e..04e2b0998 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -352,7 +352,7 @@ type=ExeTracer
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -693,7 +693,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -803,7 +803,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -891,7 +891,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1306,9 +1306,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index ec3f91aac..7ab7491a1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -201,7 +201,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -542,7 +542,7 @@ opLat=4
 pipelined=true
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -652,7 +652,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -835,7 +835,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1176,7 +1176,7 @@ opLat=4
 pipelined=true
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1286,7 +1286,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -1399,7 +1399,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1434,7 +1434,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1849,9 +1849,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index e8a4671f3..01c286841 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:47:25
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 14 2015 23:52:21
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 6e37ea292..923e006af 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.825406                       # Nu
 sim_ticks                                2825405893500                       # Number of ticks simulated
 final_tick                               2825405893500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99518                       # Simulator instruction rate (inst/s)
-host_op_rate                                   120734                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2339943688                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 607076                       # Number of bytes of host memory used
-host_seconds                                  1207.47                       # Real time elapsed on the host
+host_inst_rate                                  67919                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82398                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1596954995                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 650656                       # Number of bytes of host memory used
+host_seconds                                  1769.25                       # Real time elapsed on the host
 sim_insts                                   120165205                       # Number of instructions simulated
 sim_ops                                     145782922                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -768,9 +768,9 @@ system.cpu0.iew.iewDispNonSpecInsts            876681                       # Nu
 system.cpu0.iew.iewIQFullEvents                 26796                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents               125236                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents         19035                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        291770                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        291768                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect       399939                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              691709                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts              691707                       # Number of branch mispredicts detected at execute
 system.cpu0.iew.iewExecutedInsts             99697701                       # Number of executed instructions
 system.cpu0.iew.iewExecLoadInsts             18022679                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts          1031168                       # Number of squashed instructions skipped in execute
@@ -3629,13 +3629,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index d2adfc64d..ff84ed2f5 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -201,7 +201,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -542,7 +542,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -652,7 +652,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -740,7 +740,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1155,9 +1155,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 124b0c524..718de535d 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:47:25
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:43:21
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index fa71746e2..5e44bb6ce 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1610,7 +1610,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1645,7 +1645,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -2060,9 +2060,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
index 392d7b9c9..9e05ec404 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
@@ -40,21 +40,19 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9104, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11912, Bank: 1
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9339, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is not active!
-Command: 1, Timestamp: 3178, Bank: 4
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7386, Bank: 2
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 8168, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: Returning zero for read from miscreg pmcr
@@ -66,28 +64,27 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[2]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
-warn: 	instruction 'mcr bpiall' unimplemented
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: 	instruction 'mcr bpiall' unimplemented
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -106,6 +103,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
index 5454319fd..8581849c1 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:47:25
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:34:12
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 19db0f3e8..b0310bea3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,164 +1,160 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.823474                       # Number of seconds simulated
-sim_ticks                                2823473696000                       # Number of ticks simulated
-final_tick                               2823473696000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.823417                       # Number of seconds simulated
+sim_ticks                                2823417216000                       # Number of ticks simulated
+final_tick                               2823417216000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 253388                       # Simulator instruction rate (inst/s)
-host_op_rate                                   307362                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5820051646                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 579664                       # Number of bytes of host memory used
-host_seconds                                   485.13                       # Real time elapsed on the host
-sim_insts                                   122925898                       # Number of instructions simulated
-sim_ops                                     149109939                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 190092                       # Simulator instruction rate (inst/s)
+host_op_rate                                   230584                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4366555088                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 623124                       # Number of bytes of host memory used
+host_seconds                                   646.60                       # Real time elapsed on the host
+sim_insts                                   122913537                       # Number of instructions simulated
+sim_ops                                     149095594                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           537380                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          3052900                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           121024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           891264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         1984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           373952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2012736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker         4224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst           356480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data          3623360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           532260                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          3026788                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           122112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           894784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           379328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2028160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker         4800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst           356352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data          3635968                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10976712                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       537380                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       121024                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       373952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst       356480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1388836                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8247936                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10983560                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       532260                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       122112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       379328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst       356352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1390052                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8264064                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8265460                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8281588                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             16850                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             48221                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1891                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             13926                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           31                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5843                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             31449                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker           66                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst              5570                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data             56615                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             16770                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             47813                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             13981                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           26                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5927                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             31690                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker           75                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst              5568                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data             56812                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180484                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          128874                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                180591                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          129126                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               133255                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               133507                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           113                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              190326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1081257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               42864                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              315662                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              132444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              712858                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1496                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              126256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             1283299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              188516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1072030                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               43250                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              316915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           589                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              134351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              718335                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1700                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst              126213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             1287790                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3887662                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         190326                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          42864                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         132444                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         126256                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             491889                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2921202                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3890165                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         188516                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          43250                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         134351                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst         126213                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             492330                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2926972                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6207                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2927408                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2921202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2933179                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2926972                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          113                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             190326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1087463                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              42864                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             315662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          703                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             132444                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             712858                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1496                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             126256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            1283299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             188516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1078237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              43250                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             316915                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          589                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             134351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             718335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1700                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst             126213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            1287790                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6815070                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        115392                       # Number of read requests accepted
-system.physmem.writeReqs                        70006                       # Number of write requests accepted
-system.physmem.readBursts                      115392                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      70006                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  7377600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7488                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4479552                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   7385088                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4480384                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6823344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        115987                       # Number of read requests accepted
+system.physmem.writeReqs                        70622                       # Number of write requests accepted
+system.physmem.readBursts                      115987                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      70622                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  7416384                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4519488                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   7423168                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4519808                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          16729                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                7736                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                7063                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                7688                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                7632                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                7697                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                7461                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                7652                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7853                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                7016                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7651                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6943                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               6411                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               6488                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7344                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6713                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5927                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4604                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4172                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4724                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4597                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4526                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4564                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4573                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4592                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4263                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4993                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4344                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3939                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3901                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4724                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4019                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3458                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          16716                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                7738                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                7157                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                7568                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                7635                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                7727                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                7298                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                7875                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7810                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                7237                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7597                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7159                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               6221                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               6467                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7007                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6960                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6425                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4628                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4274                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4625                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4563                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4564                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4431                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4784                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4577                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4485                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4954                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4488                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3709                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3882                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4478                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4241                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3934                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2821902889500                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2821846409500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  115392                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  115987                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  70006                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     87082                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     25035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2573                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  70622                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     87604                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     25234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2505                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       534                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,173 +182,173 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        71                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        64                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        64                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       59                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       59                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39680                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.819355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.296873                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.728623                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15567     39.23%     39.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9452     23.82%     63.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3895      9.82%     72.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2106      5.31%     78.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1684      4.24%     82.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          926      2.33%     84.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          731      1.84%     86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          606      1.53%     88.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4713     11.88%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39680                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3702                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        31.134792                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      625.115005                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           3701     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3935                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4379                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4868                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4462                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3904                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        9                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        40043                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      298.076368                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.108717                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.784807                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15715     39.25%     39.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9618     24.02%     63.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3841      9.59%     72.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2194      5.48%     78.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1638      4.09%     82.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          995      2.48%     84.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          706      1.76%     86.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          639      1.60%     88.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4697     11.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          40043                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3750                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        30.898667                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      620.943727                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           3749     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3702                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3702                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.906807                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.729572                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       10.893119                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 6      0.16%      0.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 2      0.05%      0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.05%      0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               7      0.19%      0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3319     89.65%     90.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              56      1.51%     91.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              61      1.65%     93.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              52      1.40%     94.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              33      0.89%     95.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              54      1.46%     97.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              14      0.38%     97.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               4      0.11%     97.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              10      0.27%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.05%     97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.03%     97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.03%     97.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              54      1.46%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.08%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.08%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.05%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.03%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.03%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.14%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.11%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3702                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1386684000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3548090250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    576375000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12029.36                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            3750                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3750                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.831200                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.732451                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.879160                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 7      0.19%      0.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 3      0.08%      0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                2      0.05%      0.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               3      0.08%      0.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3363     89.68%     90.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              40      1.07%     91.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              85      2.27%     93.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              44      1.17%     94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              28      0.75%     95.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              63      1.68%     97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              19      0.51%     97.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.03%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.24%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.03%     97.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.13%     97.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.05%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              56      1.49%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.05%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.08%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.03%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.03%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.03%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.03%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             5      0.13%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3750                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1369225250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3541994000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    579405000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11815.79                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30779.36                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.61                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.59                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.62                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.59                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30565.79                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.63                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.63                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      95329                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50259                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.70                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15220783.88                       # Average gap between requests
-system.physmem.pageHitRate                      78.58                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  160733160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   87536625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 474099600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                235560960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           179692556160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            72207385965                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1621122462750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1873980335220                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.505718                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2640566607500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     91867360000                       # Time in different power states
+system.physmem.avgWrQLen                        16.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      95975                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50480                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.82                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15121705.86                       # Average gap between requests
+system.physmem.pageHitRate                      78.53                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  160793640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   87577875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 474302400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                236170080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           179688996240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            72061472520                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1621212124500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1873921437255                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.499929                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2640719336250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     91865540000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     18778047250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     18574630750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  139247640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   75805125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 425045400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                217993680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           179692556160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            71111774430                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1616695526250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1868357948685                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.638582                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2642185763250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     91867360000                       # Time in different power states
+system.physmem_1.actEnergy                  141931440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   77281875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 429569400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                221428080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           179688996240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            71292253815                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1621879121250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1873730582100                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.435019                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2641834859500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     91865540000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17159721000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17456789000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -402,47 +398,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     5013                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                5013                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         5013                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           5013    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         5013                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples  56727642376                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.269102                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -15265500874    -26.91%    -26.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    71993143250    126.91%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  56727642376                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         2853     68.40%     68.40% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1318     31.60%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         4171                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5013                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                     5058                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                5058                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         5058                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           5058    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         5058                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples  56709099876                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.269517                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -15284046374    -26.95%    -26.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    71993146250    126.95%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  56709099876                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         2875     68.18%     68.18% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1342     31.82%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4217                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5058                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5013                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4171                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5058                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4217                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4171                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total         9184                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4217                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total         9275                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12054005                       # DTB read hits
-system.cpu0.dtb.read_misses                      4307                       # DTB read misses
-system.cpu0.dtb.write_hits                    9056572                       # DTB write hits
-system.cpu0.dtb.write_misses                      706                       # DTB write misses
+system.cpu0.dtb.read_hits                    12051362                       # DTB read hits
+system.cpu0.dtb.read_misses                      4340                       # DTB read misses
+system.cpu0.dtb.write_hits                    9035813                       # DTB write hits
+system.cpu0.dtb.write_misses                      718                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         172                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     358                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     378                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2897                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    2913                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   829                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   825                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      179                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12058312                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9057278                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      186                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                12055702                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9036531                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21110577                       # DTB hits
-system.cpu0.dtb.misses                           5013                       # DTB misses
-system.cpu0.dtb.accesses                     21115590                       # DTB accesses
+system.cpu0.dtb.hits                         21087175                       # DTB hits
+system.cpu0.dtb.misses                           5058                       # DTB misses
+system.cpu0.dtb.accesses                     21092233                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -472,648 +468,648 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     2456                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                2456                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples         2456                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           2456    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         2456                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples  56727642376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.269104                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -15265627374    -26.91%    -26.91% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    71993269750    126.91%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  56727642376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1347     75.13%     75.13% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          446     24.87%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         1793                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                     2491                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2491                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2491                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2491    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2491                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples  56709099876                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.269519                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -15284164374    -26.95%    -26.95% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    71993264250    126.95%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  56709099876                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1355     75.15%     75.15% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          448     24.85%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         1803                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2456                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2456                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2491                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2491                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1793                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1793                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         4249                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    56651895                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2456                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1803                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1803                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4294                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    56612424                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2491                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         172                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     358                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     378                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1793                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1798                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                56654351                       # ITB inst accesses
-system.cpu0.itb.hits                         56651895                       # DTB hits
-system.cpu0.itb.misses                           2456                       # DTB misses
-system.cpu0.itb.accesses                     56654351                       # DTB accesses
-system.cpu0.numCycles                        68396174                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                56614915                       # ITB inst accesses
+system.cpu0.itb.hits                         56612424                       # DTB hits
+system.cpu0.itb.misses                           2491                       # DTB misses
+system.cpu0.itb.accesses                     56614915                       # DTB accesses
+system.cpu0.numCycles                        68338048                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   55195315                       # Number of instructions committed
-system.cpu0.committedOps                     66856964                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             58675450                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4621                       # Number of float alu accesses
-system.cpu0.num_func_calls                    5764530                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7314757                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    58675450                       # number of integer instructions
-system.cpu0.num_fp_insts                         4621                       # number of float instructions
-system.cpu0.num_int_register_reads          108161484                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          40950551                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3516                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1106                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           203464939                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           24566154                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     21694661                       # number of memory refs
-system.cpu0.num_load_insts                   12202966                       # Number of load instructions
-system.cpu0.num_store_insts                   9491695                       # Number of store instructions
-system.cpu0.num_idle_cycles              64604771.704346                       # Number of idle cycles
-system.cpu0.num_busy_cycles              3791402.295654                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055433                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944567                       # Percentage of idle cycles
-system.cpu0.Branches                         13394190                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2179      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46192822     67.99%     67.99% # Class of executed instruction
-system.cpu0.op_class::IntMult                   50582      0.07%     68.06% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              3903      0.01%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::MemRead                12202966     17.96%     86.03% # Class of executed instruction
-system.cpu0.op_class::MemWrite                9491695     13.97%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   55154455                       # Number of instructions committed
+system.cpu0.committedOps                     66797328                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             58626360                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4657                       # Number of float alu accesses
+system.cpu0.num_func_calls                    5768343                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7305007                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    58626360                       # number of integer instructions
+system.cpu0.num_fp_insts                         4657                       # number of float instructions
+system.cpu0.num_int_register_reads          108074182                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          40930233                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3548                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1110                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           203289315                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           24533313                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     21670788                       # number of memory refs
+system.cpu0.num_load_insts                   12200183                       # Number of load instructions
+system.cpu0.num_store_insts                   9470605                       # Number of store instructions
+system.cpu0.num_idle_cycles              64551377.953400                       # Number of idle cycles
+system.cpu0.num_busy_cycles              3786670.046600                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.055411                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.944589                       # Percentage of idle cycles
+system.cpu0.Branches                         13387911                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2178      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46158472     67.99%     68.00% # Class of executed instruction
+system.cpu0.op_class::IntMult                   50521      0.07%     68.07% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.07% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              3911      0.01%     68.08% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.08% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.08% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.08% # Class of executed instruction
+system.cpu0.op_class::MemRead                12200183     17.97%     86.05% # Class of executed instruction
+system.cpu0.op_class::MemWrite                9470605     13.95%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  67944147                       # Class of executed instruction
+system.cpu0.op_class::total                  67885870                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3087                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           833490                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.996671                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           45958483                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           834002                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.105963                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements           832545                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.996677                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           45907523                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           833057                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.107301                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.294893                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.112781                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.133577                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data    11.455419                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.943935                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.021705                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011980                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.022374                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.190626                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.229209                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.101691                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data    15.475151                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937872                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.021932                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009964                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.030225                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          363                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           87                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        193340724                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       193340724                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11422910                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      3593204                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4066922                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data      6785601                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25868637                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      8719261                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      2659250                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      3172966                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data      4237084                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18788561                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       177218                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        53891                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        68030                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data        87717                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       386856                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       215939                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74279                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        70102                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        90632                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       450952                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216972                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        75904                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        72697                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data        95027                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460600                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20142171                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      6252454                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7239888                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     11022685                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        44657198                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20319389                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      6306345                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7307918                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     11110402                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       45044054                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       171223                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        51523                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data        83889                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data       223011                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       529646                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       111924                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        33653                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       105580                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      1235287                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1486444                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54469                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        16872                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data        18830                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data        46816                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       136987                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3702                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2319                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3513                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         8435                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        17969                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data           21                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           21                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       283147                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data        85176                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       189469                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      1458298                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2016090                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       337616                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       102048                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data       208299                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      1505114                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2153077                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    825879500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1199033500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3362095000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5387008000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1242542000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   5087689996                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  62077343955                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  68407575951                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28207500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     45088000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    123538000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    196833500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       598500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       598500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   2068421500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data   6286723496                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data  65439438955                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  73794583951                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   2068421500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data   6286723496                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data  65439438955                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  73794583951                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     11594133                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      3644727                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4150811                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data      7008612                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26398283                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      8831185                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      2692903                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3278546                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data      5472371                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     20275005                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       231687                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        70763                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        86860                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       134533                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       523843                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       219641                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        76598                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        73615                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        99067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       468921                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216972                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        75904                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        72697                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        95048                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       460621                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     20425318                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      6337630                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7429357                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     12480983                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     46673288                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     20657005                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      6408393                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7516217                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     12615516                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     47197131                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014768                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.014136                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.020210                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031820                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.020064                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012674                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.012497                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.032203                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.225732                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.073314                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235097                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.238430                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.216786                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.347989                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.261504                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016855                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.030275                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.047721                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.085144                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038320                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000221                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000046                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013863                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013440                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.025503                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.116842                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.043196                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016344                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015924                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.027713                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.119307                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.045619                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16029.336413                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14293.095638                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15075.915538                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10170.959471                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36922.176329                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48188.009055                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 50253.377519                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 46020.957366                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12163.648124                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12834.614290                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14645.880261                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10954.059770                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        28500                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        28500                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24284.088241                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33180.749864                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44873.845370                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36602.822270                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20269.103755                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30181.246650                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43478.061433                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34274.010614                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       338196                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        50180                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            13872                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            843                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    24.379758                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    59.525504                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses        193172668                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       193172668                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11421172                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      3580628                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4071004                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data      6755438                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25828242                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      8699311                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      2636349                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      3181823                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data      4260254                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18777737                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       177063                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        53114                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        68363                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu3.data        88668                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       387208                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       215845                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        73517                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        70445                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        91068                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       450875                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216890                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        75092                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        73078                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data        95506                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       460566                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20120483                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      6216977                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      7252827                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data     11015692                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        44605979                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20297546                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      6270091                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      7321190                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data     11104360                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       44993187                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       170716                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        51301                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data        83273                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data       224187                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       529477                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       111265                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        33298                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       105855                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      1244902                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1495320                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54398                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        16590                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data        18761                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data        47749                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       137498                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3722                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2258                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3555                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         8411                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        17946                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data           27                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           27                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       281981                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        84599                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       189128                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      1469089                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2024797                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       336379                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       101189                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data       207889                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      1516838                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2162295                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    822368000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1195559500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3372103500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5390031000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1232764000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   5110938996                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  62452939134                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  68796642130                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27576000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     45083500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    122776500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    195436000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       593500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       593500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   2055132000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data   6306498496                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data  65825042634                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  74186673130                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   2055132000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data   6306498496                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data  65825042634                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  74186673130                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11591888                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      3631929                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4154277                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data      6979625                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26357719                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      8810576                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      2669647                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3287678                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data      5505156                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     20273057                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       231461                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        69704                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        87124                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       136417                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       524706                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       219567                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        75775                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        74000                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        99479                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       468821                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216890                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        75092                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        73078                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        95533                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460593                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     20402464                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      6301576                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7441955                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     12484781                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     46630776                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     20633925                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      6371280                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7529079                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     12621198                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     47155482                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014727                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.014125                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.020045                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.032120                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.020088                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012629                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.012473                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.032197                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.226134                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.073759                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235020                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.238006                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.215337                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.350022                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.262048                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016952                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.029799                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048041                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.084551                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038279                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000283                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000059                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013821                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013425                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.025414                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.117670                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.043422                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016302                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015882                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.027611                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.120182                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.045855                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16030.252822                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14357.108547                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15041.476535                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10179.915275                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37022.163493                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48282.452374                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 50166.952205                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 46007.972962                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12212.577502                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12681.715893                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14597.134705                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10890.226234                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 21981.481481                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21981.481481                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24292.627572                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33345.133962                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44806.708534                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36639.067092                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20309.836049                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30335.893174                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43396.224669                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34309.228449                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       331201                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        49900                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            13718                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            839                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    24.143534                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    59.475566                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       692577                       # number of writebacks
-system.cpu0.dcache.writebacks::total           692577                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           93                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data         8510                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data       110579                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       119182                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        48694                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1138393                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1187087                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1619                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2417                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5353                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9389                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data           93                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data        57204                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      1248972                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1306269                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data           93                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data        57204                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      1248972                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1306269                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        51430                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        75379                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       112432                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       239241                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        33653                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        56886                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        96894                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       187433                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        16552                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        15262                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        32143                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        63957                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data          700                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1096                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         3082                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4878                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           21                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           21                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        85083                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       132265                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data       209326                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       426674                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       101635                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       147527                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data       241469                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       490631                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         4098                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6759                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7555                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18412                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3203                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5165                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         5997                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14365                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         7301                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        11924                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        13552                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        32777                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    773027500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1007573000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1610752500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3391353000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1208889000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2669627000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   4928516402                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8807032402                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    214952000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    207552500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    496800000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    919304500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      8874500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     16213500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     51414500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76502500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       577500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       577500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1981916500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3677200000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   6539268902                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  12198385402                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2196868500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3884752500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   7036068902                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13117689902                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    706453000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1317087500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1529047000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3552587500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    543393000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    982352000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1199505482                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2725250482                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1249846000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2299439500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2728552482                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6277837982                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014111                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018160                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016042                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009063                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.012497                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017351                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017706                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009245                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.233908                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.175708                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.238923                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.122092                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.009139                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.014888                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.031110                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010403                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000221                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000046                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013425                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017803                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.016772                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.009142                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.015860                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019628                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019141                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.010395                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15030.672759                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13366.759973                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14326.459549                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14175.467416                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35922.176329                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46929.420244                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50865.031911                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46987.629724                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12986.466892                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13599.298912                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15455.931307                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14373.790203                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12677.857143                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14793.339416                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16682.186892                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15683.169332                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        27500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        27500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23293.918879                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27801.761615                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31239.640092                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28589.474404                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21615.275250                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26332.484901                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29138.601237                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26736.365827                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172389.702294                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194864.255067                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202388.749173                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192949.570932                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169651.264440                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190193.998064                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200017.589128                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189714.617612                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171188.330366                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192841.286481                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201339.468861                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191531.805290                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       690898                       # number of writebacks
+system.cpu0.dcache.writebacks::total           690898                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           95                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data         8080                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data       111730                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       119905                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        48720                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1147356                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1196076                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1581                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2443                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5244                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9268                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data           95                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data        56800                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      1259086                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1315981                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data           95                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data        56800                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      1259086                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1315981                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        51206                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        75193                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       112457                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       238856                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        33298                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        57135                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        97546                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       187979                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        16263                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        15185                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        32548                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        63996                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data          677                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1112                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         3167                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4956                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           27                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           27                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        84504                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       132328                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data       210003                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       426835                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       100767                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       147513                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data       242551                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       490831                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         4191                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6644                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7640                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18475                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3264                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5115                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6049                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14428                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         7455                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        11759                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        13689                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        32903                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    769942000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1010315000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1623285000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3403542000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1199466000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2687448500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   4925947438                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8812861938                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    208330500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    207010000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    504057000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    919397500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      8657000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     16053500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     52056000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76766500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       566500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       566500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1969408000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3697763500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   6549232438                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12216403938                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2177738500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3904773500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   7053289438                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13135801438                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    729067500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1290773000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1548554500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3568395000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    558890500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    964426500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1217476000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2740793000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1287958000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2255199500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2766030500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6309188000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014099                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018100                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016112                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009062                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.012473                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017379                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017719                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009272                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.233315                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.174292                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.238592                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.121965                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.008934                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.015027                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.031836                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010571                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000283                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000059                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013410                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017781                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.016821                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.009154                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.015816                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019592                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019218                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.010409                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15036.167637                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13436.290612                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14434.717270                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14249.346887                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36022.163493                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47036.816312                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50498.712792                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46882.162039                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12810.090389                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13632.532104                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15486.573676                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14366.483843                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12787.296898                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14436.600719                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16437.006631                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15489.608555                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20981.481481                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.481481                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23305.500331                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27943.923433                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31186.375614                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28620.904888                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21611.623845                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26470.707666                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29079.613929                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26762.371240                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173960.272011                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194276.490066                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202690.379581                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193147.225981                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171228.707108                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188548.680352                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201268.970078                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189963.473801                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172764.319249                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 191784.973212                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 202062.276280                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191751.147312                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1976565                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.476096                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           92948208                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1977077                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            47.012943                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12310006500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   437.069776                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    12.930889                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    27.368710                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst    34.106720                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.853652                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.025256                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.053455                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.066615                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998977                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1974956                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.476580                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           92807649                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1975468                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            46.980082                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      12281782000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   436.693136                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    12.890649                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    27.321957                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst    34.570838                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.852916                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.025177                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.053363                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.067521                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998978                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          260                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          253                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         96944326                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        96944326                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     55908893                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     17531533                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     10096307                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst      9411475                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       92948208                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     55908893                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     17531533                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     10096307                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst      9411475                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        92948208                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     55908893                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     17531533                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     10096307                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst      9411475                       # number of overall hits
-system.cpu0.icache.overall_hits::total       92948208                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       744795                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       210904                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       477702                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst       585610                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2019011                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       744795                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       210904                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       477702                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst       585610                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2019011                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       744795                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       210904                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       477702                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst       585610                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2019011                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2877146000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6627355500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   7849748489                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  17354249989                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2877146000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   6627355500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst   7849748489                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  17354249989                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2877146000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   6627355500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst   7849748489                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  17354249989                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     56653688                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     17742437                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     10574009                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst      9997085                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     94967219                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     56653688                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     17742437                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     10574009                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst      9997085                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     94967219                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     56653688                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     17742437                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     10574009                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst      9997085                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     94967219                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013146                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011887                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045177                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.058578                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.021260                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013146                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011887                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045177                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.058578                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.021260                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013146                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011887                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045177                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.058578                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.021260                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.969806                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13873.409573                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13404.396252                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8595.421218                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13641.969806                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13873.409573                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13404.396252                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8595.421218                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13641.969806                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13873.409573                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13404.396252                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8595.421218                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3398                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         96800349                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        96800349                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     55869890                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     17502013                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     10084181                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst      9351565                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       92807649                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     55869890                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     17502013                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst     10084181                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst      9351565                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        92807649                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     55869890                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     17502013                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     10084181                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst      9351565                       # number of overall hits
+system.cpu0.icache.overall_hits::total       92807649                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       744337                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       208894                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       479974                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst       583995                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2017200                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       744337                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       208894                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       479974                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu3.inst       583995                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2017200                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       744337                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       208894                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       479974                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst       583995                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2017200                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2851244000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6659691500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   7828995491                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  17339930991                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2851244000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   6659691500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst   7828995491                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  17339930991                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2851244000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   6659691500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst   7828995491                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  17339930991                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     56614227                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     17710907                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     10564155                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst      9935560                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     94824849                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     56614227                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     17710907                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     10564155                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst      9935560                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     94824849                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     56614227                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     17710907                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     10564155                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst      9935560                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     94824849                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013148                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011795                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045434                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.058778                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.021273                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013148                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011795                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045434                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.058778                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.021273                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013148                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011795                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045434                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.058778                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.021273                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13649.238370                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13875.108860                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13405.928974                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8596.039555                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13649.238370                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13875.108860                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13405.928974                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8596.039555                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13649.238370                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13875.108860                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13405.928974                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8596.039555                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3541                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              209                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              202                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.258373                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.529703                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        41904                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        41904                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst        41904                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        41904                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst        41904                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        41904                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       210904                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       477702                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       543706                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1232312                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       210904                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       477702                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst       543706                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1232312                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       210904                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       477702                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst       543706                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1232312                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2666242000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6149653500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   6934315992                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  15750211492                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2666242000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6149653500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   6934315992                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  15750211492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2666242000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6149653500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   6934315992                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  15750211492                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011887                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045177                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.054386                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012976                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011887                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045177                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.054386                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.012976                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011887                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045177                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.054386                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.012976                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12641.969806                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12873.409573                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.797074                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.025821                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12641.969806                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12873.409573                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.797074                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.025821                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12641.969806                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12873.409573                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.797074                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.025821                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        41700                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        41700                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst        41700                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        41700                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst        41700                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        41700                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       208894                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       479974                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       542295                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1231163                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       208894                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       479974                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst       542295                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1231163                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       208894                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       479974                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst       542295                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1231163                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2642350000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6179717500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   6915980993                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  15738048493                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2642350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6179717500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   6915980993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  15738048493                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2642350000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6179717500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   6915980993                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  15738048493                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011795                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045434                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.054581                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012984                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011795                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045434                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.054581                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.012984                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011795                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045434                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.054581                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.012984                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12649.238370                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12875.108860                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.171232                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12783.074616                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12649.238370                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12875.108860                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.171232                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12783.074616                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12649.238370                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12875.108860                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.171232                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12783.074616                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1144,58 +1140,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     1944                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                1944                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          547                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1397                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         1944                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           1944    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         1944                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1569                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12632.887189                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11014.350507                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6231.121643                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::2048-4095           15      0.96%      0.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-6143          406     25.88%     26.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::10240-12287          522     33.27%     60.10% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-14335          230     14.66%     74.76% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::14336-16383           77      4.91%     79.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::22528-24575          319     20.33%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1569                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     1838                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                1838                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          545                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1293                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         1838                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           1838    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         1838                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1481                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10921.336935                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9355.199997                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6102.562917                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::2048-4095           15      1.01%      1.01% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-6143          577     38.96%     39.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::10240-12287          520     35.11%     75.08% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-14335          129      8.71%     83.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::14336-16383           18      1.22%     85.01% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::22528-24575          222     14.99%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1481                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1032     65.77%     65.77% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          537     34.23%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1569                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1944                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K          946     63.88%     63.88% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          535     36.12%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1481                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1838                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1944                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1569                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1838                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1481                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1569                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         3513                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1481                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         3319                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3796186                       # DTB read hits
-system.cpu1.dtb.read_misses                      1676                       # DTB read misses
-system.cpu1.dtb.write_hits                    2772085                       # DTB write hits
-system.cpu1.dtb.write_misses                      268                       # DTB write misses
+system.cpu1.dtb.read_hits                     3781599                       # DTB read hits
+system.cpu1.dtb.read_misses                      1598                       # DTB read misses
+system.cpu1.dtb.write_hits                    2748070                       # DTB write hits
+system.cpu1.dtb.write_misses                      240                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         152                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     168                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     142                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1249                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1169                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   236                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   241                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                       75                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3797862                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2772353                       # DTB write accesses
+system.cpu1.dtb.perms_faults                       67                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3783197                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2748310                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6568271                       # DTB hits
-system.cpu1.dtb.misses                           1944                       # DTB misses
-system.cpu1.dtb.accesses                      6570215                       # DTB accesses
+system.cpu1.dtb.hits                          6529669                       # DTB hits
+system.cpu1.dtb.misses                           1838                       # DTB misses
+system.cpu1.dtb.accesses                      6531507                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1225,128 +1221,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     1001                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                1001                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walks                      906                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                 906                       # Table walker walks initiated with short descriptors
 system.cpu1.itb.walker.walksShortTerminationLevel::Level1          197                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2          804                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         1001                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           1001    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         1001                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          723                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12766.251729                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11015.623409                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6540.201330                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143          211     29.18%     29.18% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287          195     26.97%     56.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335          151     20.89%     77.04% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383            4      0.55%     77.59% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575          162     22.41%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          723                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2          709                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples          906                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0            906    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total          906                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          660                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11564.393939                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9819.657022                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6526.531967                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143          251     38.03%     38.03% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          195     29.55%     67.58% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335           88     13.33%     80.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383            3      0.45%     81.36% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575          123     18.64%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          660                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          526     72.75%     72.75% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          197     27.25%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          723                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K          463     70.15%     70.15% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          197     29.85%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          660                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1001                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1001                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          906                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total          906                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          723                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          723                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         1724                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    17742437                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1001                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          660                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          660                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         1566                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    17710907                       # ITB inst hits
+system.cpu1.itb.inst_misses                       906                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         152                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     168                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     142                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     750                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     687                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                17743438                       # ITB inst accesses
-system.cpu1.itb.hits                         17742437                       # DTB hits
-system.cpu1.itb.misses                           1001                       # DTB misses
-system.cpu1.itb.accesses                     17743438                       # DTB accesses
-system.cpu1.numCycles                       143583360                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                17711813                       # ITB inst accesses
+system.cpu1.itb.hits                         17710907                       # DTB hits
+system.cpu1.itb.misses                            906                       # DTB misses
+system.cpu1.itb.accesses                     17711813                       # DTB accesses
+system.cpu1.numCycles                       143508927                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   17142475                       # Number of instructions committed
-system.cpu1.committedOps                     20690900                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             18446976                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1261                       # Number of float alu accesses
-system.cpu1.num_func_calls                    2007420                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2180791                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    18446976                       # number of integer instructions
-system.cpu1.num_fp_insts                         1261                       # number of float instructions
-system.cpu1.num_int_register_reads           34256544                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          12938178                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                 872                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                390                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            75360742                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            7365753                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6767228                       # number of memory refs
-system.cpu1.num_load_insts                    3839902                       # Number of load instructions
-system.cpu1.num_store_insts                   2927326                       # Number of store instructions
-system.cpu1.num_idle_cycles              136602426.841061                       # Number of idle cycles
-system.cpu1.num_busy_cycles              6980933.158939                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.048619                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.951381                       # Percentage of idle cycles
-system.cpu1.Branches                          4294582                       # Number of branches fetched
+system.cpu1.committedInsts                   17104818                       # Number of instructions committed
+system.cpu1.committedOps                     20623291                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             18381943                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1289                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1997851                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2177891                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    18381943                       # number of integer instructions
+system.cpu1.num_fp_insts                         1289                       # number of float instructions
+system.cpu1.num_int_register_reads           34111926                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          12889581                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                 904                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                386                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            75094286                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            7377149                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6727087                       # number of memory refs
+system.cpu1.num_load_insts                    3824966                       # Number of load instructions
+system.cpu1.num_store_insts                   2902121                       # Number of store instructions
+system.cpu1.num_idle_cycles              136535289.121910                       # Number of idle cycles
+system.cpu1.num_busy_cycles              6973637.878090                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.048594                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.951406                       # Percentage of idle cycles
+system.cpu1.Branches                          4285863                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   47      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 14519635     68.15%     68.15% # Class of executed instruction
-system.cpu1.op_class::IntMult                   16307      0.08%     68.23% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               962      0.00%     68.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.24% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.24% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3839902     18.02%     86.26% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2927326     13.74%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 14489486     68.24%     68.24% # Class of executed instruction
+system.cpu1.op_class::IntMult                   16051      0.08%     68.31% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.31% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               956      0.00%     68.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.32% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3824966     18.01%     86.33% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2902121     13.67%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  21304179                       # Class of executed instruction
+system.cpu1.op_class::total                  21233627                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups                5611894                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          2863788                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           506095                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3300567                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                2344817                       # Number of BTB hits
+system.cpu2.branchPred.lookups                5616381                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          2865516                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           500930                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3264186                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                2338379                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.042854                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                1575596                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            331093                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            71.637431                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                1579826                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            329229                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1376,56 +1372,56 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    12465                       # Table walker walks requested
-system.cpu2.dtb.walker.walksShort               12465                       # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         7792                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4673                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        12465                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          12465    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        12465                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples         2089                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 13064.145524                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 11307.663622                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev  6855.441685                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-8191          538     25.75%     25.75% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::8192-16383         1043     49.93%     75.68% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::16384-24575          506     24.22%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::81920-90111            2      0.10%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total         2089                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks                    12496                       # Table walker walks requested
+system.cpu2.dtb.walker.walksShort               12496                       # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         7848                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4648                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        12496                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          12496    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        12496                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples         2107                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 12567.631704                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 10798.757465                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev  6853.701577                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-8191          615     29.19%     29.19% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::8192-16383         1022     48.50%     77.69% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-24575          468     22.21%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::81920-90111            2      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total         2107                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000070000                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000070000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000070000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K         1323     63.33%     63.33% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M          766     36.67%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total         2089                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12465                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K         1329     63.08%     63.08% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M          778     36.92%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total         2107                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12496                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12465                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2089                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12496                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2107                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2089                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total        14554                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2107                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total        14603                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     4354485                       # DTB read hits
-system.cpu2.dtb.read_misses                     11147                       # DTB read misses
-system.cpu2.dtb.write_hits                    3379229                       # DTB write hits
-system.cpu2.dtb.write_misses                     1318                       # DTB write misses
+system.cpu2.dtb.read_hits                     4358544                       # DTB read hits
+system.cpu2.dtb.read_misses                     11242                       # DTB read misses
+system.cpu2.dtb.write_hits                    3388369                       # DTB write hits
+system.cpu2.dtb.write_misses                     1254                       # DTB write misses
 system.cpu2.dtb.flush_tlb                         152                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     167                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva                     166                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    1531                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      193                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   294                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    1540                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      194                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   307                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      117                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 4365632                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3380547                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      126                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 4369786                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3389623                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                          7733714                       # DTB hits
-system.cpu2.dtb.misses                          12465                       # DTB misses
-system.cpu2.dtb.accesses                      7746179                       # DTB accesses
+system.cpu2.dtb.hits                          7746913                       # DTB hits
+system.cpu2.dtb.misses                          12496                       # DTB misses
+system.cpu2.dtb.accesses                      7759409                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1455,80 +1451,80 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                     1328                       # Table walker walks requested
-system.cpu2.itb.walker.walksShort                1328                       # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walks                     1368                       # Table walker walks requested
+system.cpu2.itb.walker.walksShort                1368                       # Table walker walks initiated with short descriptors
 system.cpu2.itb.walker.walksShortTerminationLevel::Level1          246                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1082                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples         1328                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0           1328    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total         1328                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples          881                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 12986.379115                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 11270.183591                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev  6464.618437                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143          240     27.24%     27.24% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287          238     27.01%     54.26% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335          191     21.68%     75.94% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383            6      0.68%     76.62% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575          206     23.38%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total          881                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1122                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples         1368                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0           1368    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total         1368                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples          900                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12559.444444                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 10783.610995                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev  6567.445052                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143          280     31.11%     31.11% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287          242     26.89%     58.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335          171     19.00%     77.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383            5      0.56%     77.56% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575          202     22.44%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total          900                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000055500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000055500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000055500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K          640     72.64%     72.64% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M          241     27.36%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total          881                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K          655     72.78%     72.78% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M          245     27.22%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total          900                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1328                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1328                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1368                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1368                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          881                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total          881                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total         2209                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    10575904                       # ITB inst hits
-system.cpu2.itb.inst_misses                      1328                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          900                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total          900                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total         2268                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    10566039                       # ITB inst hits
+system.cpu2.itb.inst_misses                      1368                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.itb.flush_tlb                         152                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     167                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva                     166                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                     923                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                     943                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1777                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1761                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                10577232                       # ITB inst accesses
-system.cpu2.itb.hits                         10575904                       # DTB hits
-system.cpu2.itb.misses                           1328                       # DTB misses
-system.cpu2.itb.accesses                     10577232                       # DTB accesses
-system.cpu2.numCycles                      1381990575                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                10567407                       # ITB inst accesses
+system.cpu2.itb.hits                         10566039                       # DTB hits
+system.cpu2.itb.misses                           1368                       # DTB misses
+system.cpu2.itb.accesses                     10567407                       # DTB accesses
+system.cpu2.numCycles                      1381994110                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                   19415856                       # Number of instructions committed
-system.cpu2.committedOps                     23538274                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                      1407481                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                      550                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                  4259391923                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             71.178452                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.014049                       # IPC: instructions per cycle
+system.cpu2.committedInsts                   19454188                       # Number of instructions committed
+system.cpu2.committedOps                     23590012                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                      1394518                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                      553                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                  4259350283                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             71.038386                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.014077                       # IPC: instructions per cycle
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                       41337448                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     1340653127                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               13659827                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted          7557018                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect           321485                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups             8617850                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                6480530                       # Number of BTB hits
+system.cpu2.tickCycles                       41318295                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     1340675815                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               13596196                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted          7509425                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect           305533                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups             8486163                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                6439399                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            75.198919                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                3094736                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect             16291                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            75.881161                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                3090908                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect             15400                       # Number of incorrect RAS predictions.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1558,88 +1554,90 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                    35471                       # Table walker walks requested
-system.cpu3.dtb.walker.walksShort               35471                       # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11945                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         7769                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore        15757                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples        19714                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean   617.099523                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev  4045.428418                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-16383        19501     98.92%     98.92% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-32767          152      0.77%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-49151           42      0.21%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walks                    33126                       # Table walker walks requested
+system.cpu3.dtb.walker.walksShort               33126                       # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11032                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         7972                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore        14122                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples        19004                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean   831.246053                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev  4468.197044                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383        18648     98.13%     98.13% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-32767          304      1.60%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-49151           32      0.17%     99.89% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::49152-65535            8      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-81919            7      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-81919            8      0.04%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::81920-98303            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::98304-114687            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::131072-147455            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total        19714                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples         6425                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 12552.451362                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 10392.470797                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev  7297.231216                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-8191         1902     29.60%     29.60% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::8192-16383         3093     48.14%     77.74% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-24575         1290     20.08%     97.82% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::24576-32767           56      0.87%     98.69% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-40959           42      0.65%     99.35% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::40960-49151           37      0.58%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-57343            1      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::57344-65535            3      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::81920-90111            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total         6425                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples  -8701578064                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     1.155310                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1  -8749138564    100.55%    100.55% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3     32608500     -0.37%    100.17% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5      7394500     -0.08%    100.09% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7      2262500     -0.03%    100.06% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9      1618000     -0.02%    100.04% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11      1153500     -0.01%    100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13       459000     -0.01%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15      1335500     -0.02%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17       300000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19       181000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21       108000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23        25500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25        53500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27        12000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-29        19000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::30-31        30000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total  -8701578064                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K         1781     71.41%     71.41% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M          713     28.59%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total         2494                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        35471                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkWaitTime::total        19004                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples         6133                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 11867.275395                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean  9714.087610                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev  7406.609922                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-8191         2110     34.40%     34.40% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::8192-16383         2847     46.42%     80.83% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::16384-24575         1040     16.96%     97.78% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::24576-32767           49      0.80%     98.58% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-40959           40      0.65%     99.23% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::40960-49151           39      0.64%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::49152-57343            3      0.05%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::57344-65535            3      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::81920-90111            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::90112-98303            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total         6133                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples  -8716832064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.261873                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::stdev     0.297258                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1  -8763394564    100.53%    100.53% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3     31995000     -0.37%    100.17% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5      7342000     -0.08%    100.08% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7      3254000     -0.04%    100.05% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9      1291000     -0.01%    100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11       970500     -0.01%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13       493000     -0.01%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15       640500     -0.01%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17       281000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19        70500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21       112500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23        18500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25        49000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27         6500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-29        10500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::30-31        28000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total  -8716832064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K         1783     70.92%     70.92% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M          731     29.08%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total         2514                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33126                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        35471                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2494                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33126                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2514                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2494                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total        37965                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2514                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total        35640                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                     7577935                       # DTB read hits
-system.cpu3.dtb.read_misses                     29413                       # DTB read misses
-system.cpu3.dtb.write_hits                    5839655                       # DTB write hits
-system.cpu3.dtb.write_misses                     6058                       # DTB write misses
+system.cpu3.dtb.read_hits                     7551044                       # DTB read hits
+system.cpu3.dtb.read_misses                     27915                       # DTB read misses
+system.cpu3.dtb.write_hits                    5856516                       # DTB write hits
+system.cpu3.dtb.write_misses                     5211                       # DTB write misses
 system.cpu3.dtb.flush_tlb                         158                       # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva                     224                       # Number of times TLB was flushed by MVA
+system.cpu3.dtb.flush_tlb_mva                     231                       # Number of times TLB was flushed by MVA
 system.cpu3.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                    1709                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                      415                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                   739                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_entries                    1721                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                      394                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                   742                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                      327                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                 7607348                       # DTB read accesses
-system.cpu3.dtb.write_accesses                5845713                       # DTB write accesses
+system.cpu3.dtb.perms_faults                      328                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                 7578959                       # DTB read accesses
+system.cpu3.dtb.write_accesses                5861727                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                         13417590                       # DTB hits
-system.cpu3.dtb.misses                          35471                       # DTB misses
-system.cpu3.dtb.accesses                     13453061                       # DTB accesses
+system.cpu3.dtb.hits                         13407560                       # DTB hits
+system.cpu3.dtb.misses                          33126                       # DTB misses
+system.cpu3.dtb.accesses                     13440686                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1669,385 +1667,385 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                     4217                       # Table walker walks requested
-system.cpu3.itb.walker.walksShort                4217                       # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1465                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2667                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore           85                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples         4132                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1732.090997                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  7203.300582                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-16383         3973     96.15%     96.15% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-32767          122      2.95%     99.10% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-49151           16      0.39%     99.49% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-65535           12      0.29%     99.78% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-81919            4      0.10%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::81920-98303            2      0.05%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-114687            1      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::114688-131071            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-147455            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total         4132                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walks                     4167                       # Table walker walks requested
+system.cpu3.itb.walker.walksShort                4167                       # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1453                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2641                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore           73                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples         4094                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1495.114802                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  5985.882126                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-8191         3827     93.48%     93.48% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::8192-16383          124      3.03%     96.51% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-24575           85      2.08%     98.58% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::24576-32767           26      0.64%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-40959           12      0.29%     99.51% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::40960-49151            6      0.15%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-57343            5      0.12%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::57344-65535            4      0.10%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-73727            3      0.07%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::73728-81919            2      0.05%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total         4094                       # Table walker wait (enqueue to first request) latency
 system.cpu3.itb.walker.walkCompletionTime::samples         1265                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 13666.007905                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 11737.085754                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev  7328.478477                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-4095           21      1.66%      1.66% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::4096-8191          283     22.37%     24.03% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-12287          342     27.04%     51.07% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::12288-16383          308     24.35%     75.42% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-20479           17      1.34%     76.76% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::20480-24575          261     20.63%     97.39% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-28671            6      0.47%     97.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::28672-32767            7      0.55%     98.42% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-36863            1      0.08%     98.50% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::36864-40959            7      0.55%     99.05% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-45055            9      0.71%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::45056-49151            2      0.16%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::57344-61439            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 13262.450593                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 11104.068636                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev  7912.964367                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095           17      1.34%      1.34% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191          362     28.62%     29.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287          345     27.27%     57.23% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383          231     18.26%     75.49% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479           10      0.79%     76.28% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575          261     20.63%     96.92% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671           10      0.79%     97.71% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767            6      0.47%     98.18% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863            2      0.16%     98.34% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959            5      0.40%     98.74% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055            9      0.71%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::45056-49151            4      0.32%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::53248-57343            1      0.08%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::57344-61439            2      0.16%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu3.itb.walker.walkCompletionTime::total         1265                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples  -8974548064                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     0.863052                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev     0.342327                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0    -1226005296     13.66%     13.66% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1    -7750612268     86.36%    100.02% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2        1421000     -0.02%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3         452500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         116500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5          31500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6          48000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total  -8974548064                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K          850     72.03%     72.03% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M          330     27.97%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total         1180                       # Table walker page sizes translated
+system.cpu3.itb.walker.walksPending::samples  -4725503768                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.775529                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.415678                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -1058328796     22.40%     22.40% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1    -3669011472     77.64%    100.04% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2        1338500     -0.03%    100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3         422000     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4          76000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total  -4725503768                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K          861     72.23%     72.23% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M          331     27.77%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total         1192                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4217                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4217                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4167                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4167                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1180                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1180                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total         5397                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                     9998093                       # ITB inst hits
-system.cpu3.itb.inst_misses                      4217                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1192                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1192                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total         5359                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                     9936571                       # ITB inst hits
+system.cpu3.itb.inst_misses                      4167                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.itb.flush_tlb                         158                       # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva                     224                       # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb_mva                     231                       # Number of times TLB was flushed by MVA
 system.cpu3.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                    1209                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries                    1221                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                      709                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                      718                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                10002310                       # ITB inst accesses
-system.cpu3.itb.hits                          9998093                       # DTB hits
-system.cpu3.itb.misses                           4217                       # DTB misses
-system.cpu3.itb.accesses                     10002310                       # DTB accesses
-system.cpu3.numCycles                        55588609                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                 9940738                       # ITB inst accesses
+system.cpu3.itb.hits                          9936571                       # DTB hits
+system.cpu3.itb.misses                           4167                       # DTB misses
+system.cpu3.itb.accesses                      9940738                       # DTB accesses
+system.cpu3.numCycles                        55573485                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles          20911805                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                      54608834                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   13659827                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches           9575266                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                     32188027                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                1609304                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                     73500                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                 636                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles              188                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles       174621                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        79934                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles          246                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                  9997086                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes               214812                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                   2061                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples          54233591                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.215961                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.348203                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles          20863261                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                      54294907                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   13596196                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches           9530307                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                     32292568                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                1579965                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                     69120                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                1162                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles              268                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles       137847                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        66642                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles          261                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                  9935560                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes               207453                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                   2022                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples          54221093                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.209618                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.343030                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                39592641     73.00%     73.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                 1866738      3.44%     76.45% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                 1209172      2.23%     78.68% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 3694476      6.81%     85.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                  961111      1.77%     87.26% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                  647261      1.19%     88.45% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 2977203      5.49%     93.94% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                  646450      1.19%     95.13% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                 2638539      4.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                39652063     73.13%     73.13% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                 1860834      3.43%     76.56% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                 1199577      2.21%     78.77% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 3689809      6.81%     85.58% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                  944481      1.74%     87.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                  637799      1.18%     88.50% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 2980778      5.50%     94.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                  640190      1.18%     95.18% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                 2615562      4.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total            54233591                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.245731                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.982375                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                14602129                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles             29778773                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                  8106369                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              1026636                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                719503                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved             1079419                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred                86358                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts              47749839                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts               276699                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles                719503                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                15137242                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                3025598                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles      21153466                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                  8589840                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles              5607720                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts              45799280                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                  610                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents               1145187                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                113658                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               3954911                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands           47609045                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            210470711                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups        51575848                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups             3589                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps             39452126                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                 8156919                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts            730493                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts        676284                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                  5731608                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads             8102362                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores            6460033                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          1172202                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         1643889                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                  44018542                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded             534103                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                 41806723                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued            56092                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined        6528844                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     14989618                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved         58298                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples     54233591                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.770864                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.468112                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total            54221093                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.244653                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.976993                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                14541124                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles             29923428                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                  8020267                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              1031030                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                705051                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved             1065595                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred                86058                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts              47410230                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts               276975                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles                705051                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                15074857                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                2997482                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles      21287118                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                  8510425                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles              5645953                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts              45500627                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                  766                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents               1126128                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                117998                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               4001017                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands           47247848                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            209204758                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups        51266498                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups             3571                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps             39476281                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                 7771567                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts            731786                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts        677453                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                  5778610                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads             8053628                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores            6456539                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          1175060                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         1664059                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                  43783527                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded             535809                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                 41699371                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued            53091                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined        6234373                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     14300280                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved         56558                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples     54221093                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.769062                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.467188                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0           37808852     69.71%     69.71% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1            5406123      9.97%     79.68% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2            4124283      7.60%     87.29% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3            3378417      6.23%     93.52% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4            1383474      2.55%     96.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5             844457      1.56%     97.63% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6             890959      1.64%     99.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7             261360      0.48%     99.75% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8             135666      0.25%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0           37844395     69.80%     69.80% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1            5386682      9.93%     79.73% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2            4110296      7.58%     87.31% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3            3372256      6.22%     93.53% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4            1382084      2.55%     96.08% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5             838917      1.55%     97.63% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6             889664      1.64%     99.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7             259968      0.48%     99.75% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8             136831      0.25%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total       54233591                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total       54221093                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                  64650     10.11%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                286710     44.85%     54.96% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite               287936     45.04%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                  63437      9.96%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                290906     45.69%     55.65% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite               282359     44.35%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               64      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu             27827699     66.56%     66.56% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult               30281      0.07%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc          2306      0.01%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.64% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead             7806443     18.67%     85.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite            6139930     14.69%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass               65      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu             27741162     66.53%     66.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult               30355      0.07%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc          2311      0.01%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead             7771642     18.64%     85.24% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite            6153835     14.76%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total              41806723                       # Type of FU issued
-system.cpu3.iq.rate                          0.752074                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                     639296                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.015292                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads         138534759                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes         51105205                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses     40599791                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads               7666                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes              4221                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses         3348                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses              42441848                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                   4107                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads          178912                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total              41699371                       # Type of FU issued
+system.cpu3.iq.rate                          0.750347                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                     636702                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.015269                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads         138301991                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes         50577353                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses     40524265                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads               7637                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes              4163                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses         3346                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses              42331916                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                   4092                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads          178799                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      1280236                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses         1538                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation        28536                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores       657537                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      1221804                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses         1431                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation        28394                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores       619889                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads       107166                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked        47571                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads       105799                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked        48648                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                719503                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                2584673                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles               329572                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts           44617850                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts            80448                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts              8102362                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts             6460033                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts            277261                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                 23890                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents               299738                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents         28536                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect        153085                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect       129623                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts              282708                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts             41453550                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts              7664420                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts           317790                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles                705051                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                2546149                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles               337754                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts           44384176                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts            73225                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts              8053628                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts             6456539                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts            278302                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                 24620                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents               307122                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents         28394                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect        141723                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect       123945                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts              265668                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts             41365560                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts              7637563                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts           300776                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        65205                       # number of nop insts executed
-system.cpu3.iew.exec_refs                    13740951                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                 7582733                       # Number of branches executed
-system.cpu3.iew.exec_stores                   6076531                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.745720                       # Inst execution rate
-system.cpu3.iew.wb_sent                      41141473                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                     40603139                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                 21356385                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                 37848912                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        64840                       # number of nop insts executed
+system.cpu3.iew.exec_refs                    13731746                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                 7566030                       # Number of branches executed
+system.cpu3.iew.exec_stores                   6094183                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.744340                       # Inst execution rate
+system.cpu3.iew.wb_sent                      41063512                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                     40527611                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                 21306307                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                 37726918                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      0.730422                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.564254                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      0.729262                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.564751                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts        6551591                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls         475805                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts           236318                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples     52873966                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.719843                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.617254                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts        6255806                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls         479251                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts           220583                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples     52905057                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.720581                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.620547                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0     38351228     72.53%     72.53% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1      6390419     12.09%     84.62% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2      3217103      6.08%     90.70% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      1425073      2.70%     93.40% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4       785450      1.49%     94.88% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5       547204      1.03%     95.92% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6       964459      1.82%     97.74% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7       247730      0.47%     98.21% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8       945300      1.79%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0     38385903     72.56%     72.56% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1      6395220     12.09%     84.64% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2      3197776      6.04%     90.69% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      1426680      2.70%     93.39% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4       782047      1.48%     94.86% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5       543081      1.03%     95.89% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6       967847      1.83%     97.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7       251119      0.47%     98.19% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8       955384      1.81%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total     52873966                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts            31209379                       # Number of instructions committed
-system.cpu3.commit.committedOps              38060928                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total     52905057                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts            31237505                       # Number of instructions committed
+system.cpu3.commit.committedOps              38122392                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      12624622                       # Number of memory references committed
-system.cpu3.commit.loads                      6822126                       # Number of loads committed
-system.cpu3.commit.membars                     184951                       # Number of memory barriers committed
-system.cpu3.commit.branches                   7133186                       # Number of branches committed
+system.cpu3.commit.refs                      12668474                       # Number of memory references committed
+system.cpu3.commit.loads                      6831824                       # Number of loads committed
+system.cpu3.commit.membars                     186001                       # Number of memory barriers committed
+system.cpu3.commit.branches                   7139918                       # Number of branches committed
 system.cpu3.commit.fp_insts                      3315                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                 33210326                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             1242319                       # Number of function calls committed.
+system.cpu3.commit.int_insts                 33267854                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             1244626                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu        25404774     66.75%     66.75% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult          29228      0.08%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc         2304      0.01%     66.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead        6822126     17.92%     84.75% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite       5802496     15.25%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu        25422255     66.69%     66.69% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult          29353      0.08%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.76% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc         2310      0.01%     66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead        6831824     17.92%     84.69% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite       5836650     15.31%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total         38060928                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events               945300                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                    90970787                       # The number of ROB reads
-system.cpu3.rob.rob_writes                   90587481                       # The number of ROB writes
-system.cpu3.timesIdled                         219785                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                        1355018                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                  5161755203                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                   31172252                       # Number of Instructions Simulated
-system.cpu3.committedOps                     38023801                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.783272                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.783272                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.560767                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.560767                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                45496208                       # number of integer regfile reads
-system.cpu3.int_regfile_writes               25431004                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                    14216                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                   12004                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                146184815                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                16067235                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               75058867                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                353976                       # number of misc regfile writes
+system.cpu3.commit.op_class_0::total         38122392                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events               955384                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                    90746167                       # The number of ROB reads
+system.cpu3.rob.rob_writes                   90074886                       # The number of ROB writes
+system.cpu3.timesIdled                         219461                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                        1352392                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                  5161729815                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                   31200076                       # Number of Instructions Simulated
+system.cpu3.committedOps                     38084963                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.781197                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.781197                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.561420                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.561420                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                45423777                       # number of integer regfile reads
+system.cpu3.int_regfile_writes               25365434                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                    14212                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                   12005                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                145868338                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                16008509                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads               75068874                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                356547                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30152                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30152                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
@@ -2102,7 +2100,7 @@ system.iobus.pkt_size_system.bridge.master::total       159093
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320992                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2320992                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480085                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             23971000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             24223000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2118,31 +2116,31 @@ system.iobus.reqLayer19.occupancy                2000                       # La
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             3350000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             3354000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy               85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy               88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            18885000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            18813000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               75000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy            72461073                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy            72446830                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            50561000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            50749000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            14254000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                1.001949                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.001763                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         248566131009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.001949                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062622                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062622                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         248545825009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.001763                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062610                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062610                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2158,8 +2156,8 @@ system.iocache.overall_misses::realview.ide          220                       #
 system.iocache.overall_misses::total              220                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     16046914                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     16046914                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   1649931159                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   1649931159                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   1650232916                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   1650232916                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ide     16046914                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     16046914                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ide     16046914                       # number of overall miss cycles
@@ -2182,8 +2180,8 @@ system.iocache.overall_miss_rate::realview.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 72940.518182                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45548.011236                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 45548.011236                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45556.341542                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 45556.341542                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ide 72940.518182                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 72940.518182                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ide 72940.518182                       # average overall miss latency
@@ -2208,8 +2206,8 @@ system.iocache.overall_mshr_misses::realview.ide          135
 system.iocache.overall_mshr_misses::total          135                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide      9296914                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total      9296914                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide    950731159                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total    950731159                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide    951032916                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total    951032916                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ide      9296914                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total      9296914                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ide      9296914                       # number of overall MSHR miss cycles
@@ -2224,390 +2222,376 @@ system.iocache.overall_mshr_miss_rate::realview.ide     0.613636
 system.iocache.overall_mshr_miss_rate::total     0.613636                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67987.068006                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67987.068006                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68008.646739                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68008.646739                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 68866.029630                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 68866.029630                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   101236                       # number of replacements
-system.l2c.tags.tagsinuse                65107.326464                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5169585                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   166405                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    31.066284                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              79214835000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   49083.542399                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.902823                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                   101351                       # number of replacements
+system.l2c.tags.tagsinuse                65107.437503                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5159062                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   166512                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    30.983124                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              79184308500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   48838.010407                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.902867                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4686.027695                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     1888.757570                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      762.533127                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      823.027459                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    21.612176                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.006778                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2605.585835                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      671.628280                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    48.673794                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     2617.148912                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     1895.879520                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.748955                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     4685.718264                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     1889.035593                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      795.990767                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      850.885557                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    18.207428                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2675.377352                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data      739.764762                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker    57.652959                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst     2556.556001                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data     1997.335453                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.745209                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000044                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.071503                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.028820                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.011635                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.012558                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000330                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.039758                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.010248                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.000743                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.039935                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.028929                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.993459                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           52                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65117                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           52                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2279                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8100                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54698                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000793                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.993607                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 45651328                       # Number of tag accesses
-system.l2c.tags.data_accesses                45651328                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4883                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         2386                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         1737                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker          894                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        13247                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker         1208                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker        21839                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker         4721                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  50915                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          692577                       # number of Writeback hits
-system.l2c.Writeback_hits::total               692577                       # number of Writeback hits
+system.l2c.tags.occ_percent::cpu0.inst       0.071498                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.028824                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.012146                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.012983                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000278                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.040823                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.011288                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.dtb.walker     0.000880                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.039010                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.030477                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.993461                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           60                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65101                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           60                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2291                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8090                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54680                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000916                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.993362                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 45578118                       # Number of tag accesses
+system.l2c.tags.data_accesses                45578118                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4244                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         2185                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         1248                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker          674                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        13130                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker         1192                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.dtb.walker        20158                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.itb.walker         4312                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  47143                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          690898                       # number of Writeback hits
+system.l2c.Writeback_hits::total               690898                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data              11                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               6                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu2.data               7                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data              25                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  49                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu3.data            10                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            67466                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            21347                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            26309                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data            43752                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               158874                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        736958                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        209010                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        471846                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst        538057                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1955871                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       224298                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        66271                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data        89985                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data       142818                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           523372                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4883                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          2386                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              736958                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              291764                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          1737                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker           894                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              209010                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               87618                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         13247                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker          1208                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              471846                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              116294                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker         21839                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker          4721                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst              538057                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data              186570                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2689032                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4883                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         2386                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             736958                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             291764                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         1737                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker          894                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             209010                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              87618                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        13247                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker         1208                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             471846                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             116294                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker        21839                       # number of overall hits
-system.l2c.overall_hits::cpu3.itb.walker         4721                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst             538057                       # number of overall hits
-system.l2c.overall_hits::cpu3.data             186570                       # number of overall hits
-system.l2c.overall_hits::total                2689032                       # number of overall hits
+system.l2c.UpgradeReq_hits::cpu3.data              27                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  51                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu3.data            20                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                20                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            67048                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            20977                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            26358                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3.data            44381                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               158764                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        736580                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        206983                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst        474034                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst        536634                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1954231                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       223898                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        65729                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data        89672                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data       143158                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           522457                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4244                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          2185                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              736580                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              290946                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          1248                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker           674                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              206983                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               86706                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         13130                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker          1192                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              474034                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              116030                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.dtb.walker         20158                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.itb.walker          4312                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst              536634                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data              187539                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2682595                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4244                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         2185                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             736580                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             290946                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         1248                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker          674                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             206983                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              86706                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        13130                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker         1192                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             474034                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             116030                       # number of overall hits
+system.l2c.overall_hits::cpu3.dtb.walker        20158                       # number of overall hits
+system.l2c.overall_hits::cpu3.itb.walker         4312                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst             536634                       # number of overall hits
+system.l2c.overall_hits::cpu3.data             187539                       # number of overall hits
+system.l2c.overall_hits::total                2682595                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           31                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker           66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  104                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1067                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           483                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           474                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data           722                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2746                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu3.data           11                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total              11                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          43380                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          11817                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          30097                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data          52401                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             137695                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         7833                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1891                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         5849                       # number of ReadCleanReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker           26                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.dtb.walker           75                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  107                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1079                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           458                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data           475                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data           741                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2753                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu3.data            7                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               7                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          43127                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          11857                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          30296                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data          52403                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             137683                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst         7753                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         1908                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst         5933                       # number of ReadCleanReq misses
 system.l2c.ReadCleanReq_misses::cpu3.inst         5574                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           21147                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         5096                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         2411                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data         1751                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data         4833                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total          14091                       # number of ReadSharedReq misses
+system.l2c.ReadCleanReq_misses::total           21168                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         4938                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         2417                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data         1817                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data         5008                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total          14180                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7833                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             48476                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1891                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             14228                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           31                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              5849                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             31848                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.dtb.walker           66                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7753                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             48065                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1908                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             14274                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker           26                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              5933                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             32113                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.dtb.walker           75                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.inst              5574                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data             57234                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                173037                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data             57411                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                173138                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            5                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7833                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            48476                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1891                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            14228                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           31                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             5849                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            31848                       # number of overall misses
-system.l2c.overall_misses::cpu3.dtb.walker           66                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7753                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            48065                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1908                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            14274                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker           26                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             5933                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            32113                       # number of overall misses
+system.l2c.overall_misses::cpu3.dtb.walker           75                       # number of overall misses
 system.l2c.overall_misses::cpu3.inst             5574                       # number of overall misses
-system.l2c.overall_misses::cpu3.data            57234                       # number of overall misses
-system.l2c.overall_misses::total               173037                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2620000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker        83000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.dtb.walker      5711000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total        8414000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data        61500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data       184500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3.data       275500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       521500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu3.data       256000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       256000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    919344500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2291625500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data   4294703000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7505673000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    154460000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    476710500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst    459124500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1090295000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    197936000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data    143845500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data    418005000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total    759786500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    154460000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1117280500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      2620000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker        83000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    476710500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   2435471000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.dtb.walker      5711000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst    459124500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data   4712708000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      9364168500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    154460000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1117280500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      2620000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker        83000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    476710500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   2435471000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.dtb.walker      5711000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst    459124500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data   4712708000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     9364168500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         4888                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         2387                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         1737                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker          894                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        13278                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker         1209                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker        21905                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.itb.walker         4721                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              51019                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       692577                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           692577                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1078                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          489                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          481                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data          747                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2795                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu3.data           21                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            21                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       110846                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        33164                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        56406                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data        96153                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296569                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       744791                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       210901                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst       477695                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst       543631                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1977018                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       229394                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        68682                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data        91736                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data       147651                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       537463                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         4888                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         2387                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          744791                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          340240                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         1737                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker          894                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          210901                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          101846                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        13278                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker         1209                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          477695                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          148142                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker        21905                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker         4721                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst          543631                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data          243804                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2862069                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         4888                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         2387                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         744791                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         340240                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         1737                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker          894                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         210901                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         101846                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        13278                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker         1209                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         477695                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         148142                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker        21905                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker         4721                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst         543631                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data         243804                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2862069                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001023                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000419                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002335                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000827                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003013                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.002038                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989796                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.987730                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.985447                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.966533                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.982469                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.523810                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.523810                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.391354                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.356320                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.533578                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.544975                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.464293                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010517                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008966                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.012244                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.010253                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.010696                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.022215                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.035104                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019087                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.032733                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.026218                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001023                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000419                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.010517                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.142476                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.008966                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.139701                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002335                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.000827                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.012244                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.214983                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003013                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.010253                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.234754                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.060459                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001023                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000419                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.010517                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.142476                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008966                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.139701                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002335                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.000827                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.012244                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.214983                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003013                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.010253                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.234754                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.060459                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84516.129032                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        83000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 86530.303030                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 80903.846154                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   127.329193                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   389.240506                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data   381.578947                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   189.912600                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 23272.727273                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 23272.727273                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77798.468308                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 76141.326378                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81958.416824                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 54509.408475                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81681.649921                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 81502.906480                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 82368.945102                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 51557.904194                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82097.055164                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82150.485437                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 86489.757914                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 53919.984387                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81681.649921                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 78526.883610                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84516.129032                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 81502.906480                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 76471.709370                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 86530.303030                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 82368.945102                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 82341.056016                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 54116.567555                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81681.649921                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 78526.883610                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84516.129032                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 81502.906480                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 76471.709370                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 86530.303030                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 82368.945102                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 82341.056016                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 54116.567555                       # average overall miss latency
+system.l2c.overall_misses::cpu3.data            57411                       # number of overall misses
+system.l2c.overall_misses::total               173138                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2345500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.dtb.walker      6845500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total        9191000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data        31000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       154500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data       277000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       462500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu3.data       223500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       223500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    915104500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   2308530500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data   4283890000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7507525000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    154889000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst    480391500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst    457984000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   1093264500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    194506500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data    149586500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data    433861500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total    777954500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    154889000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1109611000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker      2345500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    480391500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   2458117000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.dtb.walker      6845500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst    457984000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data   4717751500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9387935000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    154889000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1109611000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker      2345500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    480391500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   2458117000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.dtb.walker      6845500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst    457984000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data   4717751500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9387935000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4249                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         2186                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         1248                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker          674                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        13156                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker         1192                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker        20233                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker         4312                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              47250                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       690898                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           690898                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1090                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          464                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          482                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data          768                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2804                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu3.data           27                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            27                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       110175                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        32834                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        56654                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data        96784                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           296447                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       744333                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       208891                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst       479967                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst       542208                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1975399                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       228836                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        68146                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data        91489                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data       148166                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       536637                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4249                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         2186                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          744333                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          339011                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         1248                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker          674                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          208891                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          100980                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        13156                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker         1192                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          479967                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          148143                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker        20233                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker         4312                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst          542208                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data          244950                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2855733                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4249                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         2186                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         744333                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         339011                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         1248                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker          674                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         208891                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         100980                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        13156                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker         1192                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         479967                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         148143                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker        20233                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker         4312                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst         542208                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data         244950                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2855733                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001177                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.001976                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003707                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.002265                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989908                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.987069                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.985477                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.964844                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.981812                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.259259                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.259259                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.391441                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.361120                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.534755                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.541443                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.464444                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010416                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.009134                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.012361                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.010280                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010716                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.021579                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.035468                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019860                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.033800                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.026424                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001177                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010416                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.141780                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.009134                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.141355                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.001976                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.012361                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.216770                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003707                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.010280                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.234378                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.060628                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001177                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.010416                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.141780                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.009134                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.141355                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.001976                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.012361                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.216770                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003707                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.010280                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.234378                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.060628                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 90211.538462                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 91273.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 85897.196262                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data    67.685590                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   325.263158                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data   373.819163                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   167.998547                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 31928.571429                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 31928.571429                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77178.417812                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 76199.184711                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81748.945671                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 54527.610526                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81178.721174                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 80969.408394                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 82164.334410                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 51647.037982                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80474.348366                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82326.086957                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 86633.686102                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 54862.799718                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 81178.721174                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 77736.513941                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 90211.538462                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 80969.408394                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 76545.853704                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 91273.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 82164.334410                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 82175.044852                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 54222.267786                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 81178.721174                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 77736.513941                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 90211.538462                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 80969.408394                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 76545.853704                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 91273.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 82164.334410                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 82175.044852                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 54222.267786                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2616,280 +2600,268 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               92684                       # number of writebacks
-system.l2c.writebacks::total                    92684                       # number of writebacks
+system.l2c.writebacks::writebacks               92936                       # number of writebacks
+system.l2c.writebacks::total                    92936                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            3                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            4                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data           25                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data           42                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            6                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data           28                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data           39                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::total           67                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data             25                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data             42                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 74                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data             28                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              6                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data             39                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 76                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data            25                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data            42                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                74                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           31                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker           66                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total              98                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          483                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          474                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data          722                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1679                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu3.data           11                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total           11                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        11817                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        30097                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data        52401                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         94315                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1891                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5846                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst         5570                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        13307                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2411                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data         1726                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data         4791                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total         8928                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1891                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        14228                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           31                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         5846                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        31823                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker           66                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst         5570                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data        57192                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           116648                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1891                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        14228                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           31                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         5846                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        31823                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker           66                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst         5570                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data        57192                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          116648                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         4098                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6759                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data         7555                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        18412                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3203                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         5165                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data         5997                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        14365                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         7301                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data        11924                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data        13552                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        32777                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2310000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        73000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      5051000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total      7434000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     10024500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      9843000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     14997500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     34865000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       331000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       331000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    801174500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1990655500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   3770693000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   6562523000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    135550000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    418188000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    403211000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    956949000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    173826000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    124796000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    367209500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total    665831500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    135550000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    975000500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2310000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        73000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    418188000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2115451500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      5051000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst    403211000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data   4137902500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   8192737500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    135550000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    975000500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2310000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        73000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    418188000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2115451500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      5051000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst    403211000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data   4137902500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   8192737500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    655228000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1232598000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1434609000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3322435000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    506558500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    922952500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1130501000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2560012000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1161786500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2155550500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2565110000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5882447000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002335                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000827                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003013                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.001921                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.987730                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.985447                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.966533                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.600716                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.523810                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.523810                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.356320                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.533578                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.544975                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.318020                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.008966                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.012238                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.010246                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006731                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035104                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.018815                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.032448                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016611                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008966                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.139701                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002335                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000827                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.012238                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.214814                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003013                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010246                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.234582                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.040757                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008966                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.139701                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002335                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000827                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.012238                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.214814                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003013                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010246                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.234582                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.040757                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 75857.142857                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.658385                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20765.822785                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20772.160665                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20765.336510                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 30090.909091                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 30090.909091                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67798.468308                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66141.326378                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71958.416824                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 69580.904416                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71681.649921                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 71534.040369                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72389.766607                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71913.203577                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72097.055164                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72303.592121                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76645.689835                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74577.900986                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71681.649921                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68526.883610                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71534.040369                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66475.552274                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72389.766607                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72351.071828                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70234.701838                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71681.649921                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68526.883610                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71534.040369                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66475.552274                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72389.766607                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72351.071828                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70234.701838                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159889.702294                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182363.959166                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189888.682991                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180449.435151                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158151.264440                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178693.610842                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188511.088878                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178211.764706                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159127.037392                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 180774.111037                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 189279.073200                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 179468.743326                       # average overall mshr uncacheable latency
+system.l2c.overall_mshr_hits::cpu2.data            28                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             6                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.data            39                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                76                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           26                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker           75                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total             101                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          458                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          475                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data          741                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1674                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            7                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            7                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        11857                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        30296                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data        52403                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         94556                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1908                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5930                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst         5568                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        13406                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2417                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data         1789                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data         4969                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total         9175                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1908                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        14274                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           26                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         5930                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        32085                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.dtb.walker           75                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst         5568                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data        57372                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           117238                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1908                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        14274                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           26                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         5930                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        32085                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.dtb.walker           75                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst         5568                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data        57372                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          117238                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         4191                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6644                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3.data         7640                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        18475                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3264                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         5115                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6049                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        14428                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         7455                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data        11759                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3.data        13689                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        32903                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2085500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      6095500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total      8181000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      9509000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      9865000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     15375500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     34749500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       246000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       246000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    796534500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2005570500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   3759860000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   6561965000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    135809000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    421029000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    401833000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    958671000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    170336500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    129910000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    381246000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    681492500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    135809000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    966871000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2085500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    421029000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2135480500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      6095500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst    401833000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data   4141106000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8210309500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    135809000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    966871000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2085500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    421029000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2135480500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      6095500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst    401833000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data   4141106000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8210309500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    676680000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1207720500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1453053500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3337454000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    521354500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    905601000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1147910000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2574865500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1198034500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2113321500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2600963500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5912319500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.001976                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003707                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.002138                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.987069                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.985477                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.964844                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.597004                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.259259                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.259259                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.361120                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.534755                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.541443                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.318964                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.009134                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.012355                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.010269                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006786                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035468                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019554                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.033537                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.017097                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009134                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.141355                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.001976                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.012355                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.216581                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003707                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010269                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.234219                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.041054                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009134                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.141355                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.001976                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.012355                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.216581                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003707                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010269                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.234219                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.041054                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total        81000                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.008734                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20768.421053                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20749.662618                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.363202                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 35142.857143                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35142.857143                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67178.417812                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66199.184711                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71748.945671                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 69397.658530                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71178.721174                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 70999.831366                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72168.283046                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71510.592272                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70474.348366                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72615.986585                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76724.894345                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74277.111717                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.721174                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67736.513941                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70999.831366                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66556.973664                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72168.283046                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72179.913547                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 70031.128985                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.721174                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67736.513941                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70999.831366                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66556.973664                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72168.283046                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72179.913547                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 70031.128985                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161460.272011                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181776.113787                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 190190.248691                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180647.036536                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159728.707108                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 177048.093842                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 189768.556786                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178463.092598                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160702.146211                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 179719.491453                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 190003.908247                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 179689.374829                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
-system.membus.trans_dist::ReadResp              75602                       # Transaction distribution
+system.membus.trans_dist::ReadResp              75713                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27565                       # Transaction distribution
-system.membus.trans_dist::Writeback            128874                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8637                       # Transaction distribution
+system.membus.trans_dist::Writeback            129126                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8500                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4529                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             11                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4540                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            135912                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135912                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         35488                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              7                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4536                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            135907                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135907                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         35599                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105436                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2006                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       480381                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       587833                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       480701                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       588153                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109028                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       109028                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 696861                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 697181                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159093                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16930428                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17093553                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16953404                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17116529                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2321600                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2321600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19415153                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              336                       # Total snoops (count)
-system.membus.snoop_fanout::samples            417491                       # Request fanout histogram
+system.membus.pkt_size::total                19438129                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              335                       # Total snoops (count)
+system.membus.snoop_fanout::samples            417709                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  417491    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  417709    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              417491                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            56695500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              417709                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            57005500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              701000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              697500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           501323202                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           504943941                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          664397755                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          667734518                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           25144064                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           25122086                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2922,63 +2894,63 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq             112246                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2626935                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             111495                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2623751                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           762585                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2095941                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2795                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            21                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2816                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296569                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296569                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1977107                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       537598                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           761523                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2094648                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2804                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            27                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2831                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296447                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296447                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1975500                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       536772                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        13984                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5926014                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2620361                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26770                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       102262                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8675407                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    126565496                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97893497                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        45160                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       182440                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224686593                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          127382                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5875721                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.031320                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.174182                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5920920                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2617534                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26086                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        99400                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8663940                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    126461880                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97725369                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42848                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       173572                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              224403669                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          129912                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5870347                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.031302                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.174132                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                5691691     96.87%     96.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 184030      3.13%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                5686595     96.87%     96.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 183752      3.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5875721                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2190361997                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5870347                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2188688500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           178500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1848817301                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1847107273                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         767245312                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         767774788                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11020987                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          10846487                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          48078267                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          47373752                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 07cc062ab..c1c48178d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -204,7 +204,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -587,7 +587,7 @@ opLat=3
 pipelined=false
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1261,7 +1261,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1296,7 +1296,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1711,9 +1711,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index b551fcaf9..ced0bcc1f 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -26,7 +26,6 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
@@ -34,18 +33,18 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
 warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
-warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[0]
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
-warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]
+warn: CP14 unimplemented crn[4], opc1[0], crm[12], opc2[1]
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
 warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
+warn: CP14 unimplemented crn[3], opc1[5], crm[12], opc2[1]
 warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
 warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
-warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[2]
+warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
 warn: 	instruction 'mcr bpiall' unimplemented
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -59,7 +58,3 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index b9bed144d..8b2102f6a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.804297                       # Number of seconds simulated
-sim_ticks                                2804296829000                       # Number of ticks simulated
-final_tick                               2804296829000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.804117                       # Number of seconds simulated
+sim_ticks                                2804116777000                       # Number of ticks simulated
+final_tick                               2804116777000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111219                       # Simulator instruction rate (inst/s)
-host_op_rate                                   134991                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2666745991                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 581460                       # Number of bytes of host memory used
-host_seconds                                  1051.58                       # Real time elapsed on the host
-sim_insts                                   116955586                       # Number of instructions simulated
-sim_ops                                     141953418                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  79056                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95953                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1895501031                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 624156                       # Number of bytes of host memory used
+host_seconds                                  1479.35                       # Real time elapsed on the host
+sim_insts                                   116952036                       # Number of instructions simulated
+sim_ops                                     141948815                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker         4480                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           694336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4949664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           683520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4874120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           698944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4896096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           676224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4916296                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11211752                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       694336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       683520                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1377856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8431616                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11197544                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       698944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       676224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1375168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8445824                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8449140                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8463348                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker           70                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10849                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             77857                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           72                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10680                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             76160                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10921                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             77020                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           70                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10566                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             76819                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175704                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131744                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175482                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131966                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136125                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               136347                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker          1598                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              247597                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1765029                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1643                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              243740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1738090                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              249256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1746039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1598                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              241154                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1753242                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3998062                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         247597                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         243740                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             491337                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3006677                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6246                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3993252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         249256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         241154                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             490410                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3011937                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6247                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3012926                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3006677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3018187                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3011937                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker         1598                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             247597                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1771275                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1643                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             243740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1738093                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             249256                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1752285                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1598                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             241154                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1753245                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7010988                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175705                       # Number of read requests accepted
-system.physmem.writeReqs                       136125                       # Number of write requests accepted
-system.physmem.readBursts                      175705                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     136125                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11235200                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9920                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8462208                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11211816                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8449140                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      155                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          40824                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11564                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11591                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11445                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11009                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11560                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11263                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12057                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11817                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10124                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10528                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10442                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9442                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10178                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11257                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10875                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10398                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8593                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8838                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8913                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8377                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8541                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8325                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9064                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8810                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7663                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7908                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7816                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7099                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7741                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8641                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8211                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7682                       # Per bank write bursts
+system.physmem.bw_total::total                7011438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175483                       # Number of read requests accepted
+system.physmem.writeReqs                       136347                       # Number of write requests accepted
+system.physmem.readBursts                      175483                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136347                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11221120                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9728                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8475904                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11197608                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8463348                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      152                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3889                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          40841                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11242                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11247                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11589                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11122                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11335                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11409                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11590                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11844                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10538                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10661                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10504                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9563                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10483                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10932                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10755                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10516                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8424                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8579                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8987                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8481                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8341                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8592                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8708                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8869                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8028                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8030                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7878                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7235                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7993                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8331                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8147                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7813                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2804296665000                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2804116613000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  175149                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  174927                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131744                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    103856                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      8514                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1726                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131966                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    103653                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61646                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      8310                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1700                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -161,182 +161,175 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       109                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       101                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       85                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       84                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6904                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2079                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6688                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9024                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8820                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       34                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       59                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65040                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.849692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.291679                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.303136                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24533     37.72%     37.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15784     24.27%     61.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6682     10.27%     72.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3695      5.68%     77.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2905      4.47%     82.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1458      2.24%     84.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1174      1.81%     86.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1054      1.62%     88.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7755     11.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65040                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6683                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.267993                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      478.078944                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6681     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.152399                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     178.671137                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.237503                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24321     37.43%     37.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15991     24.61%     62.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6608     10.17%     72.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3730      5.74%     77.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2732      4.20%     82.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1666      2.56%     84.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1104      1.70%     86.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1133      1.74%     88.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7689     11.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64974                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6726                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.057835                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      476.710834                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6724     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6683                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6683                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.784827                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.157430                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.794900                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                18      0.27%      0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 6      0.09%      0.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                6      0.09%      0.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              12      0.18%      0.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5769     86.32%     86.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             120      1.80%     88.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             172      2.57%     91.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              80      1.20%     92.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              71      1.06%     93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             155      2.32%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              21      0.31%     96.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.21%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.16%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               6      0.09%     96.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.12%     96.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.03%     96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             156      2.33%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               5      0.07%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.04%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.04%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.06%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.01%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.04%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            14      0.21%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.04%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6683                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2675585250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5967147750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    877750000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15241.16                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33991.16                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.rdPerTurnAround::total            6726                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6726                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.690158                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.212427                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.515810                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                16      0.24%      0.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 4      0.06%      0.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                7      0.10%      0.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              10      0.15%      0.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5748     85.46%     86.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             152      2.26%     88.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             195      2.90%     91.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              73      1.09%     92.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              81      1.20%     93.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             162      2.41%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              28      0.42%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.16%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              17      0.25%     96.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.15%     96.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.12%     97.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             154      2.29%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.07%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               6      0.09%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.04%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.16%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6726                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2656155250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5943592750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    876650000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15149.38                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  33899.27                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.00                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.99                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.02                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.63                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145103                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97628                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.66                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.83                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8993030.39                       # Average gap between requests
-system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  260993880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  142407375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 719979000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                450107280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           183162969600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            78025608810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1614134111250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1876896177195                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.293165                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2685155496500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     93641600000                       # Time in different power states
+system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        10.62                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144959                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97833                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.68                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.86                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8992452.98                       # Average gap between requests
+system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  259035840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  141339000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 712748400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                446996880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           183151272720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            77780216115                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1614241917750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1876733526705                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.277905                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2685339699500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     93635360000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     25499722000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     25141656750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  230708520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  125882625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 649303200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                406691280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           183162969600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            76764954915                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1615239948000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1876580458140                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.180581                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2687003305500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     93641600000                       # Time in different power states
+system.physmem_1.actEnergy                  232167600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  126678750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 654825600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                411188400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           183151272720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            76668937560                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1615216723500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1876461794130                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.181000                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2686967028000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     93635360000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23651154500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23514328250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
@@ -356,15 +349,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26812041                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13971263                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           545954                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            16789639                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12578074                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26869227                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13991642                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           524467                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            16420293                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               12603750                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            74.915691                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6641912                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             29629                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            76.757157                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6640393                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             27621                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -395,93 +388,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    60251                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               60251                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        19166                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14911                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        26174                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        34077                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   605.672448                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3875.346595                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383        33739     99.01%     99.01% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767          267      0.78%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151           41      0.12%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535           11      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-147455            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        34077                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        12355                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12355.685957                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10118.887695                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7958.316755                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-8191         4001     32.38%     32.38% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::8192-16383         5682     45.99%     78.37% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2378     19.25%     97.62% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::24576-32767           80      0.65%     98.27% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-40959           88      0.71%     98.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::40960-49151          103      0.83%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-57343            4      0.03%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::73728-81919            1      0.01%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-90111            7      0.06%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::90112-98303            8      0.06%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::106496-114687            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        12355                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  80764749336                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.624014                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.503698                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  80684502836     99.90%     99.90% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     56898500      0.07%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5     12104000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      4341500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      2388000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1576500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       755000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      1408500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       265500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19       266500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21        51500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23        38500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25        30000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27        29500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29        26000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31        67000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  80764749336                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3631     69.79%     69.79% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1572     30.21%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5203                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        60251                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    57399                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               57399                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17473                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14797                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        25129                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        32270                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   687.186241                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  4502.840845                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383        31894     98.83%     98.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767          274      0.85%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151           54      0.17%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919           17      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-114687            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-147455            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        32270                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12902                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12660.750271                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10400.452854                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  8033.389954                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         9915     76.85%     76.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         2761     21.40%     98.25% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151          203      1.57%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535            6      0.05%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-81919            2      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303           14      0.11%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        12902                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  76391677040                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.743538                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.460978                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  76311291040     99.89%     99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     56342500      0.07%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     12108500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      4568500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2307500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1375000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       973000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      1821000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       435000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       132000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21        55000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        49500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       144000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29         8500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31        51500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  76391677040                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3747     70.16%     70.16% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1594     29.84%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5341                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        57399                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        60251                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5203                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        57399                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5341                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5203                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        65454                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5341                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        62740                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14022096                       # DTB read hits
-system.cpu0.dtb.read_misses                     51656                       # DTB read misses
-system.cpu0.dtb.write_hits                   10360983                       # DTB write hits
-system.cpu0.dtb.write_misses                     8595                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     463                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    14047287                       # DTB read hits
+system.cpu0.dtb.read_misses                     49327                       # DTB read misses
+system.cpu0.dtb.write_hits                   10317828                       # DTB write hits
+system.cpu0.dtb.write_misses                     8072                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     482                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3475                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      881                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1392                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3506                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      817                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1439                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      599                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14073752                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10369578                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      656                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14096614                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10325900                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24383079                       # DTB hits
-system.cpu0.dtb.misses                          60251                       # DTB misses
-system.cpu0.dtb.accesses                     24443330                       # DTB accesses
+system.cpu0.dtb.hits                         24365115                       # DTB hits
+system.cpu0.dtb.misses                          57399                       # DTB misses
+system.cpu0.dtb.accesses                     24422514                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -511,806 +498,804 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     8217                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                8217                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2960                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5117                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          140                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         8077                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1443.543395                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  6102.235478                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-8191         7600     94.09%     94.09% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-16383          232      2.87%     96.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-24575          133      1.65%     98.61% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-32767           50      0.62%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-40959           22      0.27%     99.50% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-49151           13      0.16%     99.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::57344-65535            2      0.02%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-73727            8      0.10%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-90111            4      0.05%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         8077                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2488                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13472.467846                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11168.518762                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  7984.929111                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          793     31.87%     31.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383          981     39.43%     71.30% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          648     26.05%     97.35% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           24      0.96%     98.31% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           15      0.60%     98.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151           24      0.96%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     7905                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                7905                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2649                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5113                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          143                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         7762                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1462.316413                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  6006.318105                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         7298     94.02%     94.02% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          191      2.46%     96.48% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575          163      2.10%     98.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           55      0.71%     99.29% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959           14      0.18%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151           16      0.21%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535            7      0.09%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727            3      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         7762                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2523                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13374.950456                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11026.619167                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  8136.408829                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          825     32.70%     32.70% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383          999     39.60%     72.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          627     24.85%     97.15% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           25      0.99%     98.14% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           16      0.63%     98.77% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151           27      1.07%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::57344-65535            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::65536-73727            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2488                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  37746197376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.883119                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.321811                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     4416616428     11.70%     11.70% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    33326087448     88.29%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        2489000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         727000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         244500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          33000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  37746197376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1794     76.41%     76.41% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          554     23.59%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2348                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         2523                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  33438392080                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.922681                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.267784                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     2590170000      7.75%      7.75% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    30844665580     92.24%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        2600500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         732500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         223500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  33438392080                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1818     76.39%     76.39% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          562     23.61%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2380                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8217                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8217                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7905                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7905                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2348                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2348                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        10565                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    20173848                       # ITB inst hits
-system.cpu0.itb.inst_misses                      8217                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2380                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2380                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        10285                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20120654                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7905                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     463                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     482                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2291                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2326                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                     1412                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20182065                       # ITB inst accesses
-system.cpu0.itb.hits                         20173848                       # DTB hits
-system.cpu0.itb.misses                           8217                       # DTB misses
-system.cpu0.itb.accesses                     20182065                       # DTB accesses
-system.cpu0.numCycles                       106431987                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20128559                       # ITB inst accesses
+system.cpu0.itb.hits                         20120654                       # DTB hits
+system.cpu0.itb.misses                           7905                       # DTB misses
+system.cpu0.itb.accesses                     20128559                       # DTB accesses
+system.cpu0.numCycles                       106084335                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39926124                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     104046311                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26812041                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19219986                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     61721491                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3201846                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    134355                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                4118                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              472                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       336728                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       143479                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          355                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20172603                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               372165                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3674                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         103868008                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.205189                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.307808                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39806494                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     103893687                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26869227                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19244143                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     61681241                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3154924                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    126092                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4609                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              416                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       201724                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       122006                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          398                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20119405                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               359114                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3525                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         103520405                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.205881                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.305845                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                75224337     72.42%     72.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3826153      3.68%     76.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2403715      2.31%     78.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 7967440      7.67%     86.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1659017      1.60%     87.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1036461      1.00%     88.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6057785      5.83%     94.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1065173      1.03%     95.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4627927      4.46%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                74908218     72.36%     72.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3833241      3.70%     76.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2379626      2.30%     78.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 8018936      7.75%     86.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1633248      1.58%     87.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1022119      0.99%     88.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6115753      5.91%     94.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1028201      0.99%     95.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4581063      4.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           103868008                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.251917                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.977585                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                27603064                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             57749227                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15599106                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1464170                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1452197                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1874763                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               150759                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              86325331                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               486551                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1452197                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                28440398                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6572412                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      43697521                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16217184                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              7488032                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              82550644                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 3098                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1081958                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                289974                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               5413982                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           85027824                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            380373358                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        92135642                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             6326                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             71200016                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                13827808                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1531327                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1437175                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8438984                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14879838                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11477452                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1996170                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2776563                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  79349721                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1058033                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 75951748                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            96660                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       11354988                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     24738171                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        114625                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    103868008                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.731233                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.423636                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           103520405                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.253282                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.979350                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                27459073                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             57640843                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15538578                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1452555                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1429102                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1871474                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               150372                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              86076544                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               485871                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1429102                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                28294007                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6612104                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      43619414                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16146294                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7419215                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              82346799                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 3179                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1065744                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                299526                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               5341738                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           84890721                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            379205899                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        91831678                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             6335                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             71376559                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                13514162                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1526597                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1432651                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8443957                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14885891                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11404400                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1982860                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2750757                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  79215613                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1056336                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 75904646                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            90770                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       11089379                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     24203913                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        112312                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    103520405                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.733234                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.426738                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           73542868     70.80%     70.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10072511      9.70%     80.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7759579      7.47%     87.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6464332      6.22%     94.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2333365      2.25%     96.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1472075      1.42%     97.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1515581      1.46%     99.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             481814      0.46%     99.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             225883      0.22%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           73282727     70.79%     70.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10008412      9.67%     80.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7714570      7.45%     87.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6465771      6.25%     94.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2339617      2.26%     96.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1485866      1.44%     97.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1511901      1.46%     99.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             481751      0.47%     99.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             229790      0.22%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      103868008                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      103520405                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 101947      9.17%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     2      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                527360     47.45%     56.63% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               481989     43.37%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 105175      9.45%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                531702     47.76%     57.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               476475     42.80%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2185      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             50526992     66.53%     66.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57691      0.08%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4308      0.01%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14430381     19.00%     85.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           10930190     14.39%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             50511411     66.55%     66.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57825      0.08%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              5      0.00%     66.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4290      0.01%     66.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14447360     19.03%     85.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           10881568     14.34%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              75951748                       # Type of FU issued
-system.cpu0.iq.rate                          0.713618                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1111298                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.014632                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         256965506                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         91807957                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     73625831                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              13956                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              7486                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         6230                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              77053395                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   7466                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          363562                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              75904646                       # Type of FU issued
+system.cpu0.iq.rate                          0.715512                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1113353                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014668                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         256519810                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         91406915                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     73615254                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              14010                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              7412                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         6126                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              77008290                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7524                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          368125                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2216786                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2550                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        53728                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1148638                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2165393                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2440                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        54160                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1099887                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       206531                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked        94919                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       208534                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked        95734                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1452197                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5712747                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               651844                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           80559572                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           134213                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14879838                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11477452                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            551306                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 44233                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               595893                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         53728                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        250776                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       220293                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              471069                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             75340518                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14186156                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           551092                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1429102                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5759594                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               639314                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           80435080                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           122511                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14885891                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11404400                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            549713                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 48457                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               578413                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         54160                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        234602                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       214611                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              449213                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             75318249                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14211760                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           529106                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       151818                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    25009470                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14210768                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10823314                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.707875                       # Inst execution rate
-system.cpu0.iew.wb_sent                      74794094                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     73632061                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38328256                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 66642343                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       163131                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    24990941                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14215836                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10779181                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.709985                       # Inst execution rate
+system.cpu0.iew.wb_sent                      74778323                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     73621380                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 38389560                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 66627447                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.691823                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575134                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.693989                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.576182                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       11328784                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         943408                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           397191                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    101330688                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.682350                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.572509                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       11066735                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         944024                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           376070                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    101026787                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.685770                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.579563                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     74383354     73.41%     73.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12129402     11.97%     85.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6135914      6.06%     91.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2613445      2.58%     94.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1268685      1.25%     95.26% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       826588      0.82%     96.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1844857      1.82%     97.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       402953      0.40%     98.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1725490      1.70%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     74129277     73.38%     73.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12088684     11.97%     85.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6100635      6.04%     91.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2597407      2.57%     93.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1266923      1.25%     95.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       835295      0.83%     96.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1855576      1.84%     97.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       402562      0.40%     98.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1750428      1.73%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    101330688                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            56867581                       # Number of instructions committed
-system.cpu0.commit.committedOps              69142978                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    101026787                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            57027520                       # Number of instructions committed
+system.cpu0.commit.committedOps              69281156                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      22991866                       # Number of memory references committed
-system.cpu0.commit.loads                     12663052                       # Number of loads committed
-system.cpu0.commit.membars                     379145                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13422378                       # Number of branches committed
-system.cpu0.commit.fp_insts                      6158                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 60521589                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2622248                       # Number of function calls committed.
+system.cpu0.commit.refs                      23025011                       # Number of memory references committed
+system.cpu0.commit.loads                     12720498                       # Number of loads committed
+system.cpu0.commit.membars                     379883                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13454174                       # Number of branches committed
+system.cpu0.commit.fp_insts                      6046                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 60620890                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2622879                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        46090829     66.66%     66.66% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55975      0.08%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4308      0.01%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12663052     18.31%     85.06% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10328814     14.94%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        46195742     66.68%     66.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          56117      0.08%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4286      0.01%     66.77% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.77% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.77% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.77% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12720498     18.36%     85.13% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10304513     14.87%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         69142978                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1725490                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   167648310                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  163485257                       # The number of ROB writes
-system.cpu0.timesIdled                         393439                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        2563979                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2956083785                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   56777369                       # Number of Instructions Simulated
-system.cpu0.committedOps                     69052766                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.874549                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.874549                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.533462                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.533462                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                82027611                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               46869593                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16807                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13164                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                266520742                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27747679                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              144321385                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                724502                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           852950                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.982213                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42504025                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           853462                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.801895                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total         69281156                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1750428                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   167227208                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  163193530                       # The number of ROB writes
+system.cpu0.timesIdled                         392212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        2563930                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2956294180                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   56928934                       # Number of Instructions Simulated
+system.cpu0.committedOps                     69182570                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.863452                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.863452                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.536638                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.536638                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                81967291                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               46848639                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16893                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13046                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                266506484                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27807772                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              144531551                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                724861                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           854304                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.982090                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42365382                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           854816                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.560820                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        105251500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   187.204537                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   324.777676                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.365634                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.634331                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   186.651423                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   325.330668                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.364554                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.635411                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          185                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189817658                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189817658                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12454816                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12866965                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25321781                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7691483                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      8218685                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15910168                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178893                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       183845                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       362738                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209855                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236893                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446748                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216102                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243311                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459413                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20146299                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     21085650                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41231949                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20325192                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21269495                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41594687                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       412638                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       421416                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       834054                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1958462                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1736177                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3694639                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        85616                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        97979                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       183595                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13773                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14074                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27847                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           27                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           34                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           61                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2371100                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2157593                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4528693                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2456716                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2255572                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4712288                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6076761000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6454165500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  12530926500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  84857330299                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  79343865125                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 164201195424                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    181836500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    208543500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    390380000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       611500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       544500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      1156000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  90934091299                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  85798030625                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 176732121924                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  90934091299                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  85798030625                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 176732121924                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12867454                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13288381                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26155835                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9649945                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9954862                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19604807                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       264509                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       281824                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       546333                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223628                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250967                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       474595                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216129                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459474                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22517399                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23243243                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45760642                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22781908                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23525067                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46306975                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032068                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031713                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031888                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202951                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.174405                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188456                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323679                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.347660                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336050                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061589                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056079                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058675                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000125                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000140                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000133                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105301                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.092827                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.098965                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107836                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.095880                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.101762                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14726.615096                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.425850                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.118942                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43328.555928                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45700.331893                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44443.095908                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13202.388732                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14817.642461                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14018.745287                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22648.148148                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16014.705882                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18950.819672                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38351.014845                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39765.623371                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39024.972972                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37014.490604                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 38038.258422                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 37504.524750                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1148125                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       185430                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            52981                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2987                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.670505                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    62.079009                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses        189302421                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189302421                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12461175                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12728962                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25190137                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7687590                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      8214972                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15902562                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       179184                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       184541                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       363725                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210025                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236354                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446379                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216363                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243044                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459407                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20148765                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     20943934                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41092699                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20327949                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     21128475                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       41456424                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       423956                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       411527                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       835483                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1938723                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1762743                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      3701466                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        85809                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        99027                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       184836                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13675                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14161                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        27836                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           25                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data           39                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           64                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2362679                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      2174270                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4536949                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2448488                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      2273297                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4721785                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6233091500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6311528000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  12544619500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83629442032                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  80611512663                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 164240954695                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    181225000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    207964000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    389189000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       566500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       630000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      1196500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  89862533532                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  86923040663                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 176785574195                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  89862533532                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  86923040663                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 176785574195                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     12885131                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13140489                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26025620                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9626313                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9977715                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19604028                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       264993                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       283568                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       548561                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223700                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250515                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474215                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216388                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243083                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459471                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22511444                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     23118204                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45629648                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     22776437                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23401772                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46178209                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032903                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031317                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032102                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.201398                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.176668                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188812                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323816                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.349218                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336947                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061131                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056528                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058699                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000116                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000160                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000139                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.104955                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.094050                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099430                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107501                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097142                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.102251                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14702.213201                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15336.850316                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15014.811193                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43136.354204                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45730.723459                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44371.866362                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13252.285192                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14685.686039                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13981.498779                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        22660                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16153.846154                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18695.312500                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38034.169488                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39978.034312                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 38965.739795                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36701.235020                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 38236.552753                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 37440.411665                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1130992                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       181993                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            52749                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2872                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.441013                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    63.368036                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       703579                       # number of writebacks
-system.cpu0.dcache.writebacks::total           703579                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       198603                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       210557                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       409160                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1801482                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1593619                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3395101                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9550                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9160                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18710                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2000085                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1804176                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3804261                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2000085                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1804176                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3804261                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       214035                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       210859                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       424894                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156980                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       142558                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299538                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58648                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64092                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122740                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4223                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4914                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9137                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           27                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           34                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           61                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       371015                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       353417                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       724432                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       429663                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       417509                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       847172                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16542                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14585                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.writebacks::writebacks       704468                       # number of writebacks
+system.cpu0.dcache.writebacks::total           704468                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       206826                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       203538                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       410364                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1782978                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1618509                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3401487                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9580                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9255                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18835                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1989804                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1822047                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3811851                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1989804                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1822047                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3811851                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       217130                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       207989                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       425119                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       155745                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       144234                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299979                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58865                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64694                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       123559                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4095                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4906                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9001                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           25                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           39                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           64                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       372875                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       352223                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       725098                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       431740                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       416917                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       848657                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16525                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14602                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16149                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11435                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16127                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11457                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32691                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26020                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32652                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26059                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3018980500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3044091500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6063072000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7145217382                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6750047429                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13895264811                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    806467500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    918616000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1725083500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     54857500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82625000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137482500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       584500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       510500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1095000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10164197882                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9794138929                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  19958336811                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10970665382                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10712754929                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  21683420311                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3143585500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2772334000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5915919500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2404168377                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2168590500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4572758877                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5547753877                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4940924500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10488678377                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016634                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015868                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016267                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014320                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.221724                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.227419                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224662                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018884                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019580                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019252                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000125                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000140                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000133                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016477                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015205                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015831                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018860                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017747                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018295                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14105.078609                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14436.621154                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14269.610774                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45516.737049                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47349.481818                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46388.988412                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13750.980426                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14332.771641                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14054.778393                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12990.172863                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16814.204314                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15046.787786                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21648.148148                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15014.705882                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17950.819672                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27395.652149                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27712.698962                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27550.324683                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25533.186199                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25658.740121                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25595.062527                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190036.603796                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190081.179294                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.490282                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148874.133197                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189644.993441                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.771353                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169702.789055                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189889.488855                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.288498                       # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3060881000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3004845500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6065726500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7052803399                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6808261422                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13861064821                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    813215500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    923997500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1737213000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     53086000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     81449000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    134535000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       541500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       591000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1132500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10113684399                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9813106922                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  19926791321                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10926899899                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10737104422                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  21664004321                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3144537000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2771379000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5915916000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2402448877                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2170311500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4572760377                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5546985877                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4941690500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10488676377                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016851                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015828                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016335                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016179                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014456                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015302                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222138                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.228143                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225242                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018306                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019584                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018981                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000116                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000160                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000139                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016564                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015236                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015891                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018956                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017816                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018378                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14096.997191                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14447.136627                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14268.302522                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45284.300613                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47202.888514                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46206.783878                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13814.923979                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14282.584165                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14059.785204                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12963.614164                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16601.916021                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14946.672592                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        21660                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15153.846154                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17695.312500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27123.525039                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27860.494408                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27481.514666                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25308.982024                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25753.577863                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25527.397195                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190289.682300                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189794.480208                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190057.377839                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148970.600670                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189431.046522                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165775.825732                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169881.963647                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189634.694347                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178649.254433                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1944870                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.570452                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           39033281                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1945382                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.064584                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9679828500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   227.356025                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   284.214426                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.444055                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.555106                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999161                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1933259                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.562237                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           38860881                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1933771                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            20.095906                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9655718500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   227.659514                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   283.902722                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.444647                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.554498                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999145                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          145                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43073652                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43073652                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19127800                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19905481                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       39033281                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19127800                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19905481                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        39033281                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19127800                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19905481                       # number of overall hits
-system.cpu0.icache.overall_hits::total       39033281                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1044128                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1050765                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2094893                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1044128                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1050765                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2094893                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1044128                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1050765                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2094893                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14016783986                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14160518990                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  28177302976                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14016783986                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  14160518990                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  28177302976                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14016783986                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  14160518990                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  28177302976                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20171928                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20956246                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41128174                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20171928                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20956246                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41128174                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20171928                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20956246                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41128174                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051761                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050141                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050936                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051761                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050141                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050936                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051761                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050141                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050936                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13424.392398                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.390049                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13450.473593                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13424.392398                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.390049                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13450.473593                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13424.392398                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.390049                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13450.473593                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        10866                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42875303                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42875303                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19083138                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19777743                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       38860881                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19083138                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19777743                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        38860881                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19083138                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19777743                       # number of overall hits
+system.cpu0.icache.overall_hits::total       38860881                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1035596                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1044946                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2080542                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1035596                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1044946                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2080542                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1035596                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1044946                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2080542                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13933067983                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14083489486                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  28016557469                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13933067983                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  14083489486                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  28016557469                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13933067983                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  14083489486                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  28016557469                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20118734                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20822689                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     40941423                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20118734                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     20822689                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     40941423                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20118734                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20822689                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     40941423                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051474                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050183                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050818                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051474                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050183                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050818                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051474                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050183                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050818                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13454.153920                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.719888                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13465.989857                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13454.153920                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13477.719888                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13465.989857                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13454.153920                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13477.719888                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13465.989857                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        11261                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              629                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              589                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.275040                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.118846                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        74230                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        75184                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       149414                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        74230                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        75184                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       149414                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        74230                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        75184                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       149414                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       969898                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       975581                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1945479                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       969898                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       975581                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1945479                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       969898                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       975581                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1945479                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        72785                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        73876                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       146661                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        72785                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        73876                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       146661                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        72785                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        73876                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       146661                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       962811                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       971070                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1933881                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       962811                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       971070                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1933881                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       962811                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       971070                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1933881                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          670                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total          670                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          670                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total          670                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12381694490                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12496898492                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  24878592982                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12381694490                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12496898492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  24878592982                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12381694490                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12496898492                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  24878592982                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12308964487                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12437182489                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  24746146976                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12308964487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12437182489                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  24746146976                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12308964487                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12437182489                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  24746146976                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     52946500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     52946500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     52946500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total     52946500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048082                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046553                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047303                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048082                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046553                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047303                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048082                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046553                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047303                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12765.975896                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12809.698520                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12787.901068                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12765.975896                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12809.698520                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12787.901068                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12765.975896                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12809.698520                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12787.901068                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047856                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046635                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047235                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047856                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046635                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047235                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047856                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046635                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047235                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12784.403675                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.709526                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12796.106366                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12784.403675                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.709526                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12796.106366                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12784.403675                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.709526                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12796.106366                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79024.626866                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79024.626866                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79024.626866                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27779338                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14456404                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           556707                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17586832                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               13077233                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27575669                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14289271                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           524894                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17274855                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               12959236                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            74.358094                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6867114                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             29983                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            75.017915                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6858393                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             28646                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1340,90 +1325,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    59343                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               59343                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        20532                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13405                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        25406                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        33937                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   563.264284                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3642.212390                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        33612     99.04%     99.04% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          250      0.74%     99.78% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           49      0.14%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           14      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919            8      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    57029                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               57029                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18821                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        12862                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        25346                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        31683                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   591.216110                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3688.783466                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383        31359     98.98%     98.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767          255      0.80%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151           48      0.15%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535           10      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919            7      0.02%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        33937                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        12361                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12657.592428                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10412.763280                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7705.801044                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         3725     30.14%     30.14% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5842     47.26%     77.40% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2426     19.63%     97.02% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          136      1.10%     98.12% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959          110      0.89%     99.01% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151          110      0.89%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            5      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::73728-81919            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-90111            3      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        12361                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  85582012132                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.698276                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.478879                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  85506656132     99.91%     99.91% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     54226500      0.06%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5     10815500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      3396500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9      2104000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11      1227000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       804500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15      1696500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       468000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19       271500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21       107000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23        23500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25       101500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27        14500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29        14000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31        85500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  85582012132                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3538     68.22%     68.22% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1648     31.78%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5186                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59343                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total        31683                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        12352                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12478.424547                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10246.973289                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7685.568959                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         3962     32.08%     32.08% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5577     45.15%     77.23% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2494     20.19%     97.42% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          102      0.83%     98.24% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959           90      0.73%     98.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151          118      0.96%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            5      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-90111            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        12352                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  89696770428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.667017                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.494297                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3  89674974428     99.98%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7     14056500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11      3500500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15      2366000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19       661500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23       722500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27       410000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31        58000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35        21000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  89696770428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3380     68.04%     68.04% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1588     31.96%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         4968                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        57029                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59343                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5186                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        57029                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         4968                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5186                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        64529                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         4968                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        61997                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14473413                       # DTB read hits
-system.cpu1.dtb.read_misses                     50516                       # DTB read misses
-system.cpu1.dtb.write_hits                   10662986                       # DTB write hits
-system.cpu1.dtb.write_misses                     8827                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     454                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    14318727                       # DTB read hits
+system.cpu1.dtb.read_misses                     47357                       # DTB read misses
+system.cpu1.dtb.write_hits                   10661439                       # DTB write hits
+system.cpu1.dtb.write_misses                     9672                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         177                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     435                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3428                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      911                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1182                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3458                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      745                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1189                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      534                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14523929                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10671813                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      539                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14366084                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10671111                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         25136399                       # DTB hits
-system.cpu1.dtb.misses                          59343                       # DTB misses
-system.cpu1.dtb.accesses                     25195742                       # DTB accesses
+system.cpu1.dtb.hits                         24980166                       # DTB hits
+system.cpu1.dtb.misses                          57029                       # DTB misses
+system.cpu1.dtb.accesses                     25037195                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1453,385 +1431,385 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     8383                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                8383                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         3253                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4959                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          171                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         8212                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1247.503653                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  5444.991786                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191         7787     94.82%     94.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383          188      2.29%     97.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575          140      1.70%     98.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767           47      0.57%     99.39% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959           15      0.18%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151           15      0.18%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343            8      0.10%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535            6      0.07%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727            4      0.05%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         8212                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2522                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13607.454401                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11346.951670                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  7824.124854                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095           43      1.70%      1.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          713     28.27%     29.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          591     23.43%     53.41% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          450     17.84%     71.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           33      1.31%     72.56% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575          613     24.31%     96.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           21      0.83%     97.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767           20      0.79%     98.49% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863           10      0.40%     98.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.12%     99.01% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055           20      0.79%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::45056-49151            3      0.12%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::53248-57343            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2522                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  25452156488                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.888283                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.315639                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     2847537836     11.19%     11.19% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    22601300152     88.80%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        2634500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         584500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          99500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  25452156488                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1775     75.50%     75.50% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          576     24.50%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2351                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     7307                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                7307                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2390                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4761                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          156                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         7151                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1572.647182                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  6795.072359                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         6710     93.83%     93.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          190      2.66%     96.49% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575          127      1.78%     98.27% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           50      0.70%     98.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           21      0.29%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           20      0.28%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343           12      0.17%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            7      0.10%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            4      0.06%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919            4      0.06%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            1      0.01%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::90112-98303            3      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::106496-114687            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7151                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2506                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 14007.980846                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11793.815638                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  8015.636923                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          694     27.69%     27.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383         1049     41.86%     69.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575          688     27.45%     97.01% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           39      1.56%     98.56% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959           20      0.80%     99.36% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151           13      0.52%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::122880-131071            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2506                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  33862083580                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.923542                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.266537                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     2594238448      7.66%      7.66% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    31264179132     92.33%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2561000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         759000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         256500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          89500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  33862083580                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1782     75.83%     75.83% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          568     24.17%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2350                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8383                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8383                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7307                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7307                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2351                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2351                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        10734                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20958158                       # ITB inst hits
-system.cpu1.itb.inst_misses                      8383                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2350                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2350                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         9657                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20824521                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7307                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     454                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         177                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     435                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2298                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2324                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1383                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1310                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20966541                       # ITB inst accesses
-system.cpu1.itb.hits                         20958158                       # DTB hits
-system.cpu1.itb.misses                           8383                       # DTB misses
-system.cpu1.itb.accesses                     20966541                       # DTB accesses
-system.cpu1.numCycles                       108767456                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20831828                       # ITB inst accesses
+system.cpu1.itb.hits                         20824521                       # DTB hits
+system.cpu1.itb.misses                           7307                       # DTB misses
+system.cpu1.itb.accesses                     20831828                       # DTB accesses
+system.cpu1.numCycles                       108440670                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          40797494                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     108309619                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27779338                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19944347                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     62902331                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3273623                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    135203                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                7501                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              353                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       608716                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       138611                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          328                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20956250                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               381072                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3851                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         106227312                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.226074                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.322776                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          40658841                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     107348372                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27575669                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19817629                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     63179196                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3214627                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    116865                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                7302                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              337                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       214773                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       119592                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          256                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20822690                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               365691                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3329                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         105904439                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.219564                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.316618                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                76467157     71.98%     71.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3961882      3.73%     75.71% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2508117      2.36%     78.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8239256      7.76%     85.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1628076      1.53%     87.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1204845      1.13%     88.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6274984      5.91%     94.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1183680      1.11%     95.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4759315      4.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                76345521     72.09%     72.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3953421      3.73%     75.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2478828      2.34%     78.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8244207      7.78%     85.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1577040      1.49%     87.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1177168      1.11%     88.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6267610      5.92%     94.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1171227      1.11%     95.57% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4689417      4.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           106227312                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.255401                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.995791                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                27883552                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             59140248                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15967546                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1750379                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1485269                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             2004727                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               153597                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              90349816                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               499958                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1485269                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                28837036                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                5092551                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      46434989                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16757814                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              7619325                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              86416848                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 2460                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1673796                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                189232                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               4958723                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           89422811                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            398213792                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        96413461                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5558                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             75531757                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13891038                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1607608                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1506576                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 10031791                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15342800                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11846385                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2170677                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2932432                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  83143036                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1157387                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 79677045                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            92227                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       11399767                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     25586754                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        106787                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    106227312                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.750062                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.431163                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           105904439                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.254293                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.989927                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                27742693                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             59209108                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15734012                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1761502                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1456830                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1964004                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               152599                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              89283066                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               495711                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1456830                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                28693287                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                4990149                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      46482214                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16541431                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              7740224                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              85441153                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 1754                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1703174                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                185824                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               5043602                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           88283625                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            394169118                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        95445176                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             5573                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             75350045                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                12933564                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1608887                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1508528                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 10148655                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15129586                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11812866                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2166416                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2845057                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  82323765                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1155194                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 79175749                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            89458                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       10712710                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     23890163                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        105302                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    105904439                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.747615                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.428343                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           74225476     69.87%     69.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10735161     10.11%     79.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8165707      7.69%     87.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6810651      6.41%     94.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2489155      2.34%     96.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1551071      1.46%     97.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1525154      1.44%     99.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             483878      0.46%     99.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             241059      0.23%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           74038259     69.91%     69.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10747404     10.15%     80.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8120323      7.67%     87.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6768186      6.39%     94.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2459889      2.32%     96.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1534209      1.45%     97.89% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1518475      1.43%     99.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             479862      0.45%     99.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             237832      0.22%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      106227312                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      105904439                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 112109      9.87%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                520489     45.82%     55.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               503315     44.31%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 107820      9.57%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.57% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                518879     46.05%     55.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               500179     44.39%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass              152      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             53438266     67.07%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               58943      0.07%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              2      0.00%     67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4274      0.01%     67.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     67.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14882536     18.68%     85.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11292868     14.17%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             53114016     67.08%     67.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               58553      0.07%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              2      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4284      0.01%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14709821     18.58%     85.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11288919     14.26%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              79677045                       # Type of FU issued
-system.cpu1.iq.rate                          0.732545                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1135919                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014257                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         266797245                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         95743822                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     77316154                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              12303                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6570                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5329                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              80806190                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   6622                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          349291                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              79175749                       # Type of FU issued
+system.cpu1.iq.rate                          0.730130                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1126884                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014233                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         265459723                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         94235106                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     76889252                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              12556                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6622                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5424                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              80295719                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   6762                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          344779                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2194104                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2343                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        51353                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1130901                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2039504                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2297                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        51237                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1073925                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       191600                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       108001                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       189496                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       106526                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1485269                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                4109384                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               740435                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           84415132                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           132598                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15342800                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11846385                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            585452                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 40704                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               687401                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         51353                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        260478                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       222263                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              482741                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             79065408                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14638962                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           552436                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1456830                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                3996467                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               749020                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           83580457                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           125116                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15129586                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11812866                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            584610                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 40298                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               696432                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         51237                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        238658                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       209145                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              447803                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             78601263                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14483577                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           517602                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       114709                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25822462                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14738058                       # Number of branches executed
-system.cpu1.iew.exec_stores                  11183500                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.726922                       # Inst execution rate
-system.cpu1.iew.wb_sent                      78493230                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     77321483                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 40676282                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 71272745                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       101498                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25666157                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14648718                       # Number of branches executed
+system.cpu1.iew.exec_stores                  11182580                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.724832                       # Inst execution rate
+system.cpu1.iew.wb_sent                      78056908                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     76894676                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 40431219                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 70987120                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.710888                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.570713                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.709094                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.569557                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       11437303                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls        1050600                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           405128                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    103651619                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.703948                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.590010                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       10746753                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls        1049892                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           374374                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    103429928                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.704076                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.589371                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     75257268     72.61%     72.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12658548     12.21%     84.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6546278      6.32%     91.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2731593      2.64%     93.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1415647      1.37%     95.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       932934      0.90%     96.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1873819      1.81%     97.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       434966      0.42%     98.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1800566      1.74%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     75071598     72.58%     72.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12660376     12.24%     84.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6524786      6.31%     91.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2717712      2.63%     93.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1422802      1.38%     95.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       934618      0.90%     96.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1880111      1.82%     97.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       428884      0.41%     98.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1789041      1.73%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    103651619                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            60242910                       # Number of instructions committed
-system.cpu1.commit.committedOps              72965345                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    103429928                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            60079421                       # Number of instructions committed
+system.cpu1.commit.committedOps              72822564                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23864180                       # Number of memory references committed
-system.cpu1.commit.loads                     13148696                       # Number of loads committed
-system.cpu1.commit.membars                     435175                       # Number of memory barriers committed
-system.cpu1.commit.branches                  13969261                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5270                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 63961435                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2719031                       # Number of function calls committed.
+system.cpu1.commit.refs                      23829023                       # Number of memory references committed
+system.cpu1.commit.loads                     13090082                       # Number of loads committed
+system.cpu1.commit.membars                     434438                       # Number of memory barriers committed
+system.cpu1.commit.branches                  13936997                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5382                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 63857795                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2718317                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        49039858     67.21%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57036      0.08%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4271      0.01%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13148696     18.02%     85.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10715484     14.69%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        48932373     67.19%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          56887      0.08%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4281      0.01%     67.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13090082     17.98%     85.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10738941     14.75%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         72965345                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1800566                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   173538824                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  171385524                       # The number of ROB writes
-system.cpu1.timesIdled                         389774                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2540144                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2437281840                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   60178217                       # Number of Instructions Simulated
-system.cpu1.committedOps                     72900652                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.807422                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.807422                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.553274                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.553274                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                85982923                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               49280931                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    16090                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13091                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                279167136                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29456801                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              148724045                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                795207                       # number of misc regfile writes
+system.cpu1.commit.op_class_0::total         72822564                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1789041                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   172463469                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  169617134                       # The number of ROB writes
+system.cpu1.timesIdled                         388810                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2536231                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2437380839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   60023102                       # Number of Instructions Simulated
+system.cpu1.committedOps                     72766245                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.806649                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.806649                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.553511                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.553511                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                85555118                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48994368                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    16096                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13216                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                277440920                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29218779                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              148245272                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                794768                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
@@ -1926,7 +1904,7 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           187534443                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           187527447                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
@@ -1935,14 +1913,14 @@ system.iobus.respLayer0.utilization               0.0                       # La
 system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                0.981092                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.980586                       # Cycle average of tags in use
 system.iocache.tags.total_refs                     29                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000796                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         234155624000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.981092                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.061318                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.061318                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         234074441000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.980586                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.061287                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.061287                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1958,14 +1936,14 @@ system.iocache.demand_misses::realview.ide          249                       #
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     30881877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     30881877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4272011566                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4272011566                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     30881877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     30881877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     30881877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     30881877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     30886877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30886877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4270029570                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4270029570                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     30886877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     30886877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     30886877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     30886877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1982,14 +1960,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124023.602410                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124023.602410                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118024.410598                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118024.410598                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124023.602410                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124023.602410                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124023.602410                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124023.602410                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124043.682731                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124043.682731                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117969.653277                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 117969.653277                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124043.682731                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124043.682731                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124043.682731                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124043.682731                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -2008,14 +1986,14 @@ system.iocache.demand_mshr_misses::realview.ide          249
 system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18431877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18431877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2462211566                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2462211566                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18431877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18431877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18431877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18431877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18436877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18436877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2460229570                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2460229570                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18436877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18436877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18436877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18436877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999227                       # mshr miss rate for WriteLineReq accesses
@@ -2024,270 +2002,270 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74023.602410                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74023.602410                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68024.410598                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68024.410598                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74023.602410                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74023.602410                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74023.602410                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74023.602410                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74043.682731                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74043.682731                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67969.653277                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67969.653277                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74043.682731                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74043.682731                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74043.682731                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74043.682731                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104591                       # number of replacements
-system.l2c.tags.tagsinuse                65128.853062                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5158175                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169835                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.371684                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48560.603393                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    44.868379                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                   104376                       # number of replacements
+system.l2c.tags.tagsinuse                65128.447881                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5130866                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   169621                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    30.249002                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              71309274500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   48546.195919                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    40.752142                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000245                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4741.126354                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2359.678514                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    45.227842                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     5921.248068                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3456.100266                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.740976                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000685                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     4832.971752                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2370.323357                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    46.716496                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     5940.987464                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3350.500506                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.740756                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000622                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.072344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.036006                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000690                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.090351                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.052736                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.993787                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           74                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65170                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           74                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          365                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3250                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         9056                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52484                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001129                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994415                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 45590460                       # Number of tag accesses
-system.l2c.tags.data_accesses                45590460                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        36255                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         7974                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        36433                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         8351                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  89013                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          703579                       # number of Writeback hits
-system.l2c.Writeback_hits::total               703579                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              56                       # number of UpgradeReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.073745                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.036168                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000713                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.090652                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.051125                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.993781                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           60                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65185                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           60                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3268                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         9040                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52500                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000916                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994644                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 45389875                       # Number of tag accesses
+system.l2c.tags.data_accesses                45389875                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        34639                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         7724                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        34842                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         7429                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  84634                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          704468                       # number of Writeback hits
+system.l2c.Writeback_hits::total               704468                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              46                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data              38                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  94                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            19                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            29                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                48                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            83887                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            72292                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               156179                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        959569                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        964750                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1924319                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       270036                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       271500                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           541536                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         36255                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          7974                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              959569                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              353923                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         36433                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          8351                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              964750                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              343792                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2711047                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        36255                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         7974                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             959569                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             353923                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        36433                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         8351                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             964750                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             343792                       # number of overall hits
-system.l2c.overall_hits::total                2711047                       # number of overall hits
+system.l2c.UpgradeReq_hits::total                  84                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            18                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            33                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                51                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            83572                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            73244                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               156816                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        952414                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        960356                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1912770                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       273094                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       269324                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           542418                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         34639                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          7724                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              952414                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              356666                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         34842                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          7429                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              960356                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              342568                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2696638                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        34639                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         7724                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             952414                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             356666                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        34842                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         7429                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             960356                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             342568                       # number of overall hits
+system.l2c.overall_hits::total                2696638                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker           70                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           72                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  143                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1471                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1262                       # number of UpgradeReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           70                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  141                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1473                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1260                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2733                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            8                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            5                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data            7                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data            6                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total              13                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          71586                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          68983                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140569                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        10198                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        10688                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           20886                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         6850                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         8348                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total          15198                       # number of ReadSharedReq misses
+system.l2c.ReadExReq_misses::cpu0.data          70675                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          69701                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140376                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        10270                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst        10574                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           20844                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         6975                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         8256                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total          15231                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.dtb.walker           70                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             10198                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             78436                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           72                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             10688                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             77331                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                176796                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             10270                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             77650                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           70                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             10574                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             77957                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                176592                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker           70                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            10198                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            78436                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           72                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            10688                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            77331                       # number of overall misses
-system.l2c.overall_misses::total               176796                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      6042500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu0.inst            10270                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            77650                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           70                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            10574                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            77957                       # number of overall misses
+system.l2c.overall_misses::total               176592                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      6224500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker        68500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      6012000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       12123000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data       460000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       400000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       860000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       191000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data        62000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       253000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5970431000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5726703500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11697134500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst    834109000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    885703000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1719812000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data    591630000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    736687500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   1328317500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      6042500                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      6112000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total       12405000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       368500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       553000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       921500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       253500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       123000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       376500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5883028500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   5772465500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  11655494000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst    846782000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    878839000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   1725621000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data    600442500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    729164500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total   1329607000                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      6224500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker        68500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    834109000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   6562061000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      6012000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    885703000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   6463391000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     14757387000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      6042500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    846782000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   6483471000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      6112000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    878839000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   6501630000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     14723127000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      6224500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker        68500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    834109000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   6562061000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      6012000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    885703000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   6463391000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    14757387000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        36325                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         7975                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        36505                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         8351                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              89156                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       703579                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           703579                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1527                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1300                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2827                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           27                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data           34                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            61                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       155473                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       141275                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296748                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       969767                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       975438                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1945205                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       276886                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       279848                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       556734                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        36325                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7975                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          969767                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          432359                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        36505                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         8351                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          975438                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          421123                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2887843                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        36325                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7975                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         969767                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         432359                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        36505                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         8351                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         975438                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         421123                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2887843                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001927                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000125                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001972                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.001604                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.963327                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.970769                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.966749                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.296296                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.147059                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.213115                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.460440                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.488289                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.473698                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010516                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.010957                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.010737                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.024739                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.029830                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.027298                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001927                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000125                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.010516                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.181414                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001972                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010957                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.183630                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.061221                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001927                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000125                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.010516                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.181414                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001972                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010957                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.183630                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.061221                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86321.428571                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst    846782000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   6483471000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      6112000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    878839000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   6501630000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    14723127000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        34709                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         7725                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        34912                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         7429                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              84775                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       704468                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           704468                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1519                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1298                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2817                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           25                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data           39                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            64                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       154247                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       142945                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           297192                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       962684                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       970930                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1933614                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       280069                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       277580                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       557649                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        34709                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         7725                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          962684                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          434316                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        34912                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7429                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          970930                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          420525                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2873230                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        34709                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         7725                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         962684                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         434316                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        34912                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7429                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         970930                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         420525                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2873230                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.002017                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000129                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.002005                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.001663                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.969717                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.970724                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.970181                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.280000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.153846                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.203125                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.458194                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.487607                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.472341                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010668                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.010891                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010780                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.024905                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.029743                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.027313                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.002017                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000129                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010668                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.178787                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.002005                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010891                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.185380                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.061461                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.002017                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000129                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.010668                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.178787                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.002005                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010891                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.185380                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.061461                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88921.428571                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        68500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        83500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 84776.223776                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   312.712441                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   316.957211                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   314.672521                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        23875                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        12400                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 19461.538462                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83402.215517                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83016.156154                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 83212.760281                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81791.429692                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82868.918413                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 82342.813368                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86369.343066                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88247.184954                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 87400.809317                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86321.428571                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87314.285714                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 87978.723404                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   250.169722                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   438.888889                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   337.175265                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 36214.285714                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        20500                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 28961.538462                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83240.587195                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82817.542073                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 83030.532285                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82451.996105                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83113.202194                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 82787.420841                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86084.946237                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88319.343508                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 87296.106625                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88921.428571                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        68500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 81791.429692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 83661.341731                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        83500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82868.918413                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 83580.853733                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 83471.271974                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86321.428571                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 82451.996105                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 83496.084997                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87314.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83113.202194                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 83400.207807                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 83373.691900                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88921.428571                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        68500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 81791.429692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 83661.341731                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        83500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82868.918413                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 83580.853733                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 83471.271974                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 82451.996105                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 83496.084997                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87314.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83113.202194                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 83400.207807                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 83373.691900                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2296,220 +2274,220 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95583                       # number of writebacks
-system.l2c.writebacks::total                    95583                       # number of writebacks
+system.l2c.writebacks::writebacks               95805                       # number of writebacks
+system.l2c.writebacks::total                    95805                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            7                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           76                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           61                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          137                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           79                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           59                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          138                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             76                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             79                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             61                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                150                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             59                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                151                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            76                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            79                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            61                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               150                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            59                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               151                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           70                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           72                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             143                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1471                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1262                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           70                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total             141                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1473                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1260                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total         2733                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total           13                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        71586                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        68983                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        140569                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        10192                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10681                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        20873                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6774                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         8287                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total        15061                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        70675                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        69701                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140376                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        10264                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10567                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        20831                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6896                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         8197                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total        15093                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker           70                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        10192                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        78360                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           72                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        10681                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        77270                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           176646                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        10264                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        77571                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           70                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        10567                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        77898                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           176441                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker           70                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        10192                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        78360                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           72                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        10681                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        77270                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          176646                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        10264                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        77571                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           70                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        10567                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        77898                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          176441                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          670                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16542                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14585                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16525                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14602                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::total        31797                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16149                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11435                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16127                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11457                       # number of WriteReq MSHR uncacheable
 system.l2c.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          670                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32691                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26020                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32652                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26059                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::total        59381                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5342500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5524500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        58500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5292000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     10693000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     30584000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     26180500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     56764500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       264500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       105000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       369500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5254571000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5036873500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  10291444500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    731590500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    778604000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1510194500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    518333500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    649828500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1168162000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      5342500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5412000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     10995000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     30607000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     26163500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     56770500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       245000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       126000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       371000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5176278500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5075455500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  10251734000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    743672000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    772867500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1516539500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    525992000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    643329500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   1169321500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      5524500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        58500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    731590500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   5772904500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      5292000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    778604000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   5686702000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  12980494000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      5342500                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    743672000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   5702270500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      5412000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    772867500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   5718785000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  12948590000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      5524500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        58500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    731590500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   5772904500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      5292000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    778604000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   5686702000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  12980494000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    743672000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   5702270500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      5412000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    772867500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   5718785000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  12948590000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     42529000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2936807000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2590020500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5569356500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2216276000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2037082000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4253358000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2937973000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2588853500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5569355500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2214813000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2038551500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4253364500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     42529000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5153083000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4627102500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   9822714500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001927                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000125                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001972                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.001604                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.963327                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.970769                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.966749                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.296296                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.147059                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.213115                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.460440                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.488289                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.473698                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010510                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010950                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010730                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.024465                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.029613                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027052                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001927                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000125                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010510                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.181238                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001972                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010950                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.183486                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.061169                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001927                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000125                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010510                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.181238                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001972                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010950                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.183486                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.061169                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5152786000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4627405000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   9822720000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.002017                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000129                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002005                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.001663                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.969717                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.970724                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.970181                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.280000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.153846                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.203125                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.458194                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.487607                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.472341                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010662                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010883                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010773                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.024623                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.029530                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027065                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.002017                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000129                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010662                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.178605                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002005                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010883                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.185240                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.061409                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.002017                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000129                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010662                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.178605                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002005                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010883                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.185240                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.061409                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        58500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 74776.223776                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20791.298436                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20745.245642                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20770.032931                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 33062.500000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 77978.723404                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20778.682960                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20764.682540                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20772.228321                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        35000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        21000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28423.076923                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73402.215517                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73016.156154                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 73212.760281                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71780.857535                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72896.170771                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72351.578594                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76518.083850                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78415.409678                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77562.047673                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28538.461538                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73240.587195                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72817.542073                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 73030.532285                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72454.403741                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73139.727453                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72802.049830                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76274.941995                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78483.530560                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77474.425230                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        58500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71780.857535                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73671.573507                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72896.170771                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73595.211596                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 73483.090475                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76321.428571                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72454.403741                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73510.338915                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73139.727453                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73413.759018                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 73387.647996                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78921.428571                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        58500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71780.857535                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73671.573507                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72896.170771                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73595.211596                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 73483.090475                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72454.403741                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73510.338915                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77314.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73139.727453                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73413.759018                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 73387.647996                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177536.392214                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177581.110730                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.520772                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137239.209858                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178144.468736                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.563225                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177789.591528                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177294.445966                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 175153.489323                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 137335.710299                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177930.653749                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154196.798869                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63476.119403                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157630.020495                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177828.689470                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.475607                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157809.200049                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177574.158640                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 165418.568229                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68122                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68110                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::Writeback            131744                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             9021                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4618                       # Transaction distribution
+system.membus.trans_dist::Writeback            131966                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8584                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4635                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq             13                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4631                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138685                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138685                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36326                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4648                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138475                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138475                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36314                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36195                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36195                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       474277                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       581847                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473652                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       581222                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108830                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108830                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 690677                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 690052                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
@@ -2519,28 +2497,28 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315264
 system.membus.pkt_size_system.iocache.mem_side::total      2315264                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                19824861                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              523                       # Total snoops (count)
-system.membus.snoop_fanout::samples            416234                       # Request fanout histogram
+system.membus.snoop_fanout::samples            415806                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  416234    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  415806    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              416234                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95824000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              415806                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95819000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1684000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1699000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           923050293                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           923516805                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1019598366                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1018756091                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64439557                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64465031                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2573,66 +2551,66 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq             154492                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2656868                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             148196                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2639888                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           835335                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2054815                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2828                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            61                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2888                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296748                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296748                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1945479                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       556983                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           836438                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2043009                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2818                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            64                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2881                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           297192                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          297192                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1933881                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       557898                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36195                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5795514                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2675972                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42691                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169160                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8683337                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124535936                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99845469                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        65304                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       291320                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224738029                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          211435                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5959204                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.050368                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.218703                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5760848                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2679672                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        39941                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       161233                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8641694                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    123794112                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99989277                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        60616                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       278484                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              224122489                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          209289                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5932182                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.049498                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.216906                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                5659051     94.96%     94.96% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 300153      5.04%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                5638548     95.05%     95.05% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 293634      4.95%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5959204                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3608244499                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            5932182                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3595734997                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           246000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           244500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2920237464                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2902818005                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1326853963                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1328890460                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          26388950                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          24804964                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          96751648                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          92041633                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3039                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
index 04d020f53..12d23ceab 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -179,7 +179,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -638,7 +638,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -748,7 +748,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -909,7 +909,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1368,7 +1368,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1478,7 +1478,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -1591,7 +1591,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1626,7 +1626,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -2041,9 +2041,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
index 501ee633b..e5014ea5e 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:55:42
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 14 2015 23:38:12
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47411962285000 because m5_exit instruction encountered
+Exiting @ tick 47482239150000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index d121e108e..683a782fa 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,170 +1,170 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.411962                       # Number of seconds simulated
-sim_ticks                                47411962285000                       # Number of ticks simulated
-final_tick                               47411962285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.482239                       # Number of seconds simulated
+sim_ticks                                47482239150000                       # Number of ticks simulated
+final_tick                               47482239150000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167928                       # Simulator instruction rate (inst/s)
-host_op_rate                                   197524                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9366197696                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 719564                       # Number of bytes of host memory used
-host_seconds                                  5062.03                       # Real time elapsed on the host
-sim_insts                                   850056300                       # Number of instructions simulated
-sim_ops                                     999871495                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 126606                       # Simulator instruction rate (inst/s)
+host_op_rate                                   148916                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6789587746                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 767628                       # Number of bytes of host memory used
+host_seconds                                  6993.39                       # Real time elapsed on the host
+sim_insts                                   885402765                       # Number of instructions simulated
+sim_ops                                    1041431052                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        75328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        71168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7498816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         38111304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     10728384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        51264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        47808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2878784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12174608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      7747264                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        431104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             79815832                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      7498816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2878784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10377600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     62807296                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        88704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        71680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          8153920                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         42330888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     14734656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       154368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       137408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2906176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         14216400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     12693312                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        441664                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             95929176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      8153920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2906176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11060096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     76090688                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          62827880                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1177                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1112                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            117169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            595502                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       167631                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          801                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          747                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             44981                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            190241                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       121051                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6736                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1247148                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          981364                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          76111272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1386                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1120                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            127405                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            661433                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       230229                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2412                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2147                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             45409                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            222144                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       198333                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6901                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1498919                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1188917                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               983938                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1589                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              158163                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              803833                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       226280                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1081                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               60719                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              256783                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       163403                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9093                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1683453                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         158163                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          60719                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             218881                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1324714                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1191491                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              171726                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              891510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       310319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3251                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               61206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              299405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       267328                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9302                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2020317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         171726                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          61206                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             232931                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1602508                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1325148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1324714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1589                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             158163                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             804267                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       226280                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1081                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              60719                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             256784                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       163403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9093                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3008602                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1247148                       # Number of read requests accepted
-system.physmem.writeReqs                       983938                       # Number of write requests accepted
-system.physmem.readBursts                     1247148                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     983938                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 79775360                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     42112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  62826240                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  79815832                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               62827880                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      658                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         218244                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               71187                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               77028                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               72273                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               78219                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               70385                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               81119                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               72267                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               76746                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               71370                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              123762                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              72044                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              80747                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              73100                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              79351                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              74612                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              72280                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               58860                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               62909                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               59749                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               64358                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               59245                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               66477                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               59553                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               62082                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               58790                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               60994                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              60508                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              63849                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              60193                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              63756                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              60310                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              60027                       # Per bank write bursts
+system.physmem.bw_write::total                1602942                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1602508                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1510                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             171726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             891943                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       310319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3251                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2894                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              61206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             299405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       267328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9302                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3623259                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1498919                       # Number of read requests accepted
+system.physmem.writeReqs                      1191491                       # Number of write requests accepted
+system.physmem.readBursts                     1498919                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1191491                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 95891200                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     39616                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  76109696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  95929176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               76111272                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      619                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         217911                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               89027                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               94433                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               86611                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               92371                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               85965                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               91989                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               84150                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               94780                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               85741                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              143775                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              89074                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              90853                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              89498                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              91267                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              94459                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              94307                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               73359                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               78327                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               72063                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               77110                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               71233                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               76219                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               70290                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               78154                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               70631                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               75804                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              71232                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              74262                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              72932                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              74472                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              77093                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              76033                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47411960356500                       # Total gap between requests
+system.physmem.numWrRetry                          28                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47482237279500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1247118                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1498889                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 981364                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    795503                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    313068                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30154                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     22514                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     19326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     17861                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     16010                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     13834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     11987                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2659                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      695                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      367                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      206                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      146                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1188917                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    923724                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    366189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     46304                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     33513                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     28479                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     26369                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     23870                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     21021                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     18560                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1922                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      878                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      593                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      355                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      308                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      261                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      223                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       79                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -188,150 +188,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    14920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    17590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    38389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    48185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    52683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    54849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    56160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    59815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    60639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    63775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    62891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    64447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63620                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    68672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    63414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    57038                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1401                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      972                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       86                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       737647                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      193.317834                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     117.156586                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     253.851861                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         435526     59.04%     59.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       146539     19.87%     78.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49058      6.65%     85.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        25178      3.41%     88.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15871      2.15%     91.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10341      1.40%     92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7959      1.08%     93.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8404      1.14%     94.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        38771      5.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         737647                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         55115                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.615186                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      363.032286                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          55112     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    16928                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    19684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    43592                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    62915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    66422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    68359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    72568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    74023                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    77349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    76686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    79204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    77889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    78555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    85240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    78371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    74036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    70191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      826                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      473                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       84                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       913839                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      188.217382                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     115.370572                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     246.881339                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         545143     59.65%     59.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       181104     19.82%     79.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        60696      6.64%     86.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        30627      3.35%     89.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        20207      2.21%     91.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12827      1.40%     93.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9718      1.06%     94.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9868      1.08%     95.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        43649      4.78%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         913839                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         67807                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.096303                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      333.350943                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          67804    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           55115                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         55115                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.811122                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.212895                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.489514                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           52725     95.66%     95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             682      1.24%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             764      1.39%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             154      0.28%     98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              76      0.14%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              61      0.11%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             472      0.86%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             111      0.20%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              10      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              8      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            31      0.06%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             7      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             3      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           55115                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    32865022462                       # Total ticks spent queuing
-system.physmem.totMemAccLat               56236709962                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6232450000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26366.05                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::81920-86015            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           67807                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         67807                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.538219                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.057457                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.559402                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           64146     94.60%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1206      1.78%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             504      0.74%     97.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             212      0.31%     97.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             312      0.46%     97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             493      0.73%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             138      0.20%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.05%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              37      0.05%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              40      0.06%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              31      0.05%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              23      0.03%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             428      0.63%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              42      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              41      0.06%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              38      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              18      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             6      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            20      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           67807                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    45254251156                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73347376156                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7491500000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       30203.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45116.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.68                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.33                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  48953.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.02                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.02                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.59                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1009662                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    480836                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.00                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  48.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                     21250619.81                       # Average gap between requests
-system.physmem.pageHitRate                      66.89                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2808479520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1532404500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4673861400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3196149840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3096718466400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1173181763970                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27418066728000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31700177853630                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.611477                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45611956984095                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1583189400000                       # Time in different power states
+system.physmem.avgWrQLen                        23.61                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1205783                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    567891                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.75                       # Row buffer hit rate for writes
+system.physmem.avgGap                     17648699.37                       # Average gap between requests
+system.physmem.pageHitRate                      66.00                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3440351880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1877176125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5610742800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3866972400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3101308728960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1186805359620                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27448283421000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31751192752785                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.696261                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45662122488643                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1585536160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    216810169905                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    234575955107                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2768124240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1510385250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5048596800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3165006960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3096718466400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1175060323800                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27416418868500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31700689771950                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.622274                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45609169557313                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1583189400000                       # Time in different power states
+system.physmem_1.actEnergy                 3468270960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1892409750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6075934800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3839134320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3101308728960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1190698585875                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27444868310250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31752151374915                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.716450                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45656375341719                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1585536160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    219597434187                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    240323289781                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -362,18 +376,18 @@ system.realview.nvmem.bw_total::total              28                       # To
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              130279608                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         91518189                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6235368                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            97695080                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               70156250                       # Number of BTB hits
+system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
+system.cpu0.branchPred.lookups              141674450                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         99862421                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6468001                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           105068912                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               76755781                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.811446                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15568853                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1041049                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            73.052799                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               16951451                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1146227                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -404,61 +418,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   272738                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               272738                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8357                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        77299                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       272738                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         272738    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       272738                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        85656                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        84887     99.10%     99.10% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          657      0.77%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           28      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           42      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           27      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        85656                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   285287                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               285287                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10160                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        74871                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       285287                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         285287    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       285287                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        85031                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19876.756712                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18427.446368                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 12146.929549                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        81330     95.65%     95.65% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535         3040      3.58%     99.22% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303          313      0.37%     99.59% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          238      0.28%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           23      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           15      0.02%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375           17      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143           17      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           13      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        85031                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    669754704                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      669754704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    669754704                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        77299     90.24%     90.24% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         8357      9.76%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        85656                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       272738                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K        74871     88.05%     88.05% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10160     11.95%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        85031                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       285287                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       272738                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85656                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       285287                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85031                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85656                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       358394                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85031                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       370318                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    83911764                       # DTB read hits
-system.cpu0.dtb.read_misses                    226051                       # DTB read misses
-system.cpu0.dtb.write_hits                   74892635                       # DTB write hits
-system.cpu0.dtb.write_misses                    46687                       # DTB write misses
+system.cpu0.dtb.read_hits                    92463041                       # DTB read hits
+system.cpu0.dtb.read_misses                    237707                       # DTB read misses
+system.cpu0.dtb.write_hits                   80598198                       # DTB write hits
+system.cpu0.dtb.write_misses                    47580                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   35474                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1932                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  8858                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              41508                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   37525                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1680                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                 10312                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    11487                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                84137815                       # DTB read accesses
-system.cpu0.dtb.write_accesses               74939322                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10309                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                92700748                       # DTB read accesses
+system.cpu0.dtb.write_accesses               80645778                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        158804399                       # DTB hits
-system.cpu0.dtb.misses                         272738                       # DTB misses
-system.cpu0.dtb.accesses                    159077137                       # DTB accesses
+system.cpu0.dtb.hits                        173061239                       # DTB hits
+system.cpu0.dtb.misses                         285287                       # DTB misses
+system.cpu0.dtb.accesses                    173346526                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -488,190 +507,192 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    68078                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                68078                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          722                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61066                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        68078                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          68078    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        68078                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        61788                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        57025     92.29%     92.29% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         3907      6.32%     98.61% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          284      0.46%     99.07% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          503      0.81%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607            9      0.01%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           25      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    62168                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                62168                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          557                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        49936                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        62168                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          62168    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        62168                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        50493                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 22007.793159                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 20271.994764                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 13773.268921                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        46934     92.95%     92.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         2907      5.76%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          206      0.41%     99.12% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          384      0.76%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839            9      0.02%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           12      0.02%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           22      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            4      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        61788                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        50493                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    669040204                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      669040204    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    669040204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        61066     98.83%     98.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          722      1.17%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        61788                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        49936     98.90%     98.90% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          557      1.10%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        50493                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        68078                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        68078                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        62168                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        62168                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61788                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61788                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       129866                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   232943519                       # ITB inst hits
-system.cpu0.itb.inst_misses                     68078                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        50493                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        50493                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       112661                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   254201587                       # ITB inst hits
+system.cpu0.itb.inst_misses                     62168                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   25164                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              41508                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   26890                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   198596                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   207950                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               233011597                       # ITB inst accesses
-system.cpu0.itb.hits                        232943519                       # DTB hits
-system.cpu0.itb.misses                          68078                       # DTB misses
-system.cpu0.itb.accesses                    233011597                       # DTB accesses
-system.cpu0.numCycles                       944358949                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               254263755                       # ITB inst accesses
+system.cpu0.itb.hits                        254201587                       # DTB hits
+system.cpu0.itb.misses                          62168                       # DTB misses
+system.cpu0.itb.accesses                    254263755                       # DTB accesses
+system.cpu0.numCycles                      1026940097                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  433389926                       # Number of instructions committed
-system.cpu0.committedOps                    509312382                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     43329563                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     4813                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93880363578                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.179005                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.458925                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  473675073                       # Number of instructions committed
+system.cpu0.committedOps                    555986446                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     46253045                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     4767                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93938653200                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.168026                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.461249                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13422                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      695520331                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      248838618                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5405789                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          500.914885                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          150600436                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5406301                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.856465                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   15947                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      756887334                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      270052763                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5859905                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          507.688861                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          164189310                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5860417                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.016660                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       4974406000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.914885                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978349                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.978349                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.688861                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.991580                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.991580                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          405                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          408                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        320300004                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       320300004                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     77010804                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       77010804                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     69515704                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      69515704                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       254236                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       254236                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165535                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       165535                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1598340                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1598340                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1577518                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1577518                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    146526508                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       146526508                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    146780744                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      146780744                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3243116                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3243116                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2266198                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2266198                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       618205                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       618205                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       821296                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       821296                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       155401                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       155401                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       174722                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       174722                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5509314                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5509314                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6127519                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6127519                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  48375468500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  48375468500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  42499797000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  42499797000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  51670537000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  51670537000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2317304500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2317304500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3678685500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   3678685500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2406500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2406500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  90875265500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  90875265500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  90875265500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  90875265500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80253920                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     80253920                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     71781902                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     71781902                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       872441                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       872441                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       986831                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       986831                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1753741                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1753741                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1752240                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1752240                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    152035822                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    152035822                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    152908263                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    152908263                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040411                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.040411                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031571                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.031571                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.708592                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.708592                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.832256                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.832256                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088611                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088611                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099714                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099714                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036237                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.036237                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040073                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.040073                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14916.354672                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14916.354672                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18753.788063                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18753.788063                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62913.416113                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62913.416113                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14911.773412                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14911.773412                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21054.506588                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21054.506588                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        349055381                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       349055381                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     84695912                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       84695912                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     74803438                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      74803438                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       285827                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       285827                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       206325                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       206325                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1857926                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1857926                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1831957                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1831957                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    159499350                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       159499350                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    159785177                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      159785177                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3661656                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3661656                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2387103                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2387103                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       659778                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       659778                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       802996                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       802996                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       167218                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       167218                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       191201                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       191201                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      6048759                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       6048759                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6708537                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6708537                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54989546000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  54989546000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  45746153500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  45746153500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  55227374500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  55227374500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2454584500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2454584500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4061452500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4061452500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2247500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2247500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 100735699500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 100735699500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 100735699500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 100735699500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     88357568                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     88357568                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     77190541                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     77190541                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       945605                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       945605                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1009321                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1009321                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2025144                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2025144                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2023158                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2023158                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    165548109                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    165548109                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    166493714                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    166493714                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041441                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.041441                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030925                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.030925                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.697731                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.697731                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.795580                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.795580                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.082571                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.082571                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.094506                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.094506                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036538                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.036538                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040293                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.040293                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15017.671239                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15017.671239                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.879187                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.879187                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 68776.649572                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 68776.649572                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14678.949037                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14678.949037                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21241.795283                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21241.795283                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16494.842280                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16494.842280                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14830.678697                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14830.678697                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16653.944966                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16653.944966                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15016.045898                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15016.045898                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -680,161 +701,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3720174                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3720174                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       395501                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       395501                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       949612                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       949612                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           96                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total           96                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41791                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41791                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           77                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           77                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1345113                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1345113                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1345113                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1345113                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2847615                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2847615                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1316586                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1316586                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       612491                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       612491                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       821200                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       821200                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113610                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113610                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       174645                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       174645                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4164201                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4164201                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4776692                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4776692                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        30167                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        29885                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60052                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38218904500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  38218904500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  23577025500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  23577025500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13456556000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13456556000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  50843266000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  50843266000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1513106500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1513106500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3501575000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3501575000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2054500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2054500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61795930000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  61795930000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75252486000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  75252486000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5426212000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5426212000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5134567500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5134567500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10560779500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10560779500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035483                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035483                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018341                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018341                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.702043                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.702043                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.832159                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.832159                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064782                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064782                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099670                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099670                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027390                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027390                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031239                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031239                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3953843                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3953843                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       461349                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       461349                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       989528                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       989528                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data          101                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total          101                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43137                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43137                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           40                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           40                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1450877                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1450877                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1450877                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1450877                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3200307                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3200307                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1397575                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1397575                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       654192                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       654192                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       802895                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       802895                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       124081                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       124081                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       191161                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       191161                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4597882                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4597882                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5252074                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5252074                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32791                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32791                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        32852                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        32852                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        65643                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        65643                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43347515000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43347515000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25679741500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  25679741500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14396564000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14396564000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  54417843000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  54417843000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1641270500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1641270500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3869107000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3869107000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2035000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2035000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  69027256500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  69027256500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  83423820500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  83423820500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5925160000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5925160000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5714063000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5714063000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11639223000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11639223000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036220                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036220                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018106                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018106                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.691824                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.691824                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.795480                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.795480                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061270                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061270                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.094486                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.094486                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027774                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027774                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031545                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031545                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13544.798983                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13544.798983                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18374.499759                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18374.499759                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22006.634138                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22006.634138                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 67777.035602                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 67777.035602                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13227.411933                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13227.411933                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20240.043733                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20240.043733                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15012.837759                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15012.837759                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15883.976597                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15883.976597                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180694.702815                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180694.702815                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173933.489590                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173933.489590                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177310.954710                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177310.954710                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          9471710                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.926461                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          223265309                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9472222                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            23.570532                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      29829927000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.926461                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999856                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999856                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         10143465                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.926573                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          243844472                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         10143977                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            24.038350                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      29838959000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.926573                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999857                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999857                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        474947313                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       474947313                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    223265309                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      223265309                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    223265309                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       223265309                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    223265309                       # number of overall hits
-system.cpu0.icache.overall_hits::total      223265309                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9472232                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9472232                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9472232                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9472232                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9472232                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9472232                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93317915500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  93317915500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  93317915500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  93317915500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  93317915500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  93317915500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    232737541                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    232737541                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    232737541                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    232737541                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    232737541                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    232737541                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040699                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.040699                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040699                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.040699                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040699                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.040699                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9851.734575                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9851.734575                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9851.734575                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9851.734575                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9851.734575                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9851.734575                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        518120904                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       518120904                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    243844472                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      243844472                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    243844472                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       243844472                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    243844472                       # number of overall hits
+system.cpu0.icache.overall_hits::total      243844472                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst     10143987                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     10143987                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst     10143987                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      10143987                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst     10143987                       # number of overall misses
+system.cpu0.icache.overall_misses::total     10143987                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100406017500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 100406017500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 100406017500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 100406017500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 100406017500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 100406017500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    253988459                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    253988459                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    253988459                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    253988459                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    253988459                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    253988459                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039939                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.039939                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039939                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.039939                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039939                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.039939                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9898.082233                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9898.082233                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9898.082233                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9898.082233                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9898.082233                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9898.082233                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -843,256 +864,258 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9472232                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9472232                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9472232                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9472232                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9472232                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9472232                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst     10143987                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10143987                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst     10143987                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10143987                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst     10143987                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10143987                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        52292                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        52292                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  88581800000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  88581800000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  88581800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  88581800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  88581800000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  88581800000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  95334024500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  95334024500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  95334024500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  95334024500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  95334024500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  95334024500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4777780500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4777780500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   4777780500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040699                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.040699                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040699                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.040699                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9351.734628                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9351.734628                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9351.734628                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9351.734628                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039939                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039939                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039939                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.039939                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039939                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.039939                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9398.082283                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9398.082283                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9398.082283                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9398.082283                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9398.082283                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9398.082283                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7001248                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7002240                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          870                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7957449                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7958709                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         1099                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       934040                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2602937                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16189.396586                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          26055882                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2619045                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            9.948619                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     27364878000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6164.786775                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    75.653187                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.660205                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5461.877118                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3523.510222                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   883.909079                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.376269                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004618                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004862                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.333367                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.215058                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.053950                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.988122                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1484                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14552                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          652                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          737                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           69                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           56                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu0.l2cache.prefetcher.pfSpanPage      1036699                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2852729                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16231.938482                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          28072062                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2868819                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            9.785233                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle     27361359000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  6837.547665                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    84.005962                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    92.461189                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5084.590207                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3169.997386                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   963.336073                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.417331                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005127                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005643                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.310339                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.193481                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.058797                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.990719                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1316                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14706                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           30                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          157                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          636                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          493                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           19                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           23                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1133                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5245                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7645                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          403                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.090576                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.888184                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       499794711                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      499794711                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       477670                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       164902                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        642572                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3720171                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3720171                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       100086                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       100086                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        33531                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        33531                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       842117                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       842117                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8718803                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      8718803                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2638824                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2638824                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       235281                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       235281                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       477670                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       164902                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      8718803                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3480941                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       12842316                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       477670                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       164902                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      8718803                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3480941                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      12842316                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10606                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7872                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        18478                       # number of ReadReq misses
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1121                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2596                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5686                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5177                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.080322                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.897583                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       536564472                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      536564472                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       494323                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       145712                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        640035                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      3953840                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3953840                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       100741                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total       100741                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        34053                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        34053                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       910402                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       910402                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      9335111                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      9335111                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2958514                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2958514                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       184784                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       184784                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       494323                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       145712                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      9335111                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3868916                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       13844062                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       494323                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       145712                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      9335111                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3868916                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      13844062                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11152                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7425                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        18577                       # number of ReadReq misses
 system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
 system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       123653                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       123653                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       141112                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       141112                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       262527                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       262527                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       753428                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       753428                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       934617                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       934617                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       584428                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       584428                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10606                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7872                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       753428                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1197144                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1969050                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10606                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7872                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       753428                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1197144                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1969050                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    328744000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    264590000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    593334000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2720179500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2720179500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2942818999                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2942818999                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1986000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1986000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12019318999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  12019318999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22377694500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22377694500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  30534644990                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  30534644990                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  47939774000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  47939774000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    328744000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    264590000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22377694500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  42553963989                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  65524992489                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    328744000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    264590000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22377694500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  42553963989                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  65524992489                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       488276                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       172774                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       661050                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3720172                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3720172                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       223739                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       223739                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       174643                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       174643                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1104644                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1104644                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9472231                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      9472231                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3573441                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3573441                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       819709                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       819709                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       488276                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       172774                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      9472231                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4678085                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     14811366                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       488276                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       172774                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      9472231                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4678085                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     14811366                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.027952                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       135342                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       135342                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       157102                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       157102                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            6                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       262550                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       262550                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       808875                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       808875                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1019727                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1019727                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       616671                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       616671                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11152                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7425                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       808875                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1282277                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2109729                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11152                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7425                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       808875                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1282277                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2109729                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    358336500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    254237500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    612574000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2939782500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2939782500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3277538000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3277538000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1967998                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1967998                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13250524998                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  13250524998                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  24450345500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  24450345500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  34035221991                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  34035221991                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  51883476000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  51883476000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    358336500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    254237500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  24450345500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  47285746989                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  72348666489                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    358336500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    254237500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  24450345500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  47285746989                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  72348666489                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       505475                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       153137                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       658612                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      3953841                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3953841                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       236083                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       236083                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       191155                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       191155                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1172952                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1172952                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst     10143986                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total     10143986                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3978241                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3978241                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       801455                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       801455                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       505475                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       153137                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst     10143986                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5151193                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     15953791                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       505475                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       153137                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst     10143986                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5151193                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     15953791                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022062                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.048486                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.028206                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
 system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.552666                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.552666                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.808003                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.808003                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.573281                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.573281                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.821857                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.821857                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.237658                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.237658                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.079541                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.079541                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.261545                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.261545                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.712970                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.712970                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.079541                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.255905                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.132942                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021721                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.045562                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.079541                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.255905                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.132942                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32110.293322                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21998.491747                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21998.491747                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20854.491461                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20854.491461                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       993000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       993000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45783.172775                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45783.172775                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29701.171844                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29701.171844                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32670.757102                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32670.757102                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 82028.537305                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 82028.537305                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29701.171844                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35546.236701                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 33277.465016                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30996.039977                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33611.534553                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29701.171844                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35546.236701                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 33277.465016                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.223837                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.223837                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.079739                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.079739                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.256326                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.256326                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.769439                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.769439                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022062                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.048486                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.079739                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.248928                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.132240                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022062                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.048486                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.079739                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.248928                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.132240                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32132.039096                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34240.740741                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32974.861388                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21721.139779                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21721.139779                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20862.484246                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20862.484246                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 327999.666667                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 327999.666667                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50468.577406                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50468.577406                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30227.594499                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30227.594499                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33376.797899                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33376.797899                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 84134.775269                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 84134.775269                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32132.039096                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34240.740741                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30227.594499                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36876.390194                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 34292.871970                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32132.039096                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34240.740741                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30227.594499                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36876.390194                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 34292.871970                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1101,240 +1124,238 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1330364                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1330364                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5123                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5123                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           12                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          628                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          628                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            2                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5751                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         5765                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           12                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5751                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         5765                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10606                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7870                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        18476                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1435907                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1435907                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         7822                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         7822                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            7                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          800                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          800                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            7                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         8622                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         8630                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            7                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         8622                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         8630                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11152                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7424                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        18576                       # number of ReadReq MSHR misses
 system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
 system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       106526                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total       106526                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       667181                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       667181                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       123653                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123653                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       141112                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       141112                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       257404                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       257404                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       753416                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       753416                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       933989                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       933989                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       584426                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       584426                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10606                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7870                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       753416                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1191393                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1963285                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10606                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7870                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       753416                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1191393                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       667181                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2630466                       # number of overall MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       115899                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total       115899                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       744785                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       744785                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       135342                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       135342                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       157102                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       157102                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       254728                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       254728                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       808868                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       808868                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1018927                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1018927                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       616671                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       616671                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11152                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7424                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       808868                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1273655                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      2101099                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        11152                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7424                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       808868                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1273655                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       744785                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2845884                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        82459                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        29885                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32791                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        85083                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        32852                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        32852                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       112344                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    482440000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  24692938914                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  24692938914                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2507267996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2507267996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2173502999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2173502999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1716000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1716000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   9909956499                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9909956499                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17856881500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17856881500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  24870500990                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  24870500990                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  44433114500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  44433114500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17856881500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  34780457489                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  53119778989                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    265108000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    217332000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17856881500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  34780457489                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  24692938914                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  77812717903                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        65643                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       117935                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    291424500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    209670500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    501095000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  33786234533                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  33786234533                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2742370498                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2742370498                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2416828000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2416828000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1703998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1703998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10773413498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10773413498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  19596844500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  19596844500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27840391991                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27840391991                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  48183450000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  48183450000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    291424500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    209670500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19596844500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  38613805489                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  58711744989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    291424500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    209670500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  19596844500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  38613805489                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  33786234533                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  92497979522                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5184743000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9544187500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4910404000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4910404000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5662672500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10022117000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5467648500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5467648500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4359444500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10095147000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14454591500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027949                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11130321000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15489765500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022062                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.048479                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028205                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.552666                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.552666                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.808003                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808003                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.573281                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.573281                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.821857                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.821857                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233020                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233020                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079539                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.261370                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261370                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.712968                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.712968                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.254675                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.132553                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021721                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.045551                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079539                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.254675                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.217168                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.217168                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.079739                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079739                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.256125                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.256125                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.769439                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.769439                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022062                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.048479                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079739                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.247254                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.131699                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022062                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.048479                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079739                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.247254                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177598                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26111.712492                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37010.854497                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20276.645096                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20276.645096                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15402.680134                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15402.680134                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       858000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       858000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38499.621214                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38499.621214                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23701.224158                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.178383                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26975.398363                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45363.741930                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20262.523814                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20262.523814                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15383.814337                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15383.814337                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 283999.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 283999.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42293.793764                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42293.793764                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24227.493856                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24227.493856                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27323.244934                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27323.244934                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 78134.775269                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 78134.775269                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24227.493856                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30317.319438                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27943.350118                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24227.493856                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30317.319438                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32502.371679                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172689.838675                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117792.238167                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166432.743821                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166432.743821                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169558.383986                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 131341.548311                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        876246                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     14005082                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38305                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        29885                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      6885213                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict     13979886                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       878417                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       473566                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       319318                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       460407                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1465787                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1113779                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9472232                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5781099                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       926693                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       819709                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28518742                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17480007                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       376075                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1070420                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         47445244                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    609569408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    544120273                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1382192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3906208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1158978081                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                   10243316                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     41099849                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.261354                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.439372                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq        878258                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     15087550                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        37855                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        32852                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      7538926                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict     15047066                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       979875                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       473443                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       345382                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       491005                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          110                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1529585                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1182209                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq     10143987                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6286308                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       908183                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       801455                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     30533828                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18915495                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       338792                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1107688                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         50895803                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    652561728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    589425738                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1225096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4043800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1247256362                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   11033818                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     44172113                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.260955                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.439155                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          30358253     73.86%     73.86% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2          10741596     26.14%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          32645184     73.90%     73.90% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2          11526929     26.10%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      41099849                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   19306972981                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      44172113                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   20686801483                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    182073987                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    184431489                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  14288744572                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  15296388050                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7674112954                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8393036752                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    203313475                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    185661487                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    582176435                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    602239946                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              125904408                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         89122664                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5902634                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            94266188                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               68486701                       # Number of BTB hits
+system.cpu1.branchPred.lookups              126920633                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         90998639                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5685011                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            95306954                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               70103943                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.652456                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               15015861                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1004863                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.555958                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               14523133                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            944517                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1364,65 +1385,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   261999                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               261999                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7478                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        69980                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       261999                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         261999    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       261999                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        77458                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        74315     95.94%     95.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         2659      3.43%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          247      0.32%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          165      0.21%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           17      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607            5      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           16      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143            8      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           10      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        77458                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -1501931648                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1501931648    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -1501931648                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        69980     90.35%     90.35% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         7478      9.65%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        77458                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       261999                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   273163                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               273163                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10101                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        83297                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       273163                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         273163    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       273163                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        93398                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20769.759524                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.534327                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 16072.129923                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        92090     98.60%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1102      1.18%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           44      0.05%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           68      0.07%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           64      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           17      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        93398                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1497259648                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1497259648    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1497259648                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        83297     89.18%     89.18% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        10101     10.82%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        93398                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       273163                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       261999                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        77458                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       273163                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        93398                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        77458                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       339457                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        93398                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       366561                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    82663207                       # DTB read hits
-system.cpu1.dtb.read_misses                    218762                       # DTB read misses
-system.cpu1.dtb.write_hits                   71167787                       # DTB write hits
-system.cpu1.dtb.write_misses                    43237                       # DTB write misses
+system.cpu1.dtb.read_hits                    80454143                       # DTB read hits
+system.cpu1.dtb.read_misses                    224980                       # DTB read misses
+system.cpu1.dtb.write_hits                   71458601                       # DTB write hits
+system.cpu1.dtb.write_misses                    48183                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   35788                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      902                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6887                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              41508                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   37844                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      998                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  7832                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9904                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                82881969                       # DTB read accesses
-system.cpu1.dtb.write_accesses               71211024                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11981                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                80679123                       # DTB read accesses
+system.cpu1.dtb.write_accesses               71506784                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        153830994                       # DTB hits
-system.cpu1.dtb.misses                         261999                       # DTB misses
-system.cpu1.dtb.accesses                    154092993                       # DTB accesses
+system.cpu1.dtb.hits                        151912744                       # DTB hits
+system.cpu1.dtb.misses                         273163                       # DTB misses
+system.cpu1.dtb.accesses                    152185907                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1452,191 +1469,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    59152                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                59152                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          461                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        48561                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        59152                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          59152    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        59152                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        49022                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        45897     93.63%     93.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         2624      5.35%     98.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          160      0.33%     99.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          295      0.60%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607            9      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           10      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        49022                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1502514148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1502514148    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1502514148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        48561     99.06%     99.06% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          461      0.94%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        49022                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    69906                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                69906                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          595                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        61795                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        69906                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          69906    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        69906                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        62390                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 23626.751082                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21282.847568                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17788.570372                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        60952     97.70%     97.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1278      2.05%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607           47      0.08%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           79      0.13%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        62390                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1498102148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1498102148    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1498102148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        61795     99.05%     99.05% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          595      0.95%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        62390                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        59152                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        59152                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        69906                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        69906                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49022                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49022                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       108174                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   225695696                       # ITB inst hits
-system.cpu1.itb.inst_misses                     59152                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        62390                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        62390                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       132296                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   226287653                       # ITB inst hits
+system.cpu1.itb.inst_misses                     69906                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              38178                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1015                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   25916                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              41508                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1042                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26941                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   201769                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   214530                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               225754848                       # ITB inst accesses
-system.cpu1.itb.hits                        225695696                       # DTB hits
-system.cpu1.itb.misses                          59152                       # DTB misses
-system.cpu1.itb.accesses                    225754848                       # DTB accesses
-system.cpu1.numCycles                       837975509                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               226357559                       # ITB inst accesses
+system.cpu1.itb.hits                        226287653                       # DTB hits
+system.cpu1.itb.misses                          69906                       # DTB misses
+system.cpu1.itb.accesses                    226357559                       # DTB accesses
+system.cpu1.numCycles                       843613035                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  416666374                       # Number of instructions committed
-system.cpu1.committedOps                    490559113                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     42698463                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     4659                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93986622085                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.011143                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.497230                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  411727692                       # Number of instructions committed
+system.cpu1.committedOps                    485444606                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     45963671                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5033                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 94121734017                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.048959                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.488053                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5009                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      670350336                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      167625173                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          4806043                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          444.186980                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          146495712                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          4806555                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            30.478318                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8387638822500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   444.186980                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.867553                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.867553                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        309963007                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       309963007                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     75874550                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       75874550                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     66435000                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      66435000                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       232604                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       232604                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       157450                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       157450                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1693988                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1693988                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1671438                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1671438                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    142309550                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       142309550                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    142542154                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      142542154                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3161753                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3161753                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1996683                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1996683                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       552089                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       552089                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       421817                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       421817                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       158395                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       158395                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       179133                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       179133                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5158436                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5158436                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5710525                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5710525                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43703345000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  43703345000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  33230827500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  33230827500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  13699084500                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  13699084500                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2222797000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2222797000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3749543500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   3749543500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3215500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3215500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  76934172500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  76934172500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  76934172500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  76934172500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     79036303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     79036303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     68431683                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     68431683                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       784693                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       784693                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       579267                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       579267                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1852383                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1852383                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1850571                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1850571                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    147467986                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    147467986                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    148252679                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    148252679                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040004                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.040004                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029178                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029178                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.703573                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.703573                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.728191                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.728191                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.085509                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.085509                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096799                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096799                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034980                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.034980                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.038519                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.038519                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13822.504478                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13822.504478                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16643.016192                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16643.016192                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32476.368899                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 32476.368899                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14033.252312                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14033.252312                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20931.617848                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20931.617848                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    5855                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      670689322                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      172923713                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          4998697                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          442.736384                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          144280355                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4999208                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.860643                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8387679361000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   442.736384                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.864720                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.864720                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        306336541                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       306336541                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     73634827                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       73634827                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     66559153                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      66559153                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       217159                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       217159                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       114949                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       114949                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1666179                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1666179                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1632337                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1632337                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    140193980                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       140193980                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    140411139                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      140411139                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3169592                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3169592                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2202884                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2202884                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       634590                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       634590                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       446274                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       446274                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       155480                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       155480                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       187648                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       187648                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5372476                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5372476                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6007066                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6007066                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  46997405500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  46997405500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  36924614000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  36924614000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  13123924500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  13123924500                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2384254000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2384254000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3955578000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3955578000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3296000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3296000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  83922019500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  83922019500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  83922019500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  83922019500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     76804419                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     76804419                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     68762037                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     68762037                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       851749                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       851749                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       561223                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       561223                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1821659                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1821659                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1819985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1819985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    145566456                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    145566456                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    146418205                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    146418205                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041268                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.041268                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.032036                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.032036                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.745043                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.745043                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.795181                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.795181                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.085351                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.085351                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103104                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103104                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036907                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.036907                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041027                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.041027                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14827.588377                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14827.588377                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16761.942072                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16761.942072                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 29407.773027                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 29407.773027                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15334.795472                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15334.795472                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21079.777029                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21079.777029                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15620.734183                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15620.734183                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13970.550598                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13970.550598                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1645,161 +1658,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3028608                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3028608                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       352163                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       352163                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       814004                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       814004                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        37997                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        37997                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           57                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           57                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1166167                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1166167                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1166167                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1166167                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2809590                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2809590                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1182679                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1182679                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       551754                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       551754                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       421759                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       421759                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120398                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120398                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       179076                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       179076                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      3992269                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      3992269                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4544023                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4544023                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8249                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8249                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         8420                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        16669                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        16669                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  35216853500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  35216853500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  19067594000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  19067594000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11091696000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11091696000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  13273963000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  13273963000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1514299000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1514299000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3568894000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3568894000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2841500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2841500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  54284447500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  54284447500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  65376143500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  65376143500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1096081500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1096081500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1226588000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1226588000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2322669500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2322669500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035548                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035548                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017283                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017283                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.703146                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.703146                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.728091                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.728091                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064996                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064996                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096768                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096768                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027072                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027072                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030651                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.030651                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3232302                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3232302                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       357442                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       357442                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       916671                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       916671                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           62                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total           62                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        39535                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        39535                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           40                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           40                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1274113                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1274113                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1274113                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1274113                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2812150                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2812150                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1286213                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1286213                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       634154                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       634154                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       446212                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       446212                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       115945                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       115945                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       187608                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       187608                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4098363                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4098363                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4732517                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4732517                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5214                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5214                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5003                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5003                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10217                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10217                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  37676406000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  37676406000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20748839500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20748839500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13118141500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13118141500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  12673625000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  12673625000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1579299000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1579299000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3766730000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3766730000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3027000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3027000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  58425245500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  58425245500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  71543387000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  71543387000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    574067000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    574067000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    612660500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    612660500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1186727500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1186727500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036614                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036614                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018705                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018705                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.744532                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.744532                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.795071                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.795071                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063648                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063648                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103082                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103082                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028155                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.028155                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032322                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.032322                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13397.722739                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13397.722739                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16131.728959                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16131.728959                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20686.050234                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20686.050234                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 28402.698717                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 28402.698717                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13621.104834                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13621.104834                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20077.661933                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20077.661933                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14255.751748                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14255.751748                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15117.407291                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15117.407291                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110101.074031                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110101.074031                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 122458.624825                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 122458.624825                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116152.246256                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116152.246256                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          8962341                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          506.974355                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          216525917                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          8962853                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            24.158147                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8375817756000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.974355                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990184                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990184                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          8492244                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          506.981743                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          217573051                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          8492756                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.618663                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8375822912000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.981743                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990199                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990199                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          221                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        459940393                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       459940393                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    216525917                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      216525917                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    216525917                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       216525917                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    216525917                       # number of overall hits
-system.cpu1.icache.overall_hits::total      216525917                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      8962853                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      8962853                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      8962853                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       8962853                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      8962853                       # number of overall misses
-system.cpu1.icache.overall_misses::total      8962853                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  87475415500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  87475415500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  87475415500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  87475415500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  87475415500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  87475415500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    225488770                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    225488770                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    225488770                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    225488770                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    225488770                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    225488770                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.039749                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.039749                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.039749                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.039749                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.039749                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.039749                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9759.773534                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9759.773534                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9759.773534                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9759.773534                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9759.773534                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9759.773534                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        460624372                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       460624372                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    217573051                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      217573051                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    217573051                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       217573051                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    217573051                       # number of overall hits
+system.cpu1.icache.overall_hits::total      217573051                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      8492757                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      8492757                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      8492757                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       8492757                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      8492757                       # number of overall misses
+system.cpu1.icache.overall_misses::total      8492757                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  83328642500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  83328642500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  83328642500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  83328642500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  83328642500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  83328642500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    226065808                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    226065808                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    226065808                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    226065808                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    226065808                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    226065808                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037568                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.037568                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037568                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.037568                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037568                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.037568                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9811.730455                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9811.730455                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9811.730455                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9811.730455                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9811.730455                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9811.730455                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1808,254 +1821,257 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8962853                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      8962853                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      8962853                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      8962853                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      8962853                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      8962853                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8492757                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      8492757                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      8492757                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      8492757                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      8492757                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      8492757                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           93                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           93                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  82993989000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  82993989000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  82993989000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  82993989000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  82993989000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  82993989000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8742000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8742000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8742000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.039749                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.039749                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.039749                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.039749                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9259.773534                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9259.773534                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9259.773534                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9259.773534                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        94000                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        94000                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        94000                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  79082264500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  79082264500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  79082264500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  79082264500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  79082264500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  79082264500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8371000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8371000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8371000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8371000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037568                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037568                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037568                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.037568                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037568                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.037568                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9311.730513                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9311.730513                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9311.730513                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9311.730513                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9311.730513                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9311.730513                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90010.752688                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90010.752688                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6768411                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6768469                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           54                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6929819                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6929951                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          118                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       863435                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2141720                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13540.912612                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          24731326                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2157705                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           11.461866                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9851161667500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5143.146487                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    72.763483                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.029020                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4350.990102                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3012.175036                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   886.808482                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.313913                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004441                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004579                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.265563                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.183849                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.054126                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.826472                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1213                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14689                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           25                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          401                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          707                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           75                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           53                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          662                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5268                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8016                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          626                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074036                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.896545                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       461861904                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      461861904                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       450787                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       134849                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        585636                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3028606                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3028606                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        55878                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        55878                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        34341                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        34341                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       766672                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       766672                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8228059                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      8228059                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2592448                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2592448                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       167873                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       167873                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       450787                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       134849                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      8228059                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3359120                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       12172815                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       450787                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       134849                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      8228059                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3359120                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      12172815                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10577                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7168                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        17745                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       137373                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       137373                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       144729                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       144729                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.prefetcher.pfSpanPage       828225                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2217454                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13495.655652                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          24120573                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2233034                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           10.801704                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10014360255000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5089.747096                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    72.528183                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    67.846494                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3761.982865                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3615.755476                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   887.795537                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.310654                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004427                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004141                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.229613                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.220688                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.054187                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.823709                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1264                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           84                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14232                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          220                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          713                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          323                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           63                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5272                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5785                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2792                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.077148                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005127                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.868652                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       454838713                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      454838713                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       490664                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       168334                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        658998                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3232300                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3232300                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        70185                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        70185                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        33315                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        33315                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       851172                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       851172                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      7787132                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      7787132                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2622380                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2622380                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       211432                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       211432                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       490664                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       168334                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      7787132                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3473552                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       11919682                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       490664                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       168334                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      7787132                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3473552                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      11919682                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11999                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9044                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        21043                       # number of ReadReq misses
+system.cpu1.l2cache.Writeback_misses::writebacks            2                       # number of Writeback misses
+system.cpu1.l2cache.Writeback_misses::total            2                       # number of Writeback misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       130491                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       130491                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       154287                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       154287                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       224779                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       224779                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       734794                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       734794                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       888888                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       888888                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       252467                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       252467                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10577                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7168                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       734794                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1113667                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1866206                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10577                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7168                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       734794                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1113667                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1866206                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    295249500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    216312000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    511561500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2960853000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2960853000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2990715499                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2990715499                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2750499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2750499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   8344875497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   8344875497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20496216000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20496216000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  25619176492                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  25619176492                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  11469563500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  11469563500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    295249500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    216312000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20496216000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  33964051989                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  54971829489                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    295249500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    216312000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20496216000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  33964051989                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  54971829489                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       461364                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       142017                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       603381                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3028606                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3028606                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       193251                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       193251                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       179070                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       179070                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       236022                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       236022                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       705624                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       705624                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       939588                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       939588                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       233719                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       233719                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11999                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9044                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       705624                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1175610                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1902277                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11999                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9044                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       705624                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1175610                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1902277                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    460284000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    375161500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    835445500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2824238500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2824238500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3183877499                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3183877499                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2927500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2927500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9419253499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   9419253499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  19920417000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  19920417000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  29851836990                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  29851836990                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  10546903000                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  10546903000                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    460284000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    375161500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  19920417000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  39271090489                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  60026952989                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    460284000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    375161500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  19920417000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  39271090489                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  60026952989                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       502663                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       177378                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       680041                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3232302                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3232302                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       200676                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       200676                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       187602                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       187602                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data       991451                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total       991451                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8962853                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      8962853                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3481336                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3481336                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       420340                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       420340                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       461364                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       142017                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      8962853                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4472787                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     14039021                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       461364                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       142017                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      8962853                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4472787                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     14039021                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.029409                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.710853                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.710853                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.808226                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.808226                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1087194                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1087194                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8492756                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      8492756                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3561968                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3561968                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       445151                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       445151                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       502663                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       177378                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      8492756                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4649162                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     13821959                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       502663                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       177378                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      8492756                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4649162                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     13821959                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023871                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050987                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.030944                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.650257                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.650257                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.822417                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.822417                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.226717                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.226717                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.081982                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.081982                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.255330                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.255330                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.600626                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.600626                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.081982                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.248987                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.132930                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022925                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050473                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.081982                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.248987                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.132930                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28828.486898                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21553.383853                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21553.383853                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20664.244892                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20664.244892                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 458416.500000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 458416.500000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37124.800346                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37124.800346                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 27893.826025                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 27893.826025                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 28821.602375                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 28821.602375                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45429.951241                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45429.951241                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27893.826025                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30497.493406                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 29456.463804                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 27914.295169                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 30177.455357                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27893.826025                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30497.493406                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 29456.463804                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.217093                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.217093                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.083085                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.083085                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.263783                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.263783                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.525033                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.525033                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023871                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050987                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.083085                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.252865                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.137627                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023871                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050987                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.083085                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.252865                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.137627                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38360.196683                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41481.811146                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39701.824835                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21643.166962                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21643.166962                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20636.071082                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20636.071082                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 487916.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 487916.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39908.370826                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39908.370826                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28230.923268                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28230.923268                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31771.198642                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31771.198642                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45126.425323                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45126.425323                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38360.196683                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41481.811146                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28230.923268                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33404.862573                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 31555.316596                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38360.196683                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41481.811146                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28230.923268                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33404.862573                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 31555.316596                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2064,232 +2080,237 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       853283                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          853283                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3653                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         3653                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          365                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          365                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4018                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         4025                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            5                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4018                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         4025                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10577                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7166                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        17743                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       103597                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total       103597                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       615258                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       615258                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       137373                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       137373                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       144729                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       144729                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.writebacks::writebacks       960235                       # number of writebacks
+system.cpu1.l2cache.writebacks::total          960235                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            3                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6240                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         6240                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          370                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          370                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            4                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            4                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            3                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         6610                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         6614                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            3                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         6610                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         6614                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11999                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9041                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        21040                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::writebacks            2                       # number of Writeback MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::total            2                       # number of Writeback MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       104712                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total       104712                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       691959                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       691959                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       130491                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       130491                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       154287                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       154287                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       221126                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       221126                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       734789                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       734789                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       888523                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       888523                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       252467                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       252467                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10577                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7166                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       734789                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1109649                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1862181                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10577                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7166                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       734789                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1109649                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       615258                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2477439                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       229782                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       229782                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       705623                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       705623                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       939218                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       939218                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       233715                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       233715                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11999                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9041                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       705623                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1169000                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1895663                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11999                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9041                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       705623                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1169000                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       691959                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2587622                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         8249                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         8342                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         8420                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5214                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5307                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         5003                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         5003                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        16669                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        16762                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    405072000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  18848278545                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  18848278545                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2780289998                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2780289998                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2207149499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2207149499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2390499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2390499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   6581571997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6581571997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  16087394500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  16087394500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  20254649492                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  20254649492                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   9954761500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   9954761500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16087394500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  26836221489                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  43328687989                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    231787500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    173284500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16087394500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  26836221489                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  18848278545                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  62176966534                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7998000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1030068000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1038066000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1163435000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1163435000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7998000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2193503000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2201501000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029406                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10217                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10310                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    388290000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    320879500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    709169500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  28798715692                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  28798715692                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2619056498                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2619056498                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2341678999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2341678999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2531500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2531500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7275794499                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7275794499                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  15686656500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  15686656500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  24180303490                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  24180303490                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   9143886000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   9143886000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    388290000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    320879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  15686656500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  31456097989                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  47851923989                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    388290000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    320879500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  15686656500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  31456097989                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  28798715692                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  76650639681                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7627000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    532300500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    539927500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    575129000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    575129000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7627000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1107429500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1115056500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023871                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050970                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.030939                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.710853                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.710853                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808226                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808226                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.650257                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.650257                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.822417                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.822417                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.223033                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.223033                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.081982                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.255225                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255225                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.600626                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.600626                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.248089                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132643                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022925                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050459                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.081982                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.248089                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.211353                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.211353                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.083085                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.083085                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.263680                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.263680                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.525024                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.525024                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023871                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050970                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.083085                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.251443                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.137149                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023871                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050970                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.083085                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.251443                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.176468                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22829.961111                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30634.755737                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20238.984356                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20238.984356                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22795.864026                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39429.951241                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39429.951241                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24184.423623                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23267.710276                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        86000                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        86000                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.187211                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33705.774715                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41619.107045                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20070.782644                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20070.782644                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15177.422589                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.422589                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 421916.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 421916.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31663.900997                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31663.900997                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22230.931390                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22230.931390                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25745.144886                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25745.144886                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39124.087029                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39124.087029                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22230.931390                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26908.552600                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25242.843263                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22230.931390                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26908.552600                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29622.038954                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102090.621404                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101738.741285                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114956.825904                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 114956.825904                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 108390.868161                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108152.909796                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        832335                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     13281124                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38305                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         8420                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      6193652                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict     13562835                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       802874                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq        900589                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     12966269                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        37855                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         5003                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      6817398                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict     13255066                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       909243                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       426908                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       320139                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       432313                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1723284                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp       998712                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8962853                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5808138                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       527324                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       420340                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     26886674                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15523980                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       318688                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1026227                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         43755569                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    573628544                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    486175782                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1136136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3690912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1064631374                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   10738560                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     39200977                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.285389                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.451600                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       440871                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       344666                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       456246                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           50                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          110                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1853750                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1095537                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8492756                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6090536                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       551879                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       445151                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     25476691                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16156139                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       386266                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1103974                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         43123070                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    543542336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    511133259                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1419024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4021304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1060115923                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   11712363                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     39696559                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.307834                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.461597                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          28013450     71.46%     71.46% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2          11187527     28.54%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          27476611     69.22%     69.22% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          12219948     30.78%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      39200977                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   17410316483                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      39696559                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   17378215985                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    171564976                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    190636988                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  13446378573                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  12741161217                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7120820957                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7401084853                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    176677986                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    208902970                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    564893937                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    601334453                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40371                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40371                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136979                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136979                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47802                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40366                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40366                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136635                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136635                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47764                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2299,18 +2320,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231676                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231676                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122698                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231224                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231224                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354700                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47822                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354002                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47784                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2320,18 +2341,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155959                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355056                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355056                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155805                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338912                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7513101                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36314000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496803                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36259000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2351,7 +2372,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            22142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2359,71 +2380,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           570865133                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569722386                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92952000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92794000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148116000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147920000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115819                       # number of replacements
-system.iocache.tags.tagsinuse               11.287255                       # Cycle average of tags in use
+system.iocache.tags.replacements               115594                       # number of replacements
+system.iocache.tags.tagsinuse               11.293777                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115835                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115610                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9174218723000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.836610                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.450645                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239788                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.465665                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705453                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9174240356000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.830924                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.462853                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.239433                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466428                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705861                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1042899                       # Number of tag accesses
-system.iocache.tags.data_accesses             1042899                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040865                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040865                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8854                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8891                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8884                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8921                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8854                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8894                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8884                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8924                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8854                       # number of overall misses
-system.iocache.overall_misses::total             8894                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8884                       # number of overall misses
+system.iocache.overall_misses::total             8924                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1658968057                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1664163057                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1643383037                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1648578037                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12654105076                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12654105076                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12626572349                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12626572349                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1658968057                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1664532057                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1643383037                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1648947037                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1658968057                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1664532057                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1643383037                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1648947037                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8854                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8891                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8884                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8921                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8854                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8894                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8884                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8924                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8854                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8894                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8884                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8924                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2438,54 +2459,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 187173.890114                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184982.331945                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 184797.448380                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118306.089770                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118306.089770                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 187369.331037                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 187152.243872                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 184982.331945                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 184776.673801                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 187369.331037                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 187152.243872                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32802                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 184982.331945                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 184776.673801                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32047                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3449                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3474                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.510583                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.224813                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106950                       # number of writebacks
-system.iocache.writebacks::total               106950                       # number of writebacks
+system.iocache.writebacks::writebacks          106695                       # number of writebacks
+system.iocache.writebacks::total               106695                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8854                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8891                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8884                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8921                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8854                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8894                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8884                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8924                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8854                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8894                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8884                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8924                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1216268057                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1219613057                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1199183037                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1202528037                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7304905076                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7304905076                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7290172349                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7290172349                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1216268057                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1219832057                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1199183037                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1202747037                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1216268057                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1219832057                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1199183037                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1202747037                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2500,614 +2521,613 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134982.331945                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 134797.448380                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68280.351043                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68280.351043                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68306.089770                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68306.089770                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 137369.331037                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 137152.243872                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 134982.331945                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 134776.673801                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 137152.243872                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 134982.331945                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 134776.673801                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1146599                       # number of replacements
-system.l2c.tags.tagsinuse                63894.227459                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5787888                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1208030                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.791179                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1417273                       # number of replacements
+system.l2c.tags.tagsinuse                63778.929439                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6059487                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1477461                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.101284                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   20522.379023                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   161.905583                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   188.170352                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7049.393840                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11329.558347                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10071.994886                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    91.721739                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   112.803397                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4897.031985                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4344.569454                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  5124.698853                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.313147                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002470                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002871                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.107565                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.172875                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.153686                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001400                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001721                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.074723                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.066293                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.078197                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.974949                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10689                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          178                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50564                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          577                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         2554                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         7550                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          172                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1822                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        12846                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        35586                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.163101                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.002716                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.771545                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 67839853                       # Number of tag accesses
-system.l2c.tags.data_accesses                67839853                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2183647                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2183647                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           31153                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           25605                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               56758                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6308                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5360                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             11668                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           179937                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           157833                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               337770                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6619                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4994                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       688403                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       550904                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       317834                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5630                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3645                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       689738                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       516463                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       301818                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3086048                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6619                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4994                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              688403                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              730841                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       317834                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5630                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3645                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              689738                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              674296                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       301818                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3423818                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6619                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4994                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             688403                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             730841                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       317834                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5630                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3645                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             689738                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             674296                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       301818                       # number of overall hits
-system.l2c.overall_hits::total                3423818                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         42274                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         44615                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             86889                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         8694                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         8260                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           16954                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         478873                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         118092                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             596965                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1177                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1112                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        65012                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       121116                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       167688                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker          801                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker          747                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        45048                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        75565                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       121227                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         599493                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1177                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1112                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             65012                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            599989                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       167688                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker          801                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker          747                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             45048                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            193657                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       121227                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1196458                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1177                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1112                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            65012                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           599989                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       167688                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker          801                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker          747                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            45048                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           193657                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       121227                       # number of overall misses
-system.l2c.overall_misses::total              1196458                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    285461500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    257633000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    543094500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     50714500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     48938500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total     99653000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  44986860000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   9946118500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  54932978500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    102808500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker     98262500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5348800500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  10715307000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker     71359500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker     66724500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3695471500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   6552252500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  59947082310                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    102808500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker     98262500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   5348800500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  55702167000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker     71359500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker     66724500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3695471500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  16498371000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    114880060810                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    102808500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker     98262500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   5348800500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  55702167000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19492330795                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker     71359500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker     66724500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3695471500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  16498371000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  13803765015                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   114880060810                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2183647                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2183647                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        73427                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        70220                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          143647                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        15002                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        13620                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         28622                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       658810                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       275925                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           934735                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7796                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6106                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       753415                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       672020                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       485522                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6431                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         4392                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       734786                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       592028                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       423045                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3685541                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         7796                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6106                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          753415                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1330830                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       485522                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         6431                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         4392                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          734786                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          867953                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       423045                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4620276                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         7796                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6106                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         753415                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1330830                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       485522                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         6431                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         4392                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         734786                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         867953                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       423045                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4620276                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.575728                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.635360                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.604879                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.579523                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.606461                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.592342                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.726876                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.427986                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.638646                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.086290                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.180227                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.061308                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.127638                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.162661                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.086290                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.450838                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.061308                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.223119                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.258958                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.150975                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.182116                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.086290                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.450838                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.124553                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.170082                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.061308                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.223119                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.258958                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6752.649383                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5774.582540                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6250.440217                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5833.275822                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5924.757869                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5877.845936                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93943.195795                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84223.474071                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 92020.434196                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82274.049406                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88471.440602                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82034.085864                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 86710.150202                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 99996.300724                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82274.049406                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 92838.647042                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82034.085864                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 85193.775593                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 96016.793577                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87347.918437                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88365.557554                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82274.049406                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 92838.647042                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116241.655903                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89088.014981                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89323.293173                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82034.085864                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 85193.775593                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113867.084189                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 96016.793577                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               272                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   17721.105226                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   135.826880                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   142.018903                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5534.663770                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     7879.546362                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  8528.634482                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   234.293349                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   288.797420                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3403.637563                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8415.757562                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11494.647922                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.270403                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002073                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002167                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.084452                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.120232                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.130137                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003575                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004407                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.051935                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.128414                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.175394                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.973189                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9520                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          195                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50473                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2           59                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          311                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9149                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          195                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1751                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5310                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        43220                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.145264                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.002975                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.770157                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 72899096                       # Number of tag accesses
+system.l2c.tags.data_accesses                72899096                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2396145                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2396145                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           29304                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           31986                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               61290                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          6099                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          5707                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             11806                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           163881                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           167785                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               331666                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5962                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3875                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       733621                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       590091                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       312280                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6619                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4964                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       660183                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       546610                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       303770                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3167975                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5962                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3875                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              733621                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              753972                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       312280                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          6619                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4964                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              660183                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              714395                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       303770                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3499641                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         5962                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3875                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             733621                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             753972                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       312280                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         6619                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4964                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             660183                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             714395                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       303770                       # number of overall hits
+system.l2c.overall_hits::total                3499641                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         45221                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         40936                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             86157                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         9627                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data         8295                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           17922                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         527041                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         116613                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             643654                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1386                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1120                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        75246                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       138345                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       230447                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2412                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2147                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        45440                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       109170                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       198349                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         804062                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1386                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1120                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             75246                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            665386                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       230447                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2412                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2147                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             45440                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            225783                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       198349                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1447716                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1386                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1120                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            75246                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           665386                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       230447                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2412                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2147                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            45440                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           225783                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       198349                       # number of overall misses
+system.l2c.overall_misses::total              1447716                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    294012000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    222456500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    516468500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     58985000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data     48576500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    107561500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  49590710499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   9911915500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  59502625999                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    125671500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    101124000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6225311500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  12482167500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  28558623509                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    215227500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    192832000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3809523500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   9886876499                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  23694466040                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  85291823548                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    125671500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    101124000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   6225311500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  62072877999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  28558623509                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    215227500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    192832000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   3809523500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  19798791999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  23694466040                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    144794449547                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    125671500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    101124000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   6225311500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  62072877999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  28558623509                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    215227500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    192832000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3809523500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  19798791999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  23694466040                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   144794449547                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2396145                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2396145                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        74525                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        72922                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          147447                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        15726                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        14002                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         29728                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       690922                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       284398                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           975320                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7348                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4995                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       808867                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       728436                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       542727                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9031                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7111                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       705623                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       655780                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       502119                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3972037                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         7348                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         4995                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          808867                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1419358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       542727                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9031                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7111                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          705623                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          940178                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       502119                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4947357                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         7348                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         4995                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         808867                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1419358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       542727                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9031                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7111                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         705623                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         940178                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       502119                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4947357                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.606790                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.561367                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.584325                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.612171                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.592415                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.602866                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.762808                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.410035                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.659941                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.188623                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.224224                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.093026                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.189921                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.424609                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.267080                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.301927                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.064397                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.166474                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.395024                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.202431                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.188623                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.224224                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.093026                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.468794                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.424609                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.267080                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.301927                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.064397                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.240149                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.395024                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.292624                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.188623                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.224224                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.093026                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.468794                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.424609                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.267080                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.301927                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.064397                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.240149                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.395024                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.292624                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6501.669578                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5434.251026                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5994.504219                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6127.038537                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5856.118143                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  6001.646022                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 94092.699617                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84998.374967                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 92445.049668                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90672.077922                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90289.285714                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82732.789783                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90224.926813                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 123927.078717                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89231.965174                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89814.625058                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83836.344630                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90564.042310                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119458.459786                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 106076.177643                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90672.077922                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90289.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 82732.789783                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 93288.524254                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 123927.078717                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89231.965174                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89814.625058                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83836.344630                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 87689.471745                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119458.459786                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 100015.783169                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90672.077922                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90289.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 82732.789783                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 93288.524254                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 123927.078717                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89231.965174                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89814.625058                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83836.344630                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 87689.471745                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119458.459786                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 100015.783169                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              1849                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       25                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     90.666667                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     73.960000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              874415                       # number of writebacks
-system.l2c.writebacks::total                   874415                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          124                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            6                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          136                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           15                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          281                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            124                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            136                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                281                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           124                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           136                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               281                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        39767                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        39767                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        42274                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        44615                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        86889                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         8694                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8260                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        16954                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       478873                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       118092                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        596965                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1177                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1112                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        64888                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       121110                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker          801                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker          747                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44912                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        75550                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       599212                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1177                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1112                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        64888                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       599983                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker          801                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker          747                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        44912                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       193642                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1196177                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1177                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1112                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        64888                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       599983                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       167688                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker          801                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker          747                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        44912                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       193642                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       121227                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1196177                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1082222                       # number of writebacks
+system.l2c.writebacks::total                  1082222                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          107                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data            9                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          115                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           19                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          250                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            107                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            115                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             19                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                250                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           107                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           115                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            19                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               250                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        50233                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        50233                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        45221                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        40936                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        86157                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9627                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8295                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        17922                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       527041                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       116613                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        643654                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1386                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1120                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        75139                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       138336                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       230447                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2412                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2147                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        45325                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       109151                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       198349                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       803812                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1386                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1120                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        75139                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       665377                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       230447                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2412                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         2147                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        45325                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       225764                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       198349                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1447466                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1386                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1120                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        75139                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       665377                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       230447                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2412                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         2147                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        45325                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       225764                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       198349                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1447466                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52292                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        30167                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32791                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         8247                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        90799                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        29885                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         8420                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38305                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5212                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        90388                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        32852                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5003                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        37855                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52292                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60052                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        65643                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        16667                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       129104                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    877451504                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    925962001                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1803413505                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    180795000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    171889500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    352684500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  40198130000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8765198500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  48963328500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4691111500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9503861000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3237260500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   5795509500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  53935473310                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   4691111500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  49701991000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3237260500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  14560708000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 102898801810                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     91038500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     87142500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   4691111500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  49701991000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17815450795                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     63349500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     59254500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3237260500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  14560708000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  12591495015                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 102898801810                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10215                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       128243                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    938962001                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    849367002                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1788329003                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    200436500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    172427000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    372863500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  44320300499                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   8745785500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  53066085999                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    111811500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker     89924000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5466131500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  11098053500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  26254153509                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    191107500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    171362000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3348487500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   8794010999                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  21710976040                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  77236018048                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    111811500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     89924000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   5466131500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  55418353999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  26254153509                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    191107500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    171362000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3348487500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  17539796499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  21710976040                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 130302104047                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    111811500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     89924000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   5466131500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  55418353999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  26254153509                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    191107500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    171362000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3348487500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  17539796499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  21710976040                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 130302104047                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3261312500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4641716000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6042500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    881581500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8790652500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4402307500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1020289500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5422597000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5072417000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5669500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    438450000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8777849000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4909122500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    490071500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5399194000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3261312500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9044023500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6042500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1901871000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  14213249500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9981539500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5669500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    928521500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  14177043000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.575728                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.635360                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.604879                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.579523                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.606461                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.592342                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726876                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.427986                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.638646                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.180218                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.127612                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.162585                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.450834                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.223102                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.258897                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.150975                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.182116                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.086125                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.450834                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.345377                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.124553                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.170082                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.061123                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.223102                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.286558                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.258897                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.292378                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.499630                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.371854                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20795.376121                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20809.866828                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20802.436003                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83943.195795                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74223.474071                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 82020.434196                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78472.966724                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 76710.913302                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 90010.669529                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82838.998772                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75193.955857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 86023.056630                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 86023.056630                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.606790                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.561367                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.584325                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.612171                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.592415                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.602866                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.762808                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.410035                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.659941                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.188623                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.224224                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.092894                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.189908                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.424609                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.267080                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.301927                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.064234                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.166445                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.395024                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.202368                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.188623                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.224224                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.092894                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.468787                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.424609                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.267080                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.301927                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.064234                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.240129                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.395024                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.292574                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.188623                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.224224                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.092894                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.468787                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.424609                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.267080                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.301927                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.064234                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.240129                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.395024                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.292574                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20763.848676                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20748.656488                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20756.630372                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20820.245144                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.859554                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20804.792992                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84092.699617                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74998.374967                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 82445.049668                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72746.929025                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80225.346258                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73877.275234                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80567.388288                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96087.167208                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72746.929025                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83288.652898                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73877.275234                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77690.847518                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 90020.839209                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72746.929025                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83288.652898                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73877.275234                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77690.847518                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 90020.839209                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154689.304992                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84123.177283                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97112.990662                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149431.465360                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 97955.526684                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142628.292167                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152057.942203                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90897.846304                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 110548.279438                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               90799                       # Transaction distribution
-system.membus.trans_dist::ReadResp             698902                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38305                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38305                       # Transaction distribution
-system.membus.trans_dist::Writeback            981364                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           209019                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           434160                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         274076                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          111283                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            609626                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           589528                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        608103                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106984                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106984                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122944                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               90388                       # Transaction distribution
+system.membus.trans_dist::ReadResp             903121                       # Transaction distribution
+system.membus.trans_dist::WriteReq              37855                       # Transaction distribution
+system.membus.trans_dist::WriteResp             37855                       # Transaction distribution
+system.membus.trans_dist::Writeback           1188917                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           251117                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           423385                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         299485                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          111205                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            657294                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           636531                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        812733                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122698                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25274                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4403229                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4551499                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343039                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       343039                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4894538                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155959                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        23798                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5171308                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5317856                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342726                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342726                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5660582                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155805                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50548                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    135367808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    135575639                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7275904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7275904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               142851543                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           619953                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3354848                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        47596                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    164770304                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    164975029                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7270144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7270144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               172245173                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           635192                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3870084                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3354848    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3870084    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3354848                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109588500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3870084                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109645497                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21072500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            19606499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6982752656                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8359681063                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6858580357                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8175730132                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          229669194                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229316266                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3151,56 +3171,56 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq              90801                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4609563                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38305                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38305                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3165042                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1502795                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          483481                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        285744                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         769225                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          105                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          105                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1092976                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1092976                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4526002                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106984                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8264892                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6572319                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              14837211                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    254099969                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    185036822                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              439136791                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2966852                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         12598332                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.109406                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.312147                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq              90390                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4911274                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             37855                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            37855                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3585089                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1614217                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          477552                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        311291                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         788843                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          110                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          110                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1123188                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1123188                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4828127                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8913245                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6867211                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15780456                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    273644474                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    200023995                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              473668469                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3257042                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         13541412                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.121741                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.326987                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               11220005     89.06%     89.06% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1378327     10.94%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               11892865     87.83%     87.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1648547     12.17%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           12598332                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8167142441                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           13541412                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8755054077                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2478499                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2518500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4888169243                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5258284103                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4052371405                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4190040133                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
index ecd472250..8ee0c60d1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -179,7 +179,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -638,7 +638,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -748,7 +748,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -836,7 +836,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1251,9 +1251,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
index 067811cf5..8160d6530 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:47:25
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 14 2015 23:30:17
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51694136923000 because m5_exit instruction encountered
+Exiting @ tick 51694125219000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 8fffe3d01..f3053af8f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.694137                       # Number of seconds simulated
-sim_ticks                                51694136923000                       # Number of ticks simulated
-final_tick                               51694136923000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.694125                       # Number of seconds simulated
+sim_ticks                                51694125219000                       # Number of ticks simulated
+final_tick                               51694125219000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173196                       # Simulator instruction rate (inst/s)
-host_op_rate                                   203514                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9441127725                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 675004                       # Number of bytes of host memory used
-host_seconds                                  5475.42                       # Real time elapsed on the host
-sim_insts                                   948323287                       # Number of instructions simulated
-sim_ops                                    1114322939                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 131034                       # Simulator instruction rate (inst/s)
+host_op_rate                                   153967                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7136466436                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 718208                       # Number of bytes of host memory used
+host_seconds                                  7243.66                       # Real time elapsed on the host
+sim_insts                                   949163000                       # Number of instructions simulated
+sim_ops                                    1115282140                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       407232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       344384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10254400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         100902664                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        404352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            112313032                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10254400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10254400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     94405184                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       407680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       346624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10124864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         101217736                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        409088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            112505992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10124864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10124864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     94737216                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          94425764                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         6363                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5381                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             160225                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1576617                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6318                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1754904                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1475081                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          94757796                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6370                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5416                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             158201                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1581540                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6392                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1757919                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1480269                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1477654                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           7878                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6662                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               198367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1951917                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7822                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2172645                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          198367                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             198367                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1826226                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1482842                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           7886                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               195861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1958012                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2176379                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          195861                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             195861                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1832650                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1826624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1826226                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          7878                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              198367                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1952315                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7822                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3999270                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1754904                       # Number of read requests accepted
-system.physmem.writeReqs                      1477654                       # Number of write requests accepted
-system.physmem.readBursts                     1754904                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1477654                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                112259136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     54720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  94423744                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 112313032                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               94425764                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      855                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2252                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         146151                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              109407                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              112864                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              109220                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              104188                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              106449                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              113846                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              104146                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              106564                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               99467                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              160932                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             104576                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             109948                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             102336                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             105581                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              99543                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             104982                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               93507                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               95050                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               93111                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               91031                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               92702                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               96804                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               89915                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               93502                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               87351                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               94209                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              90719                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              94851                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              89273                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              92330                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              88747                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              92269                       # Per bank write bursts
+system.physmem.bw_write::total                1833048                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1832650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          7886                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              195861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1958410                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4009426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1757919                       # Number of read requests accepted
+system.physmem.writeReqs                      1482842                       # Number of write requests accepted
+system.physmem.readBursts                     1757919                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1482842                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                112457536                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     49280                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  94756288                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 112505992                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               94757796                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      770                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2248                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         146200                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              105973                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              111407                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              105002                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              101812                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              108332                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117578                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              104534                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              108687                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              103848                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              161007                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             107405                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             110838                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             104563                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             103815                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             100822                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             101526                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               90430                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               94995                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               91678                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               90022                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               94229                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               99888                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               89385                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               93994                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               90076                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               95745                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              91874                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              95898                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              91438                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              92023                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              89075                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              89817                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51694135218000                       # Total gap between requests
+system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51694123514000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1754889                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1757904                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1475081                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1420187                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    327570                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       933                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       327                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       534                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       776                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       878                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      379                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       46                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1480269                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1422025                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    328688                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1048                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       351                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       481                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       469                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       492                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       522                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       773                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       906                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      358                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      190                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      168                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      117                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       93                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       57                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -159,164 +159,165 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    15753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    18367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    69542                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    87805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    88303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    88136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    87821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    90771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    91285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    93842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    92895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    93403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    89996                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    90062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   102154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    88485                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    90293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    86850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       688077                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      300.376987                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.587339                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.638975                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         270609     39.33%     39.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       164654     23.93%     63.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        63521      9.23%     72.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        36566      5.31%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        27027      3.93%     81.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        18739      2.72%     84.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        14736      2.14%     86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        13602      1.98%     88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        78623     11.43%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         688077                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         86230                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.341007                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      270.950677                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          86227    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    15568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    18151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    71947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    88213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    88480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    88386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    88377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    91264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    92065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    94405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    93246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    93724                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    90170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    90391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   100271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    88772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    90332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    87233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      613                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      492                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       83                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       690739                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      299.988042                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.369601                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     327.443819                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         271817     39.35%     39.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       165800     24.00%     63.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        63380      9.18%     72.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        36796      5.33%     77.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        26984      3.91%     81.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        18833      2.73%     84.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        14857      2.15%     86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        13605      1.97%     88.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        78667     11.39%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         690739                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         86593                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.291686                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      270.345126                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          86590    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           86230                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         86230                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.109718                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.738195                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        5.845815                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           83739     97.11%     97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             148      0.17%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             433      0.50%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             182      0.21%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             327      0.38%     98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             491      0.57%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             146      0.17%     99.11% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           86593                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         86593                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.097999                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.728630                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        5.809360                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           84121     97.15%     97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             149      0.17%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             413      0.48%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             198      0.23%     98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             310      0.36%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             507      0.59%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             123      0.14%     99.11% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::44-47              35      0.04%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              38      0.04%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              19      0.02%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              25      0.03%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              26      0.03%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             445      0.52%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              41      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              34      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              31      0.04%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            32      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             8      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           86230                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    26659687931                       # Total ticks spent queuing
-system.physmem.totMemAccLat               59548106681                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8770245000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15198.94                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::48-51              41      0.05%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              24      0.03%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              40      0.05%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              29      0.03%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             413      0.48%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              31      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              42      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              40      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               8      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               4      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            31      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             4      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           86593                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    26847024830                       # Total ticks spent queuing
+system.physmem.totMemAccLat               59793568580                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8785745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15278.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33948.94                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.17                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34028.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.18                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.83                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.17                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.18                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.61                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1434287                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1107055                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.77                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15991711.59                       # Average gap between requests
-system.physmem.pageHitRate                      78.69                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2644873560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1443135375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6760088400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4831630560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3376409683920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1310236671105                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29867151449250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34569477532170                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.731116                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49685803332014                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1726180820000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.96                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1436721                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1110255                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.76                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.99                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15951229.82                       # Average gap between requests
+system.physmem.pageHitRate                      78.67                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2651919480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1446979875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6733888200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4825144080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3376408666800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1308234674070                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29868898243500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34569199516005                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.725939                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49688706621634                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1726180300000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    282152299236                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    279237825366                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2556988560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1395182250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6921447000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4728773520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3376409683920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1305311169150                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29871472073250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34568795317650                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.717918                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49692977337193                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1726180820000                       # Time in different power states
+system.physmem_1.actEnergy                 2570067360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1402318500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6971827200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4768930080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3376408666800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1306063695690                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29870802610500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34568988116130                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.721850                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49691848230640                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1726180300000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    274978307807                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    276092348110                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -340,15 +341,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               260235992                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         182594285                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12181539                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            193306639                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               136184729                       # Number of BTB hits
+system.cpu.branchPred.lookups               260286663                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         182589592                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12077009                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            191806323                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               136128585                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.450104                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31573215                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2152291                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.971896                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31602025                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2167880                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -379,61 +380,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    586554                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                586554                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22200                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191198                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       586554                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          586554    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       586554                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       213398                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 26171.173113                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 22678.472578                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15672.620914                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       210833     98.80%     98.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         2191      1.03%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          145      0.07%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          108      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           74      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           36      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       213398                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    582770                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                582770                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22376                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       191329                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       582770                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          582770    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       582770                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       213705                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 26351.678716                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       211142     98.80%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         2168      1.01%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          149      0.07%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          124      0.06%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           84      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       213705                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples    -58656296                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0       -58656296    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total    -58656296                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        191199     89.60%     89.60% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         22200     10.40%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       213399                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       586554                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K        191330     89.53%     89.53% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         22376     10.47%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       213706                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       582770                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       586554                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213399                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       582770                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213706                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213399                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       799953                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213706                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       796476                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183104972                       # DTB read hits
-system.cpu.dtb.read_misses                     484611                       # DTB read misses
-system.cpu.dtb.write_hits                   162443368                       # DTB write hits
-system.cpu.dtb.write_misses                    101943                       # DTB write misses
+system.cpu.dtb.read_hits                    183257458                       # DTB read hits
+system.cpu.dtb.read_misses                     481031                       # DTB read misses
+system.cpu.dtb.write_hits                   162586595                       # DTB write hits
+system.cpu.dtb.write_misses                    101739                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    80156                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       829                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  15457                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    80339                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1450                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  15121                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23578                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                183589583                       # DTB read accesses
-system.cpu.dtb.write_accesses               162545311                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23575                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                183738489                       # DTB read accesses
+system.cpu.dtb.write_accesses               162688334                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         345548340                       # DTB hits
-system.cpu.dtb.misses                          586554                       # DTB misses
-system.cpu.dtb.accesses                     346134894                       # DTB accesses
+system.cpu.dtb.hits                         345844053                       # DTB hits
+system.cpu.dtb.misses                          582770                       # DTB misses
+system.cpu.dtb.accesses                     346426823                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -463,46 +464,42 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    136663                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                136663                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1080                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       119012                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       136663                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          136663    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       136663                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       120092                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28563.884355                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 25001.850654                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 17459.523046                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-32767        59524     49.57%     49.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-65535        57595     47.96%     97.52% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-98303         1126      0.94%     98.46% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::98304-131071         1581      1.32%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-163839           30      0.02%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::163840-196607          128      0.11%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-229375           37      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::229376-262143           22      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-294911           13      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::294912-327679           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-360447           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::360448-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       120092                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                    136614                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                136614                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1073                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       118911                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       136614                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          136614    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       136614                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       119984                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28837.324143                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 25253.165818                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 17670.490053                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       116985     97.50%     97.50% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         2707      2.26%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          180      0.15%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           56      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           24      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       119984                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples    -59528796                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0       -59528796    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total    -59528796                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        119012     99.10%     99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1080      0.90%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       120092                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K        118911     99.11%     99.11% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1073      0.89%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       119984                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136663                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       136663                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136614                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       136614                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       120092                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       120092                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       256755                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    453103030                       # ITB inst hits
-system.cpu.itb.inst_misses                     136663                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119984                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       119984                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       256598                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    452975639                       # ITB inst hits
+system.cpu.itb.inst_misses                     136614                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -511,140 +508,139 @@ system.cpu.itb.flush_tlb                           11                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               47231                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    57609                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    57698                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    364302                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    370160                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                453239693                       # ITB inst accesses
-system.cpu.itb.hits                         453103030                       # DTB hits
-system.cpu.itb.misses                          136663                       # DTB misses
-system.cpu.itb.accesses                     453239693                       # DTB accesses
-system.cpu.numCycles                       2508251480                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                453112253                       # ITB inst accesses
+system.cpu.itb.hits                         452975639                       # DTB hits
+system.cpu.itb.misses                          136614                       # DTB misses
+system.cpu.itb.accesses                     453112253                       # DTB accesses
+system.cpu.numCycles                       2511767999                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   948323287                       # Number of instructions committed
-system.cpu.committedOps                    1114322939                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      97332960                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7744                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100881187078                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.644933                       # CPI: cycles per instruction
-system.cpu.ipc                               0.378081                       # IPC: instructions per cycle
+system.cpu.committedInsts                   949163000                       # Number of instructions committed
+system.cpu.committedOps                    1115282140                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      97160712                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7743                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100877722288                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.646298                       # CPI: cycles per instruction
+system.cpu.ipc                               0.377886                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16604                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1790178903                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       718072577                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements          11134622                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.957818                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           329114421                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11135134                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.556395                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                    19481                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1790897935                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       720870064                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          11142195                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.957822                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           329410408                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11142707                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.562871                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4277412500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.957818                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.957822                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999918                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999918                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1383337751                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1383337751                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    168246441                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       168246441                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    151606594                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      151606594                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       524249                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        524249                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       336460                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       336460                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4018923                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4018923                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4332342                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4332342                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     319853035                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        319853035                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    320377284                       # number of overall hits
-system.cpu.dcache.overall_hits::total       320377284                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6626426                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6626426                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4317891                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4317891                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1480828                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1480828                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1245336                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1245336                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       315150                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       315150                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1384553632                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1384553632                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    168394927                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       168394927                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    151754199                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      151754199                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       523439                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        523439                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       336679                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       336679                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4017108                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4017108                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4334477                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4334477                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     320149126                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        320149126                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    320672565                       # number of overall hits
+system.cpu.dcache.overall_hits::total       320672565                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6628843                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6628843                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4317749                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4317749                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1481094                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1481094                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1245106                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1245106                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       319103                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       319103                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     10944317                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10944317                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12425145                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12425145                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 107226750500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 107226750500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 152543350000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 152543350000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  58512566000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  58512566000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4781324500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4781324500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     10946592                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10946592                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     12427686                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12427686                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 107264639000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 153170066000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  58641269000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  58641269000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4837420500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4837420500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       115500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       115500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 259770100500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 259770100500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 259770100500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 259770100500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    174872867                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    174872867                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    155924485                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    155924485                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2005077                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2005077                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1581796                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1581796                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4334073                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4334073                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4332344                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4332344                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    330797352                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    330797352                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    332802429                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    332802429                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037893                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037893                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027692                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027692                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738539                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.738539                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787292                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.787292                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.072715                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.072715                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 260434705000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 260434705000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 260434705000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 260434705000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    175023770                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    175023770                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    156071948                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    156071948                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2004533                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2004533                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1581785                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1581785                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4336211                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4336211                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4334479                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4334479                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    331095718                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    331095718                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    333100251                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    333100251                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037874                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.037874                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027665                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027665                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738872                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.738872                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787152                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.787152                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073590                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073590                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.033085                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.033085                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037335                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037335                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.686855                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.686855                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35328.207683                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35328.207683                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 46985.364592                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 46985.364592                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15171.583373                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15171.583373                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.033062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.033062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037309                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037309                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.502413                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.502413                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35474.518320                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35474.518320                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 47097.410983                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 47097.410983                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15159.432848                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15159.432848                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        57750                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        57750                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23735.615525                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23735.615525                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20906.806359                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20906.806359                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23791.395989                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23791.395989                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20956.009429                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20956.009429                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -653,155 +649,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8552025                       # number of writebacks
-system.cpu.dcache.writebacks::total           8552025                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       818755                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       818755                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1904630                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1904630                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          150                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total          150                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70014                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        70014                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2723385                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2723385                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2723385                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2723385                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5807671                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5807671                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2413261                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2413261                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473332                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1473332                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1245186                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1245186                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       245136                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       245136                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      8554549                       # number of writebacks
+system.cpu.dcache.writebacks::total           8554549                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       817761                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       817761                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1903794                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1903794                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          151                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total          151                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70489                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70489                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2721555                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2721555                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2721555                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2721555                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5811082                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5811082                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2413955                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2413955                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1473693                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1473693                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1244955                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1244955                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       248614                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       248614                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8220932                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8220932                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9694264                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9694264                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8225037                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8225037                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9698730                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9698730                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33699                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67406                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  87900213000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  87900213000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80008628500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  80008628500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23654166000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23654166000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  57263274500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  57263274500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3335164500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3335164500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  87944699500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  87944699500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80337194000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  80337194000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23656791000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23656791000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  57392051500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  57392051500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3386354500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3386354500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       113500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       113500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167908841500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 167908841500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191563007500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191563007500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5830486500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5830486500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5692032500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5692032500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11522519000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11522519000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033211                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033211                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015477                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015477                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734801                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734801                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787198                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787198                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056560                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056560                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168281893500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 168281893500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191938684500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191938684500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5830552000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5830552000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5692063000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5692063000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11522615000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11522615000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033202                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033202                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.735180                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.735180                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787057                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787057                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057334                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057334                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024852                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024852                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029129                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029129                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15135.191542                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15135.191542                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33153.740312                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33153.740312                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16054.878330                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16054.878330                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 45987.727536                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 45987.727536                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13605.363961                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13605.363961                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024842                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024842                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029117                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029117                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15133.962918                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15133.962918                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33280.319641                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33280.319641                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16052.726721                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.726721                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 46099.699588                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 46099.699588                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13620.932450                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13620.932450                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        56750                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        56750                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20424.550586                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20424.550586                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19760.448808                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19760.448808                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173016.602867                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173016.602867                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168867.965111                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168867.965111                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170942.037801                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170942.037801                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          24460747                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.918526                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           428265010                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24461259                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.507889                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       26893649500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.918526                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          24575522                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.918698                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           428017274                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24576034                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.416043                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26893274500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.918698                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999841                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999841                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          118                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         477187547                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        477187547                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    428265010                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       428265010                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     428265010                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        428265010                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    428265010                       # number of overall hits
-system.cpu.icache.overall_hits::total       428265010                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24461269                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24461269                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24461269                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24461269                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24461269                       # number of overall misses
-system.cpu.icache.overall_misses::total      24461269                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 325762917500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 325762917500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 325762917500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 325762917500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 325762917500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 325762917500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    452726279                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    452726279                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    452726279                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    452726279                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    452726279                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    452726279                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054031                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.054031                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.054031                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.054031                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.054031                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.054031                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13317.498675                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13317.498675                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13317.498675                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13317.498675                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13317.498675                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13317.498675                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         477169361                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        477169361                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    428017274                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       428017274                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     428017274                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        428017274                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    428017274                       # number of overall hits
+system.cpu.icache.overall_hits::total       428017274                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     24576044                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      24576044                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     24576044                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       24576044                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     24576044                       # number of overall misses
+system.cpu.icache.overall_misses::total      24576044                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 327136040500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 327136040500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 327136040500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 327136040500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 327136040500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 327136040500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    452593318                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    452593318                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    452593318                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    452593318                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    452593318                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    452593318                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054301                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.054301                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.054301                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.054301                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.054301                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.054301                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13311.175733                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13311.175733                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13311.175733                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13311.175733                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13311.175733                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13311.175733                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -810,225 +806,225 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24461269                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24461269                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24461269                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24461269                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24461269                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24461269                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24576044                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24576044                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24576044                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24576044                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24576044                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24576044                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        52295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52295                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        52295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 301301649500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 301301649500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 301301649500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 301301649500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 301301649500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 301301649500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302559997500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 302559997500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302559997500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 302559997500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302559997500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 302559997500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4042938500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4042938500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4042938500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   4042938500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054031                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054031                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054031                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.054031                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054031                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.054031                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12317.498716                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12317.498716                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12317.498716                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12317.498716                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054301                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054301                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054301                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.054301                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054301                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.054301                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12311.175773                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12311.175773                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12311.175773                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12311.175773                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12311.175773                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12311.175773                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1604829                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65266.156442                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           67107084                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1667914                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            40.234139                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      24502559000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 35881.888844                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   344.047128                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   429.269400                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8228.433015                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 20382.518055                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.547514                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005250                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006550                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125556                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.311013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995883                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          276                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62809                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1607082                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65318.726670                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           67354503                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1670310                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            40.324552                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      24502286000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36002.307210                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   335.180696                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   433.791675                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8203.980766                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 20343.466323                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.549352                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005114                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006619                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.125183                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.310417                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996685                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          219                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63009                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          275                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          504                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2442                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5503                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54305                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.958389                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        585371330                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       585371330                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       972902                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       283103                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1256005                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      8552025                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8552025                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        10723                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        10723                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1658365                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1658365                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24353307                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     24353307                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7197008                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      7197008                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       701735                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       701735                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       972902                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       283103                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     24353307                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      8855373                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        34464685                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       972902                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       283103                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     24353307                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      8855373                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       34464685                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6363                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5381                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        11744                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        38680                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        38680                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          218                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          524                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2413                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5473                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54554                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003342                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961441                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        587356710                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       587356710                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       972528                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       286301                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1258829                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      8554549                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      8554549                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        10855                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        10855                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1654669                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1654669                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24470106                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     24470106                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7204785                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7204785                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       700263                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       700263                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       972528                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       286301                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     24470106                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      8859454                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        34588389                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker       972528                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       286301                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     24470106                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      8859454                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       34588389                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6370                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5416                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        11786                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data        38716                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        38716                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       705767                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       705767                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107959                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total       107959                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       328857                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       328857                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       543451                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       543451                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         6363                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         5381                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst       107959                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1034624                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1154327                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         6363                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         5381                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       107959                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1034624                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1154327                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    554201500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    467153500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1021355000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    576538000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total    576538000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data       709953                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       709953                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       105935                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total       105935                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       328366                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       328366                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       544692                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       544692                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker         6370                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         5416                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst       105935                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1038319                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1156040                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker         6370                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         5416                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst       105935                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1038319                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1156040                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    553122500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    470413000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1023535500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    578007500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total    578007500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       110500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       110500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  57650400000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  57650400000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8792604500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   8792604500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  27746254000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  27746254000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  47759810000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total  47759810000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    554201500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    467153500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   8792604500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  85396654000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  95210613500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    554201500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    467153500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   8792604500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  85396654000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  95210613500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       979265                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       288484                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1267749                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      8552025                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8552025                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        49403                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        49403                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  58013412000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  58013412000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8652629500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   8652629500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  27752985500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  27752985500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  47906162000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total  47906162000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    553122500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    470413000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   8652629500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  85766397500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  95442562500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    553122500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    470413000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   8652629500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  85766397500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  95442562500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       978898                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       291717                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1270615                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      8554549                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      8554549                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        49571                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        49571                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2364132                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2364132                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24461266                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     24461266                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7525865                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7525865                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1245186                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1245186                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       979265                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       288484                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     24461266                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9889997                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     35619012                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       979265                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       288484                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     24461266                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9889997                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     35619012                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018653                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.009264                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782948                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782948                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2364622                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2364622                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24576041                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     24576041                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7533151                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7533151                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1244955                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1244955                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       978898                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       291717                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     24576041                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9897773                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     35744429                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       978898                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       291717                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     24576041                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9897773                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     35744429                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006507                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.018566                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.009276                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.781021                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.781021                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.298531                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.298531                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004413                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004413                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043697                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043697                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.436442                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.436442                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018653                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004413                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.104613                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.032408                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006498                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018653                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004413                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.104613                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.032408                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86815.368891                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 86968.239101                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14905.325750                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14905.325750                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.300240                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.300240                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004310                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004310                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043589                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043589                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.437519                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.437519                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006507                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018566                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004310                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.104904                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.032342                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006507                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018566                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004310                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.104904                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.032342                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86832.417582                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86856.166913                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 86843.331071                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14929.421944                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14929.421944                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        55250                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        55250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81684.748649                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81684.748649                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81443.923156                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81443.923156                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84371.790778                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84371.790778                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87882.458584                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87882.458584                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86815.368891                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81443.923156                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82538.829565                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82481.492246                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87097.516895                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86815.368891                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81443.923156                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82538.829565                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82481.492246                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81714.440252                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81714.440252                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81678.666163                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81678.666163                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84518.450449                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84518.450449                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87950.919052                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87950.919052                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86832.417582                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86856.166913                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81678.666163                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82601.202039                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82559.913584                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86832.417582                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86856.166913                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81678.666163                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82601.202039                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82559.913584                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1037,8 +1033,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1368450                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1368450                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1373638                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1373638                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1049,33 +1045,33 @@ system.cpu.l2cache.demand_mshr_hits::total           24                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6363                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5381                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        11744                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1115                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1115                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38680                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        38680                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6370                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5416                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        11786                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1102                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1102                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        38716                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        38716                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       705767                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       705767                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107956                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107956                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       328836                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       328836                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       543451                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       543451                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6363                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5381                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       107956                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1034603                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1154303                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6363                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5381                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       107956                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1034603                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1154303                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       709953                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       709953                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       105932                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total       105932                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       328345                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       328345                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       544692                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       544692                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6370                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       105932                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1038298                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1156016                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6370                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5416                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       105932                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1038298                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1156016                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52295                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33699                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85994                       # number of ReadReq MSHR uncacheable
@@ -1084,151 +1080,151 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33707
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52295                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67406                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119701                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    413343500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    903915000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    803162500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    803162500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    489422500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    416253000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    905675500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    803927500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    803927500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        90500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        90500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  50592730000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  50592730000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7712869000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7712869000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  24456668500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  24456668500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  42325300000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  42325300000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    413343500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7712869000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  75049398500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  83666182500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    490571500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    413343500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7712869000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  75049398500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  83666182500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  50913882000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  50913882000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7593134000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7593134000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  24468048000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  24468048000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  42459242000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  42459242000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    489422500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    416253000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7593134000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  75381930000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  83880739500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    489422500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    416253000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7593134000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  75381930000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  83880739500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409182000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8641547500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5303781000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5303781000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409250000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8641615500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5303815500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5303815500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3232365500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10712963000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13945328500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009264                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10713065500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13945431000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006507                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018566                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009276                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782948                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782948                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.781021                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.781021                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.298531                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.298531                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004413                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043694                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043694                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.436442                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.436442                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104611                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.032407                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006498                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018653                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004413                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104611                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.032407                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76968.239101                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.283868                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.283868                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.300240                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.300240                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004310                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004310                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043587                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043587                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.437519                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.437519                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006507                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018566                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004310                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104902                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.032341                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006507                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018566                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004310                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104902                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.032341                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76856.166913                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76843.331071                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.735510                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.735510                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45250                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71684.748649                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71684.748649                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71444.560747                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74373.452116                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74373.452116                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77882.458584                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77882.458584                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72539.320396                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72481.993463                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77097.516895                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76815.368891                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71444.560747                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72539.320396                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72481.993463                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71714.440252                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71714.440252                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71679.322584                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71679.322584                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74519.325709                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74519.325709                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77950.919052                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77950.919052                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76856.166913                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71679.322584                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72601.440049                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72560.189046                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76856.166913                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71679.322584                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72601.440049                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72560.189046                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160514.614677                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.121404                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157349.541638                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157349.541638                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160516.632541                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.912157                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157350.565165                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157350.565165                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158931.890336                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116501.353372                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158933.410972                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116502.209672                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1796538                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33784448                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1789463                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      33899423                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback     10027137                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     27284097                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        49406                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback     10034845                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     27401014                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        49574                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        49408                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2364132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2364132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     24461269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7534742                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1351850                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1245186                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73484098                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33638682                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       696808                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2281485                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total         110101073                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1568867840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1180529566                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2307872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7834120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2759539398                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2279468                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     74907361                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.047344                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.212374                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        49576                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2364622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2364622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24576044                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7542009                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1351619                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1244955                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73828388                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33661752                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       699908                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2274176                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         110464224                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1576213440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1181188062                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2333736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7831184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2767566422                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2271727                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     75147333                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.047128                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.211913                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           71360927     95.27%     95.27% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            3546434      4.73%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           71605763     95.29%     95.29% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            3541570      4.71%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       74907361                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    45104615497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       75147333                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    45226020496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1167000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1150500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   36773946781                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   36946016966                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15533347490                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   15544978992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     408345956                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     408213455                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1302236467                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1295285984                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40306                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40306                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1247,11 +1243,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230970                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230970                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353754                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1268,11 +1264,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334312                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334312                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1301,71 +1297,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           568973549                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568890575                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147730000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115486                       # number of replacements
-system.iocache.tags.tagsinuse               10.447136                       # Cycle average of tags in use
+system.iocache.tags.replacements               115467                       # number of replacements
+system.iocache.tags.tagsinuse               10.447125                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115483                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13147036427000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.519010                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.928125                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13147039080000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.519011                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928115                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.219938                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433008                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.652946                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433007                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.652945                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039893                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039722                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039722                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8821                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8858                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8840                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8880                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8821                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8861                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8840                       # number of overall misses
-system.iocache.overall_misses::total             8880                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8821                       # number of overall misses
+system.iocache.overall_misses::total             8861                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1592056146                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1597125146                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1605437158                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1610506158                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12612249403                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12612249403                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12610481417                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12610481417                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1592056146                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1597476146                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1605437158                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1610857158                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1592056146                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1597476146                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1605437158                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1610857158                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8821                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8858                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8840                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8880                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8821                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8861                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8840                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8880                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8821                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8861                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1380,54 +1376,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 180096.849095                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 179917.218204                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 181813.745541                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118242.794223                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118242.794223                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118226.218940                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 180096.849095                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 179895.962387                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 182001.718399                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 181791.802054                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 180096.849095                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 179895.962387                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         29944                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 182001.718399                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 181791.802054                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31114                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3370                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3332                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.885460                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.337935                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8821                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8858                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8840                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8880                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8821                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8861                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8840                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8880                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8821                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8861                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1150056146                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1153275146                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1164387158                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1167606158                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7279049403                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7279049403                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7277281417                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7277281417                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1150056146                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1153476146                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1164387158                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1167807158                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1150056146                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1153476146                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1164387158                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1167807158                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1442,72 +1438,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130096.849095                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 129917.218204                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68242.794223                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68242.794223                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 130096.849095                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 129895.962387                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131791.802054                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 130096.849095                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 129895.962387                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131791.802054                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               85994                       # Transaction distribution
-system.membus.trans_dist::ReadResp             543407                       # Transaction distribution
+system.membus.trans_dist::ReadResp             540915                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
-system.membus.trans_dist::Writeback           1475081                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           242486                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            39492                       # Transaction distribution
+system.membus.trans_dist::Writeback           1480269                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           239619                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            39541                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           39494                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1248409                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1248409                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        457413                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           39543                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1253823                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1253823                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        454921                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6922                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5186779                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5316437                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341268                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341268                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5657705                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5195008                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5324666                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341395                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341395                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5666061                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13844                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    199510060                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    199680478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7228736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7228736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               206909214                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3224                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3692024                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    200030316                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    200200734                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7233472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               207434206                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3131                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3697223                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3692024    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3697223    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3692024                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           102515000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3697223                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           102366500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5516000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5756000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9935800091                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9961724084                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         9380119144                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         9396279986                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228946369                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228925719                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1551,13 +1547,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
index ef60c64b3..7fb6c1d15 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -352,7 +352,7 @@ type=ExeTracer
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -693,7 +693,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -803,7 +803,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -891,7 +891,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1306,9 +1306,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
index 18ae58d7b..95cf6c86b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
@@ -11,84 +11,89 @@ warn: 12461855003000: Instruction results do not match! (Values may not actually
 warn: 12461858210000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 13850221736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13887901759500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13889201357500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13891026528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13912972124000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13922135264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13972304377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14214756028000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14214756243500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14222804811500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14230560980500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14230561210500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14230561417000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14238296234000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14238296464000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14238296670500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14243468378000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14243468608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14249670454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14249670684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14259219992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14259220222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14259220428500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14270200247500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14270200481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14270200711500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14270200918000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14279912002500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14279912512000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14279912746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14279912976000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14279913182500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14295232623000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14295232862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14300292322000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14300292552000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14307240927500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14307241161500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14307241391500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14307241598000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14317300126000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14317300896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14317301130500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14317301360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14317301567000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14379824982500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14379825231000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14379825446500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14437325800500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14437326869000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14437327084500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14565495184000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565581739000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14565581956000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565582249000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14565582808000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565583286500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565583575500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565584084500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565585151500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14565585961500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566302033500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566302294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
-warn: 14566302499000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566373295000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14566373505000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566373776000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14566374346500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566374602000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14566374825500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566375114500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566375623500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566376687000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566377185000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14566377487000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14614511931000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
-warn: 14614512222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14614512481000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14614512725500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14614512987500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14614513217000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 13846883856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13889111424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13890567287500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13890857543500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14120809755000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14122306502500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14122718805500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14129885647500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14130112878000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14130333669000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14130937323000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14131157192000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14131378652000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14143275616000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14210692350500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14453290384000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14453290599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14461368009500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14469164155500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14469164395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14469164601500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14477036010500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14477036254000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14477036493500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14477036700000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14482248599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14482248839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14488506207500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14488506438000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14498157332500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14498158077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14498158308000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14498158514500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14509187190500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14509187421000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14509187627500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14518942903500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14518943414000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14518943648500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14518943879000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14518944085500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14534430251500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14534430481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14539499143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14539499377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14539499607500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14546501559500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14546502303000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14546502533000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14546502739500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14556606981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14556607490500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14556607724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14556607954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14556608161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14619728573500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14619728789000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14678031922000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14678032489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14678032742000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14678032990500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14678033206000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14803922617500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804021218000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804021536500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804745192000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804745453000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
+warn: 14804745657500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804816537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14804816747000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804817018000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14804817588500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804817844000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14804818067500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804818356500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804818865500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804819928000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804820419500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14804820721500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14853183049500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14853362963500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 14853363240000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14853363492000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14853363736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14853363998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14853364228000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
index 703b25032..ddf9e75e0 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 11:01:08
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:50:46
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51323721423000 because m5_exit instruction encountered
+Exiting @ tick 51562169701000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 597734940..e2a586128 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,141 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.323721                       # Number of seconds simulated
-sim_ticks                                51323721423000                       # Number of ticks simulated
-final_tick                               51323721423000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.562170                       # Number of seconds simulated
+sim_ticks                                51562169701000                       # Number of ticks simulated
+final_tick                               51562169701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  88242                       # Simulator instruction rate (inst/s)
-host_op_rate                                   103686                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5307363437                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 679356                       # Number of bytes of host memory used
-host_seconds                                  9670.29                       # Real time elapsed on the host
-sim_insts                                   853325819                       # Number of instructions simulated
-sim_ops                                    1002674190                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  60233                       # Simulator instruction rate (inst/s)
+host_op_rate                                    70799                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2812244888                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 727556                       # Number of bytes of host memory used
+host_seconds                                 18334.88                       # Real time elapsed on the host
+sim_insts                                  1104366834                       # Number of instructions simulated
+sim_ops                                    1298086167                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       203200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       189632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5727200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          73778504                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        419776                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             80318312                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5727200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5727200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68723904                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       657984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       557504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           6634080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         148649160                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        417792                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            156916520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      6634080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6634080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    139624832                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68744484                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3175                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         2963                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             105440                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1152802                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6559                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1270939                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1073811                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         139645412                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker        10281                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         8711                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             119610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2322656                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6528                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2467786                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         2181638                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1076384                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3959                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3695                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               111590                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1437513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8179                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1564935                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          111590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             111590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1339028                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1339429                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1339028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3695                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              111590                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1437914                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8179                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2904365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1270939                       # Number of read requests accepted
-system.physmem.writeReqs                      1076384                       # Number of write requests accepted
-system.physmem.readBursts                     1270939                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1076384                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 81299584                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40512                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  68742976                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  80318312                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               68744484                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      633                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         142017                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               76590                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               80112                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               82312                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               76894                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               75148                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               84486                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               75307                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               76047                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               76921                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              104197                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              75653                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              81028                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              74845                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              77383                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              76622                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              76761                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               64108                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67910                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               69982                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               67432                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               65959                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               70786                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64733                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               66187                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67287                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               71812                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65064                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              69201                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              65082                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              66370                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66024                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              66172                       # Per bank write bursts
+system.physmem.num_writes::total              2184211                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker          12761                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker          10812                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               128662                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2882911                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3043249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          128662                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             128662                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2707893                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2708292                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2707893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker         12761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker         10812                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              128662                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2883310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5751541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2467786                       # Number of read requests accepted
+system.physmem.writeReqs                      2184211                       # Number of write requests accepted
+system.physmem.readBursts                     2467786                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2184211                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                157889856                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     48448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 139644224                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 156916520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              139645412                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      757                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         155211                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              149005                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              156339                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              155955                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              150628                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              148084                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              159303                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              149188                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              152515                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              150862                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              179370                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             150320                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             155893                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             152080                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             155961                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             150556                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             150970                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              132106                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              138501                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              137398                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              135602                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              133392                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              140433                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              132940                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              137025                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              135656                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              141181                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             134433                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             138339                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             136301                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             138853                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             135122                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             134659                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51323720227500                       # Total gap between requests
+system.physmem.numWrRetry                          21                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51562168447500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1249654                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2446501                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1073811                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    646219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    339232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    151287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    128129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       489                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       502                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       533                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       812                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       936                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      392                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      192                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2181638                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1276105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    831313                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    193469                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    160610                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       761                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       490                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       829                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       946                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      413                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      181                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      164                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      120                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -159,164 +159,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    11927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    14439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    31518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    44897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    53343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    63481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    63532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    67021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    67803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    70464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    69167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    70329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    66867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    85010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    86471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    65847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    69713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    62929                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       481355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      311.708207                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.914901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.146013                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         186832     38.81%     38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       113175     23.51%     62.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        45398      9.43%     71.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23450      4.87%     76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18101      3.76%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11671      2.42%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10460      2.17%     84.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8315      1.73%     86.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        63953     13.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         481355                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61522                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.647411                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      265.936082                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          61519    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    20208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    23029                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    68337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   107857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   119474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   131451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   131860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   135328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   136231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   138984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   139007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   140497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   136343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   166652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   162914                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   137438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   145049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   131294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      409                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       55                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       938073                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      317.175418                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     184.850858                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.830774                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         348981     37.20%     37.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       217922     23.23%     60.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        89990      9.59%     70.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        51985      5.54%     75.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        41514      4.43%     79.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        28050      2.99%     82.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        24686      2.63%     85.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        20558      2.19%     87.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       114387     12.19%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         938073                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples        129462                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        19.055908                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      183.344638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047         129459    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61522                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61522                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.458942                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.948779                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.823778                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           58490     95.07%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             664      1.08%     96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             448      0.73%     96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             190      0.31%     97.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             308      0.50%     97.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             527      0.86%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             143      0.23%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              33      0.05%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              36      0.06%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.03%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              32      0.05%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              22      0.04%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             426      0.69%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              45      0.07%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              33      0.05%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              35      0.06%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              13      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            31      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total          129462                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples        129462                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.853911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.595936                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        4.789289                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19          125866     97.22%     97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1229      0.95%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             433      0.33%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             197      0.15%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             330      0.25%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             524      0.40%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             121      0.09%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              23      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              39      0.03%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              16      0.01%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              43      0.03%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              23      0.02%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             425      0.33%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              36      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              42      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              37      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              19      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            35      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61522                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    31530968444                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55349205944                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6351530000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       24821.55                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total          129462                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    61876185756                       # Total ticks spent queuing
+system.physmem.totMemAccLat              108132979506                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  12335145000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25081.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  43571.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.58                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.34                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.56                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.34                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43831.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.06                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.71                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.04                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.71                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.31                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1047361                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    815697                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.94                       # Row buffer hit rate for writes
-system.physmem.avgGap                     21864788.20                       # Average gap between requests
-system.physmem.pageHitRate                      79.47                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1828287720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  997577625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4889757600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3480388560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1226219398425                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29718601656750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34308233025720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.467372                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49439480717043                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713811840000                       # Time in different power states
+system.physmem.avgWrQLen                        25.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    2056722                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1654173                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.81                       # Row buffer hit rate for writes
+system.physmem.avgGap                     11083878.27                       # Average gap between requests
+system.physmem.pageHitRate                      79.82                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3550765680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1937421750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                9523885800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               7046332560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3367790100480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1313489115900                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29785116936750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34488454558920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.871313                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49548907375208                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1721774080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    170428636707                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    291487862292                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1810756080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  988011750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5018598000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3479837760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1228704019020                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29716422156750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34308639338400                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.475289                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49435820968594                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713811840000                       # Time in different power states
+system.physmem_1.actEnergy                 3541066200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1932129375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                9718893600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               7092645120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3367790100480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1316895447015                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29782128927000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34489099208790                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.883816                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49543906734220                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1721774080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    174088371406                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    296486485780                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -340,15 +337,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               225557622                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         150824960                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12221670                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            159273353                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               104130221                       # Number of BTB hits
+system.cpu.branchPred.lookups               288825634                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         198097109                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          13566789                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            207338959                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               136913226                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.378307                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30957399                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             344598                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             66.033526                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                37451224                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             402112                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -379,45 +376,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks            199616                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong        199616                       # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples       199616                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0       199616    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total       199616                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks            346524                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        346524                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       346524                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       346524    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       346524                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples   1622408500                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0   1622408500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total   1622408500                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K       155025     91.25%     91.25% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M        14865      8.75%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total       169890                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       199616                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K       271954     90.33%     90.33% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        29125      9.67%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       301079                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       346524                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       199616                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       169890                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       346524                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       301079                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       169890                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total       369506                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       301079                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       647603                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            160527490                       # DTB read hits
-system.cpu.checker.dtb.read_misses             148526                       # DTB read misses
-system.cpu.checker.dtb.write_hits           145616651                       # DTB write hits
-system.cpu.checker.dtb.write_misses             51090                       # DTB write misses
-system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
+system.cpu.checker.dtb.read_hits            204557812                       # DTB read hits
+system.cpu.checker.dtb.read_misses             253438                       # DTB read misses
+system.cpu.checker.dtb.write_hits           188384851                       # DTB write hits
+system.cpu.checker.dtb.write_misses             93086                       # DTB write misses
+system.cpu.checker.dtb.flush_tlb                   22                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid        79428                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid            2050                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            72318                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_tlb_mva_asid       126406                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid            2406                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries            87812                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           7517                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults          10297                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults             19125                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        160676016                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       145667741                       # DTB write accesses
+system.cpu.checker.dtb.perms_faults             24573                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses        204811250                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       188477937                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 306144141                       # DTB hits
-system.cpu.checker.dtb.misses                  199616                       # DTB misses
-system.cpu.checker.dtb.accesses             306343757                       # DTB accesses
+system.cpu.checker.dtb.hits                 392942663                       # DTB hits
+system.cpu.checker.dtb.misses                  346524                       # DTB misses
+system.cpu.checker.dtb.accesses             393289187                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -447,46 +444,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.walks            120521                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong        120521                       # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples       120521                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0       120521    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total       120521                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walks            130770                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        130770                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       130770                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       130770    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       130770                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.itb.walker.walksPending::samples   1621807000                       # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walksPending::0   1621807000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walksPending::total   1621807000                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K       108578     98.83%     98.83% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::2M         1286      1.17%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total       109864                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::4K       116506     98.90%     98.90% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::2M         1293      1.10%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       117799                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       120521                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       120521                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       130770                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       130770                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109864                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109864                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total       230385                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            853734937                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             120521                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       117799                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       117799                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       248569                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits           1104906556                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             130770                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
 system.cpu.checker.itb.write_misses                 0                       # DTB write misses
-system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb                   22                       # Number of times complete TLB was flushed
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid        79428                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid            2050                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            52057                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb_mva_asid       126406                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid            2406                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries            60682                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        853855458                       # ITB inst accesses
-system.cpu.checker.itb.hits                 853734937                       # DTB hits
-system.cpu.checker.itb.misses                  120521                       # DTB misses
-system.cpu.checker.itb.accesses             853855458                       # DTB accesses
-system.cpu.checker.numCycles               1003246954                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses       1105037326                       # ITB inst accesses
+system.cpu.checker.itb.hits                1104906556                       # DTB hits
+system.cpu.checker.itb.misses                  130770                       # DTB misses
+system.cpu.checker.itb.accesses            1105037326                       # DTB accesses
+system.cpu.checker.numCycles               1298799784                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -518,87 +515,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    951838                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                951838                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16475                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       156308                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       435006                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       516832                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  1986.510123                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-32767       508349     98.36%     98.36% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-65535         5443      1.05%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-98303         1244      0.24%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::98304-131071         1085      0.21%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-163839          165      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::163840-196607          178      0.03%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-229375          121      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::229376-262143           54      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-294911           95      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::294912-327679            7      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-360447            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::360448-393215           38      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-425983           41      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::425984-458751            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       516832                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       485267                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       475094     97.90%     97.90% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         9290      1.91%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          546      0.11%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          199      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           82      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           20      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       485267                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 776250627376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.722476                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.519579                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  774163165376     99.73%     99.73% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1120728500      0.14%     99.88% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     435636500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     187638500      0.02%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     148036000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    113935000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     26323500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     52542500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2621500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 776250627376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        156309     90.46%     90.46% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         16475      9.54%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       172784                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       951838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                   1430156                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong               1430156                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        30793                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       273791                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       677378                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       752778                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2375.228819                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       746726     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         4359      0.58%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          685      0.09%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          394      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          311      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215          120      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751          171      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       752778                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       802636                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       783977     97.68%     97.68% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071        16023      2.00%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1555      0.19%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          558      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          316      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          129      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           37      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           22      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       802636                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 1044763922448                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.739319                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.520240                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  1040800473448     99.62%     99.62% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    2579873000      0.25%     99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     637994000      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     271834500      0.03%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     201274500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    132884500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     46819000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     89469000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      3255500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19        45000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 1044763922448                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        273792     89.89%     89.89% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         30793     10.11%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       304585                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data      1430156                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       951838                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       172784                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total      1430156                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       304585                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       172784                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1124622                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       304585                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1734741                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    170417440                       # DTB read hits
-system.cpu.dtb.read_misses                     677013                       # DTB read misses
-system.cpu.dtb.write_hits                   148384109                       # DTB write hits
-system.cpu.dtb.write_misses                    274825                       # DTB write misses
-system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
+system.cpu.dtb.read_hits                    217117628                       # DTB read hits
+system.cpu.dtb.read_misses                    1002788                       # DTB read misses
+system.cpu.dtb.write_hits                   192115888                       # DTB write hits
+system.cpu.dtb.write_misses                    427368                       # DTB write misses
+system.cpu.dtb.flush_tlb                           22                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               79428                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    2050                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72556                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid              126406                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    2406                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    87986                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10696                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                  15675                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     70061                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                171094453                       # DTB read accesses
-system.cpu.dtb.write_accesses               148658934                       # DTB write accesses
+system.cpu.dtb.perms_faults                     85972                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                218120416                       # DTB read accesses
+system.cpu.dtb.write_accesses               192543256                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         318801549                       # DTB hits
-system.cpu.dtb.misses                          951838                       # DTB misses
-system.cpu.dtb.accesses                     319753387                       # DTB accesses
+system.cpu.dtb.hits                         409233516                       # DTB hits
+system.cpu.dtb.misses                         1430156                       # DTB misses
+system.cpu.dtb.accesses                     410663672                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -628,877 +622,877 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    162167                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                162167                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1433                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       122178                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17760                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       144407                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1087.128740                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  7079.961036                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       143546     99.40%     99.40% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          491      0.34%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303          245      0.17%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           86      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839           14      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    177415                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                177415                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1441                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       130680                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        19804                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       157611                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1499.045117                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 10189.386950                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       155888     98.91%     98.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          579      0.37%     99.27% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          739      0.47%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          292      0.19%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           35      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           38      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375           19      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       144407                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       141371                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27408.566821                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       138940     98.28%     98.28% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         2106      1.49%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          209      0.15%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           62      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           27      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           18      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       157611                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       151925                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29463.087050                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       146250     96.26%     96.26% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         4800      3.16%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          534      0.35%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          196      0.13%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           80      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           44      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           15      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       141371                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 655988501088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.936740                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.243710                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     41542191152      6.33%      6.33% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    614402729936     93.66%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        43110500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          467500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total       151925                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 920206753364                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.948994                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.220270                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     46987798652      5.11%      5.11% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    873167595712     94.89%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        50573500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          783500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 655988501088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        122178     98.84%     98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1433      1.16%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       123611                       # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 920206753364                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        130680     98.91%     98.91% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1441      1.09%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       132121                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162167                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       162167                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       177415                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       177415                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123611                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       123611                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       285778                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    358625455                       # ITB inst hits
-system.cpu.itb.inst_misses                     162167                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       132121                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       132121                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       309536                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    461294711                       # ITB inst hits
+system.cpu.itb.inst_misses                     177415                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb                           22                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               79428                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    2050                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53363                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid              126406                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    2406                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    62159                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    372145                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    458083                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                358787622                       # ITB inst accesses
-system.cpu.itb.hits                         358625455                       # DTB hits
-system.cpu.itb.misses                          162167                       # DTB misses
-system.cpu.itb.accesses                     358787622                       # DTB accesses
-system.cpu.numCycles                       1590418745                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                461472126                       # ITB inst accesses
+system.cpu.itb.hits                         461294711                       # DTB hits
+system.cpu.itb.misses                          177415                       # DTB misses
+system.cpu.itb.accesses                     461472126                       # DTB accesses
+system.cpu.numCycles                       2141240199                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          646410999                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1006402404                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225557622                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135087620                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     866562323                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26107474                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3678311                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                25439                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9275413                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1023850                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          676                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 358236204                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6112300                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   49056                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1540030748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.765724                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.157325                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          785638694                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1289733601                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   288825634                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          174364450                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1267374465                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29210356                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    4418623                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                28241                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles      12152128                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1217886                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          633                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 460817774                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6728045                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   53516                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         2085435848                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.725171                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.139838                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                979927440     63.63%     63.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                215057699     13.96%     77.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70955696      4.61%     82.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                274089913     17.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1366680941     65.53%     65.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                278589155     13.36%     78.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 86788366      4.16%     83.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                353377386     16.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1540030748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.141823                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.632791                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                525466953                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             519947088                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 434864784                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50506307                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9245616                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33796734                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3867997                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1090931528                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29050280                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9245616                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                570424085                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                50840114                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      363017689                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 440398811                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             106104433                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1071115355                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6801917                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5040663                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 343395                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 645255                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               54344412                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20434                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1018974666                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1651092433                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1266893179                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1473696                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             953236782                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65737881                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           27206823                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23528426                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 103688094                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            174464093                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           151959443                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9931077                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9032567                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1035787653                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27506074                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1051526043                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3293799                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60619533                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33780075                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         314140                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1540030748                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.682795                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.925415                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           2085435848                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.134887                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.602330                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                612239538                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             852574124                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 529946172                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              80118083                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10557931                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             41219534                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               4107385                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1403247413                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              32566835                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               10557931                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                674962554                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                85247440                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      550746700                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 547461697                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             216459526                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1379612307                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               7971383                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7360618                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 963827                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1074082                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents              133209723                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            22971                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1329803577                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2195861380                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1637517470                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1437183                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1251935276                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 77868298                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           43546894                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       39087703                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 166786807                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            221659276                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           196613901                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12565776                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11015266                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1326936815                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            43849103                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1356961205                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4098709                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        72699747                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41430931                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         372473                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    2085435848                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.650685                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.914510                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           888949202     57.72%     57.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           336251490     21.83%     79.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           235798342     15.31%     94.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72468185      4.71%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6544331      0.42%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19198      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0          1239320860     59.43%     59.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           449936886     21.58%     81.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           291017288     13.95%     94.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            95682212      4.59%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9449903      0.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               28699      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1540030748                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      2085435848                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                58035888     35.01%     35.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  99674      0.06%     35.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26738      0.02%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              574      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44566242     26.88%     61.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              63041416     38.03%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                73477453     34.17%     34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  90486      0.04%     34.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26768      0.01%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              385      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               57876005     26.91%     61.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              83594438     38.87%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             724142674     68.87%     68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2543730      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122779      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 376      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121012      0.01%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            174312709     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           150282706     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                31      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             937288786     69.07%     69.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2936989      0.22%     69.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                129444      0.01%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 372      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         114407      0.01%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            221949724     16.36%     85.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194541406     14.34%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1051526043                       # Type of FU issued
-system.cpu.iq.rate                           0.661163                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   165770532                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157648                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3809671307                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1123107931                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1033541701                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2475857                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             947397                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       910004                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1215741366                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1555198                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4333965                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1356961205                       # Type of FU issued
+system.cpu.iq.rate                           0.633727                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   215065535                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.158491                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5016097714                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1442740685                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1335189379                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2424787                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             927446                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       888349                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1570502436                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1524273                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5709357                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13839303                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14833                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       143349                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6338712                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     16902439                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24350                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       184211                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8196884                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2540349                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1552925                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      3577769                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1870440                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9245616                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6389360                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               5797347                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1063516239                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               10557931                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12374030                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7706525                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1371058602                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             174464093                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            151959443                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           23100216                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  59008                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               5663632                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         143349                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3667729                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5111764                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8779493                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1040328227                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             170406440                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10257681                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             221659276                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            196613901                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           38550114                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 178028                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               7343410                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         184211                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4239042                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5703306                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              9942348                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1343677933                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             217120223                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          11882036                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222512                       # number of nop insts executed
-system.cpu.iew.exec_refs                    318786335                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                197400349                       # Number of branches executed
-system.cpu.iew.exec_stores                  148379895                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.654122                       # Inst execution rate
-system.cpu.iew.wb_sent                     1035262700                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1034451705                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 440415620                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 712619707                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        272684                       # number of nop insts executed
+system.cpu.iew.exec_refs                    409245203                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                255119365                       # Number of branches executed
+system.cpu.iew.exec_stores                  192124980                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.627523                       # Inst execution rate
+system.cpu.iew.wb_sent                     1337102879                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1336077728                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 573421420                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 940568778                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.650427                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618023                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.623974                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.609654                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51498978                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        27191934                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8413549                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1528028900                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.656188                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.286676                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        62140410                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        43476630                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9519542                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   2071346493                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.626687                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.267080                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1013092181     66.30%     66.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    289858237     18.97%     85.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    121052617      7.92%     93.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36682667      2.40%     95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28563883      1.87%     97.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14105791      0.92%     98.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8655946      0.57%     98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4198069      0.27%     99.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11819509      0.77%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1395640231     67.38%     67.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    393909449     19.02%     86.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    150461425      7.26%     93.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     44316735      2.14%     95.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     35977476      1.74%     97.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     18232281      0.88%     98.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10892931      0.53%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5452952      0.26%     99.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     16463013      0.79%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1528028900                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            853325819                       # Number of instructions committed
-system.cpu.commit.committedOps             1002674190                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   2071346493                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1104366834                       # Number of instructions committed
+system.cpu.commit.committedOps             1298086167                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      306245520                       # Number of memory references committed
-system.cpu.commit.loads                     160624789                       # Number of loads committed
-system.cpu.commit.membars                     6977905                       # Number of memory barriers committed
-system.cpu.commit.branches                  190474151                       # Number of branches committed
-system.cpu.commit.fp_insts                     896785                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 921116747                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25400785                       # Number of function calls committed.
+system.cpu.commit.refs                      393173853                       # Number of memory references committed
+system.cpu.commit.loads                     204756836                       # Number of loads committed
+system.cpu.commit.membars                     9104821                       # Number of memory barriers committed
+system.cpu.commit.branches                  246834909                       # Number of branches committed
+system.cpu.commit.fp_insts                     874964                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1186447841                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             30876862                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        694059947     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2158876      0.22%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98131      0.01%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111674      0.01%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       160624789     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      145620731     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        902159630     69.50%     69.50% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2542825      0.20%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           103949      0.01%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       105868      0.01%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       204756836     15.77%     85.49% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      188417017     14.51%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1002674190                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11819509                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2562796067                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2120254358                       # The number of ROB writes
-system.cpu.timesIdled                         8129447                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        50387997                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101057024238                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   853325819                       # Number of Instructions Simulated
-system.cpu.committedOps                    1002674190                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.863788                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.863788                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.536542                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.536542                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1231590969                       # number of integer regfile reads
-system.cpu.int_regfile_writes               735370650                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462122                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   782688                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 226859046                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                227515194                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2534481060                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               27245755                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9758519                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.983709                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           284707567                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9759031                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.173754                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total        1298086167                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              16463013                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3405665880                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2734432791                       # The number of ROB writes
+system.cpu.timesIdled                         9009507                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        55804351                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100983102115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                  1104366834                       # Number of Instructions Simulated
+system.cpu.committedOps                    1298086167                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.938885                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.938885                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.515760                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.515760                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1596434625                       # number of integer regfile reads
+system.cpu.int_regfile_writes               940526506                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1424965                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   765828                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 311708448                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                312593649                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              3410532874                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               44362921                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements          13614186                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.983787                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           360288791                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          13614698                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             26.463223                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1642601500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.983709                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.983787                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1243872376                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1243872376                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    147964440                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147964440                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128940955                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128940955                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       380183                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        380183                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       324678                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       324678                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3327415                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3327415                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3725844                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3725844                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     276905395                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        276905395                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    277285578                       # number of overall hits
-system.cpu.dcache.overall_hits::total       277285578                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9612542                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9612542                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11385353                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11385353                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1184834                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1184834                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1232047                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1232047                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       450033                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       450033                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1595334423                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1595334423                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    186468319                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       186468319                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    162903680                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      162903680                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       463393                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        463393                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       334025                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       334025                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4787397                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4787397                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      5271269                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      5271269                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     349371999                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        349371999                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    349835392                       # number of overall hits
+system.cpu.dcache.overall_hits::total       349835392                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12723000                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12723000                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     18625078                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     18625078                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      2035956                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      2035956                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1270469                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1270469                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       547335                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       547335                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20997895                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20997895                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22182729                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22182729                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 144669003500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 330867751444                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  63675897168                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  63675897168                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6433485000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6433485000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     31348078                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       31348078                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     33384034                       # number of overall misses
+system.cpu.dcache.overall_misses::total      33384034                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 203343916000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 979374659621                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  74427778402                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  74427778402                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8800618500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   8800618500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       251000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       251000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 475536754944                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 475536754944                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 475536754944                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 475536754944                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    157576982                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    157576982                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    140326308                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    140326308                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1565017                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1565017                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1556725                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1556725                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3777448                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3777448                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3725851                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3725851                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    297903290                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    297903290                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    299468307                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    299468307                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061002                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.061002                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081135                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081135                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.757074                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.757074                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791435                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791435                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119137                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119137                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070486                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070486                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074074                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074074                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1182718575621                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1182718575621                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    199191319                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    199191319                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    181528758                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    181528758                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2499349                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2499349                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5334732                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      5334732                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      5271276                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      5271276                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    380720077                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    380720077                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    383219426                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    383219426                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.063873                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.063873                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.102601                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.102601                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.814595                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.814595                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791819                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791819                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.102598                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.102598                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.082339                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.082339                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.087115                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.087115                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22646.877458                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21437.252150                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     35158879                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37728.583412                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35427.671072                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     46020939                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1606955                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           2096301                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.879193                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.953402                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7549082                       # number of writebacks
-system.cpu.dcache.writebacks::total           7549082                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4467834                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4467834                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9360902                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9360902                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7079                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7079                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219205                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219205                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13828736                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13828736                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13828736                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13828736                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5144708                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5144708                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2024451                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2024451                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1178103                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1178103                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224968                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1224968                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230828                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       230828                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks     10299062                       # number of writebacks
+system.cpu.dcache.writebacks::total          10299062                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5706012                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5706012                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15543150                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total     15543150                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7171                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7171                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       263403                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       263403                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     21249162                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     21249162                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     21249162                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     21249162                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7016988                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7016988                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3081928                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      3081928                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2029224                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      2029224                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1263298                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1263298                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       283932                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       283932                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7169159                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7169159                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8347262                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8347262                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75818409500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75818409500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  57062160713                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  57062160713                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20148080000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20148080000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  62191648168                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  62191648168                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3063087000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3063087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     10098916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     10098916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     12128140                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     12128140                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  32373018500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  32373018500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  72874671402                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  72874671402                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   4076865500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   4076865500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       244000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       244000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 132880570213                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 153028650213                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5828327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5828327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5707957967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5707957967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11536285467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11536285467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032649                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032649                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014427                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014427                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.752773                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.752773                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786888                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786888                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061107                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061107                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024065                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024065                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027874                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027874                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 254057212172                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 286430230672                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5829096500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5829096500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5708243467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5708243467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11537339967                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11537339967                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035227                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035227                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016978                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016978                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.811901                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.811901                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787350                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787350                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.053223                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.053223                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026526                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026526                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031648                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031648                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15042093                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.944879                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           342405629                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15042605                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.762389                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements          16756542                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.945135                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           443237235                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          16757054                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             26.450785                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       17214303500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.944879                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999892                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.945135                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999893                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999893                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         373257734                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        373257734                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    342405629                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       342405629                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     342405629                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        342405629                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    342405629                       # number of overall hits
-system.cpu.icache.overall_hits::total       342405629                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15809279                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15809279                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15809279                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15809279                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15809279                       # number of overall misses
-system.cpu.icache.overall_misses::total      15809279                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208403044384                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208403044384                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208403044384                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208403044384                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208403044384                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    358214908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    358214908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    358214908                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    358214908                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    358214908                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    358214908                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044134                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044134                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044134                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044134                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044134                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044134                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13182.324405                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13182.324405                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        15030                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         477553750                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        477553750                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    443237235                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       443237235                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     443237235                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        443237235                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    443237235                       # number of overall hits
+system.cpu.icache.overall_hits::total       443237235                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     17559241                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      17559241                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     17559241                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       17559241                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     17559241                       # number of overall misses
+system.cpu.icache.overall_misses::total      17559241                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 232141013891                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 232141013891                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 232141013891                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 232141013891                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 232141013891                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    460796476                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    460796476                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    460796476                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    460796476                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    460796476                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    460796476                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.038106                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.038106                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.038106                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.038106                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.038106                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.038106                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13220.446937                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13220.446937                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        15959                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1210                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1225                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    12.421488                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    13.027755                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       766453                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       766453                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       766453                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       766453                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       766453                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       766453                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15042826                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15042826                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15042826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15042826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15042826                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15042826                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       801966                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       801966                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       801966                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       801966                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       801966                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       801966                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16757275                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     16757275                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     16757275                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     16757275                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     16757275                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     16757275                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 186915451392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 186915451392                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 208567956898                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 208567956898                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1594412000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   1594412000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041994                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.041994                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.041994                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036366                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036366                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036366                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.036366                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036366                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.036366                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1148683                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65278.817014                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46198537                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1210914                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.151790                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          2345734                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65318.237935                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           55622573                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2409067                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.088844                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      15659706000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   301.460755                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   460.210435                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7626.713626                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567520                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004600                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007022                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.116374                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300560                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996076                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          380                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61851                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          379                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          530                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2690                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5173                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53395                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.005798                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.943771                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        410382726                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       410382726                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       788948                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       299798                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1088746                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7549082                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7549082                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9455                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9455                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   265.508156                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   348.644093                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6890.433367                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.546517                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004051                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005320                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.105140                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.335649                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996677                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          240                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63093                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          240                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2664                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5217                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003662                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962723                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        506469360                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       506469360                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1313351                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       329734                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1643085                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks     10299062                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total     10299062                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        12887                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        12887                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1576072                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1576072                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14958434                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14958434                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6296354                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6296354                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       732370                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       732370                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       788948                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       299798                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14958434                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7872426                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        23919606                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       788948                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       299798                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14958434                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7872426                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23919606                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3175                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         2963                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6138                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34552                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34552                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1723701                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1723701                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     16658716                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     16658716                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      8894179                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      8894179                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       672751                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       672751                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker      1313351                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       329734                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     16658716                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     10617880                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        28919681                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker      1313351                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       329734                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     16658716                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data     10617880                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       28919681                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        10281                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         8711                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        18992                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data        47777                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        47777                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       407912                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       407912                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        84184                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        84184                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       253746                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       253746                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       492598                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       492598                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         3175                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         2963                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        84184                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       661658                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        751980                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         3175                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         2963                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        84184                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       661658                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       751980                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    276956000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    265379500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    542335500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    544075000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total    544075000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data      1312732                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total      1312732                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        98354                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        98354                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       420801                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       420801                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       590547                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       590547                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker        10281                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         8711                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        98354                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1733533                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1850879                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker        10281                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         8711                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        98354                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1733533                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1850879                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    914040000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    769017500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1683057500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    621639500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total    621639500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  36032836500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  36032836500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   7082572500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   7082572500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  22536354000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  22536354000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  51203919000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total  51203919000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    276956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    265379500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   7082572500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  58569190500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  66194098500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    276956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    265379500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   7082572500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  58569190500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  66194098500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       792123                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       302761                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1094884                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      7549082                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      7549082                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        44007                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        44007                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 120138160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 120138160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8298337000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   8298337000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  37547469500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  37547469500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  62416970000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total  62416970000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    914040000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    769017500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   8298337000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 157685629500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 167667024000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    914040000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    769017500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   8298337000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 157685629500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 167667024000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1323632                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       338445                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1662077                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks     10299062                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total     10299062                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        60664                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        60664                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            7                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            7                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1983984                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1983984                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15042618                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     15042618                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6550100                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6550100                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224968                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1224968                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       792123                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       302761                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     15042618                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      8534084                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     24671586                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       792123                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       302761                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     15042618                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8534084                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     24671586                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.009787                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.005606                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.785148                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.785148                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      3036433                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      3036433                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     16757070                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     16757070                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      9314980                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      9314980                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1263298                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1263298                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1323632                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       338445                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     16757070                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     12351413                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     30770560                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1323632                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       338445                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     16757070                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     12351413                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     30770560                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007767                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.025738                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.011427                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787568                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787568                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.205602                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.205602                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005596                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005596                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038739                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038739                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402131                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402131                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.009787                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005596                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.077531                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.030480                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.009787                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005596                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.077531                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.030480                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.432327                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.432327                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005869                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005869                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.045175                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.045175                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.467465                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.467465                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.025738                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005869                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.140351                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060151                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.007767                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.025738                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005869                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.140351                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060151                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88905.748468                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88281.196189                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 88619.287068                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13011.271114                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13011.271114                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91517.659355                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91517.659355                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84372.135348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84372.135348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89228.565284                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89228.565284                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 105693.484177                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 105693.484177                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88905.748468                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88281.196189                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84372.135348                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90962.000435                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 90587.782346                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88905.748468                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88281.196189                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84372.135348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90962.000435                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 90587.782346                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1507,194 +1501,194 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       967181                       # number of writebacks
-system.cpu.l2cache.writebacks::total           967181                       # number of writebacks
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3175                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2963                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6138                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1073                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1073                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34552                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34552                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      2075008                       # number of writebacks
+system.cpu.l2cache.writebacks::total          2075008                       # number of writebacks
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        10281                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         8711                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        18992                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1261                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1261                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        47777                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        47777                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       407912                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       407912                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        84184                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        84184                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       253725                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       253725                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       492598                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       492598                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3175                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2963                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        84184                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       661637                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       751959                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3175                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2963                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        84184                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       661637                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       751959                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1312732                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total      1312732                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        98354                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        98354                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       420779                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       420779                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       590547                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       590547                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        10281                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         8711                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        98354                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1733511                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1850857                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker        10281                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         8711                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        98354                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1733511                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1850857                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54973                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54987                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88669                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    235749500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    480955500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    717374500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    717374500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88690                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    811230000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    681907500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1493137500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    993052500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    993052500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       161500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       161500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31953716500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31953716500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   6240732500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   6240732500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19997854000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19997854000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  46277939000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  46277939000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    235749500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   6240732500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  51951570500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  58673258500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    235749500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   6240732500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  51951570500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  58673258500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107010840000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107010840000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7314797000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7314797000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33338388000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33338388000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  56511500000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  56511500000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    811230000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    681907500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7314797000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140349228000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 149157162500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    811230000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    681907500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7314797000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140349228000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 149157162500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5407344500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6735569000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5315951000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5315951000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5407939500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6736164000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5316157000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5316157000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10723295500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12051520000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10724096500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12052321000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007767                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.025738                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.011427                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785148                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785148                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787568                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787568                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.205602                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.205602                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005596                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038736                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038736                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402131                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402131                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030479                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030479                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.432327                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.432327                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005869                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005869                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.045172                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.045172                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.467465                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.467465                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007767                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.025738                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005869                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.140349                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060150                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007767                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.025738                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005869                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.140349                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060150                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1633565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23227278                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8622904                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     17438576                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        44010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2244083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      28317103                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback     12480720                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     20347986                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        60667                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        44017                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1983984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1983984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15042826                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6558947                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1331632                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1224968                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45167572                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29499463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       732865                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1940611                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          77340511                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    963068272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1029563294                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2422088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6336984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2001390638                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1864369                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     52693428                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.056141                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.230194                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        60674                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      3036433                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      3036433                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     16757275                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      9323830                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1369962                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1263298                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50310988                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     41099763                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       807461                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3043712                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          95261924                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1072793136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1449869810                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2707560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10589056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2535959562                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     3104722                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     65657900                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.072586                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.259455                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           49735173     94.39%     94.39% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            2958255      5.61%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           60892075     92.74%     92.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            4765825      7.26%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       52693428                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    33222815494                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       65657900                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    41856500497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1182000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1150500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22592032956                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   25164199957                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13487423434                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   19241199390                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     430634727                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     469526277                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1148958035                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1720822991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1713,11 +1707,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1734,11 +1728,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1767,71 +1761,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           568813596                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568892559                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115455                       # number of replacements
-system.iocache.tags.tagsinuse               10.423947                       # Cycle average of tags in use
+system.iocache.tags.replacements               115458                       # number of replacements
+system.iocache.tags.tagsinuse               10.449705                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13095311635000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544418                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.879529                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221526                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429971                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651497                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13095311633000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.528028                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.921676                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.220502                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.432605                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653107                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039623                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039650                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8810                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8847                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8810                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8850                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8810                       # number of overall misses
-system.iocache.overall_misses::total             8850                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
+system.iocache.overall_misses::total             8853                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1621911166                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1626980166                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1615020135                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1620089135                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12610487430                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12610487430                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12610143424                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12610143424                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1621911166                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1627331166                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1615020135                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1620440135                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1621911166                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1627331166                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1615020135                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1620440135                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8810                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8847                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8810                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8850                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8810                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8850                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1846,54 +1840,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183901.906409                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183060.919209                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183879.227797                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 183254.298763                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183038.533266                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183879.227797                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31681                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 183254.298763                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183038.533266                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31319                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3345                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3376                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.471151                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.276955                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8810                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8810                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8850                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8810                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8850                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1181411166                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1184630166                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1174370135                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1177589135                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7277287430                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7277287430                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7276943424                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7276943424                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1181411166                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1184831166                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1174370135                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1177790135                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1181411166                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1184831166                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1174370135                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1177790135                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1908,72 +1902,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 133038.533266                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 133038.533266                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54973                       # Transaction distribution
-system.membus.trans_dist::ReadResp             407867                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::Writeback           1073811                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           187846                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35358                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54987                       # Transaction distribution
+system.membus.trans_dist::ReadResp             601962                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33703                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33703                       # Transaction distribution
+system.membus.trans_dist::Writeback           2181638                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           277040                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            48552                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           35361                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            899707                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           899707                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        352894                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           48555                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1902507                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1902507                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        546975                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3753956                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3883578                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4225292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      7371150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      7500814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341657                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341657                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7842471                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    141818700                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    141988686                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7244096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7244096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               149232782                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2955                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2747442                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    289319820                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    289489890                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7242112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7242112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               296732002                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2989                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5154600                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2747442    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5154600    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2747442                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           104159500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5154600                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           104456000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5443500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5495500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7279924206                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         14230820482                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6776038462                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        13100845399                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228860056                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228852771                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1984,11 +1978,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -2017,17 +2011,17 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16150                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    20008                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index def82d401..cd4c4065f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -201,7 +201,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -542,7 +542,7 @@ opLat=4
 pipelined=true
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -652,7 +652,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -835,7 +835,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1176,7 +1176,7 @@ opLat=4
 pipelined=true
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -1286,7 +1286,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -1399,7 +1399,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1434,7 +1434,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1849,9 +1849,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
index 4c70e8d66..ebddc1020 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
@@ -11,3 +11,5 @@ warn: allocating bonus target for snoop
 warn: allocating bonus target for snoop
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
index 0fe5c8030..b9e9b0535 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 11:05:08
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 14 2015 23:59:20
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47309826639000 because m5_exit instruction encountered
+Exiting @ tick 47309815475000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 6bf45e0f6..9055480cb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,172 +1,172 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.309827                       # Number of seconds simulated
-sim_ticks                                47309826639000                       # Number of ticks simulated
-final_tick                               47309826639000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.309815                       # Number of seconds simulated
+sim_ticks                                47309815475000                       # Number of ticks simulated
+final_tick                               47309815475000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115168                       # Simulator instruction rate (inst/s)
-host_op_rate                                   135435                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5759542779                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 728780                       # Number of bytes of host memory used
-host_seconds                                  8214.16                       # Real time elapsed on the host
-sim_insts                                   946011818                       # Number of instructions simulated
-sim_ops                                    1112485532                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  80227                       # Simulator instruction rate (inst/s)
+host_op_rate                                    94350                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4125416978                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 770696                       # Number of bytes of host memory used
+host_seconds                                 11467.89                       # Real time elapsed on the host
+sim_insts                                   920033396                       # Number of instructions simulated
+sim_ops                                    1081995375                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       184448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       167936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          5084832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         44767048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     19339456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       176320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       161792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2535456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         18891728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     20722048                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        420544                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            112451608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      5084832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2535456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7620288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     93755328                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       174848                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       152512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4545760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         43325128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     19040640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       136192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       127232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2550688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         17518992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     15564544                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        439744                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            103576280                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4545760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2550688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7096448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     86607680                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          93775912                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2882                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2624                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             95403                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            699498                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       302179                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2755                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2528                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             39660                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            295196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       323782                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6571                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1773078                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1464927                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          86628264                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2732                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             86980                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            676968                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       297510                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2128                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1988                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             39898                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            273747                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       243196                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6871                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1634401                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1353245                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1467501                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3550                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              107479                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              946253                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       408783                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3727                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               53593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              399319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       438007                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8889                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2376919                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         107479                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          53593                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             161072                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1981731                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1355819                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3696                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          3224                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               96085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              915775                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       402467                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2879                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2689                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               53915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              370304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       328992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9295                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2189319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          96085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          53915                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             149999                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1830649                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1982166                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1981731                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3899                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3550                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             107479                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             946688                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       408783                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3727                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              53593                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             399319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       438007                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8889                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4359084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1773078                       # Number of read requests accepted
-system.physmem.writeReqs                      1467501                       # Number of write requests accepted
-system.physmem.readBursts                     1773078                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1467501                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                113443520                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     33472                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  93774528                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 112451608                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               93775912                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      523                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1831084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1830649                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3696                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         3224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              96085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             916210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       402467                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2879                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2689                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              53915                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             370304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       328992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9295                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4020403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1634401                       # Number of read requests accepted
+system.physmem.writeReqs                      1355819                       # Number of write requests accepted
+system.physmem.readBursts                     1634401                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1355819                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                104570688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     30976                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  86627008                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 103576280                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               86628264                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      484                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         224875                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              113386                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              120644                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              108661                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              115173                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              103078                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              114921                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              108340                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              105879                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               98747                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              127278                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              99197                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             111650                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             107228                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             113583                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             112177                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             112613                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               94420                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               97266                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               90974                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               94616                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               87287                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               94599                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               89304                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               90590                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               84448                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               90113                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              85465                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              93225                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              88655                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              95246                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              93025                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              95994                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         224542                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              101664                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              108898                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               93497                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              100406                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               99202                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              111502                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              102695                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              105017                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               95660                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              119055                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              95976                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              99461                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              97685                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              98791                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             102404                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             102004                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               83138                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               88505                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               79517                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               83751                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               82730                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               91993                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               85763                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               87476                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               80354                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               84626                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              82451                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              83951                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              82076                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              85332                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              85178                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              86706                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          83                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47309825190500                       # Total gap between requests
+system.physmem.numWrRetry                          54                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47309813973500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1751720                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1613043                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1464927                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    608524                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    449703                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    194607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    195607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    116312                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     71048                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     40112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     36551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     32712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     10303                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     5634                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     3467                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     2280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1844                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      910                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      582                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      168                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1353245                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    578892                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    412924                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    179105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    178845                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    107013                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     63608                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     33748                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     30706                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     27701                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      8546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     4578                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2741                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1676                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1308                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      831                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      574                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      473                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      388                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      147                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
@@ -188,170 +188,163 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    20153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    23447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    36691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    44303                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    53186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    62828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    72210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    82749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    88726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    95528                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    97547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   101638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   103246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   108748                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   123417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   115282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   109625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    98032                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     7953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     4632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    19221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    22339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    35019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    41881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    50025                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    59082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    67725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    77253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    82334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    88348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    89969                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    94025                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    94875                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    99373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   112446                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   104983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    99994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    89665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     6823                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     3907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1575                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      893                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      774                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      501                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      136                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      281                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1119709                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      185.063798                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     114.156365                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.940793                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         674939     60.28%     60.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       219039     19.56%     79.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        70659      6.31%     86.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        37987      3.39%     89.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        28223      2.52%     92.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        14545      1.30%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        15798      1.41%     94.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9595      0.86%     95.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        48924      4.37%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1119709                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         84177                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.057367                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      250.150754                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          84175    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::61                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      146                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1028414                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      185.914855                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     114.442896                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     243.413322                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         618503     60.14%     60.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       202037     19.65%     79.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        65034      6.32%     86.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35244      3.43%     89.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        24806      2.41%     91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        13355      1.30%     93.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        14362      1.40%     94.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8867      0.86%     95.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        46206      4.49%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1028414                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         77347                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.124284                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      260.957500                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          77345    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::69632-73727            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           84177                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         84177                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.406501                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.998569                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.063432                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           78913     93.75%     93.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2654      3.15%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             594      0.71%     97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             256      0.30%     97.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             356      0.42%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             499      0.59%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             111      0.13%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              36      0.04%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              47      0.06%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              28      0.03%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              36      0.04%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              26      0.03%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             418      0.50%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              37      0.04%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              46      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              46      0.05%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              12      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           77347                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         77347                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.499670                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.056595                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.288618                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           72278     93.45%     93.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2489      3.22%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             567      0.73%     97.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             275      0.36%     97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             300      0.39%     98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             491      0.63%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             126      0.16%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              49      0.06%     99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              40      0.05%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              44      0.06%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              35      0.05%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              27      0.03%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             405      0.52%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              43      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              50      0.06%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              52      0.07%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              16      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            25      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            23      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           84177                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    95142418476                       # Total ticks spent queuing
-system.physmem.totMemAccLat              128377824726                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8862775000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       53675.30                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::148-151             8      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           77347                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    84737173288                       # Total ticks spent queuing
+system.physmem.totMemAccLat              115373117038                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8169585000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       51861.37                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  72425.30                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.40                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.38                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.98                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  70611.37                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.21                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.83                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.19                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1427545                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    690525                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14599188.97                       # Average gap between requests
-system.physmem.pageHitRate                      65.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4299372000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2345887500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6942631800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4789082880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3090047684880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1174100419575                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27355981545000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31638506623635                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.751312                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45508743621503                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1579778980000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.70                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1319893                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    639153                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.78                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15821516.13                       # Average gap between requests
+system.physmem.pageHitRate                      65.57                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3982161960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2172806625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6418448400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4425017040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3090046667760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1165891095180                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27363173363250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31636109560215                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.700864                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45520771842112                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1579778460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    221302763997                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    209258446888                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 4165628040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2272912125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6883242600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4705588080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3090047684880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1168667714520                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27360747075750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31637489845995                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.729820                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45516677078545                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1579778980000                       # Time in different power states
+system.physmem_1.actEnergy                 3792625200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2069388750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6326026200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4345967520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3090046667760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1161508413915                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27367017820500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31635106909845                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.679671                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45527169156111                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1579778460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    213370138955                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    202865647889                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -385,15 +378,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              147637418                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         98315773                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7247820                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           103619610                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               67413734                       # Number of BTB hits
+system.cpu0.branchPred.lookups              147707110                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         98263896                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          7114286                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           103765470                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               67713845                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            65.058857                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               20080737                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            195189                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            65.256626                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               20037326                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            200169                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -424,84 +417,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   596316                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               596316                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13005                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90766                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       267964                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       328352                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  1967.306427                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       326191     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1511      0.46%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          485      0.15%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143           70      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           71      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           17      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   575296                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               575296                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12884                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88904                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       257665                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       317631                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2022.074357                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 12176.572384                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       315561     99.35%     99.35% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1443      0.45%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          466      0.15%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143           74      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           64      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           16      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       328352                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       293288                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       290000     98.88%     98.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2364      0.81%     99.68% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          368      0.13%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          346      0.12%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          119      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           72      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       293288                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 554812439744                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.594659                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.537153                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 553701545244     99.80%     99.80% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    589103000      0.11%     99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    238633000      0.04%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    116174000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9     85227000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     46829500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     15433000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     19112000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       363500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19        19500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 554812439744                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        90767     87.47%     87.47% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        13005     12.53%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       103772                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       596316                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       317631                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       284896                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 18154.968831                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15325.984047                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16062.585690                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767       269179     94.48%     94.48% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535        12793      4.49%     98.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303         1124      0.39%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          999      0.35%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839          121      0.04%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607          154      0.05%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375          275      0.10%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143           60      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           49      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679           59      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447           25      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983           18      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::491520-524287            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       284896                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 550505269948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.606717                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.533946                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 549425097448     99.80%     99.80% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    576911000      0.10%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    232215500      0.04%     99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    109337500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     81684000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     43624500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     15920500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     20013500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       440500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19        25500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 550505269948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        88905     87.34%     87.34% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        12884     12.66%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       101789                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       575296                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       596316                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       103772                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       575296                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101789                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       103772                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       700088                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101789                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       677085                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   107674804                       # DTB read hits
-system.cpu0.dtb.read_misses                    416109                       # DTB read misses
-system.cpu0.dtb.write_hits                   89240851                       # DTB write hits
-system.cpu0.dtb.write_misses                   180207                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   107498760                       # DTB read hits
+system.cpu0.dtb.read_misses                    398450                       # DTB read misses
+system.cpu0.dtb.write_hits                   89911233                       # DTB write hits
+system.cpu0.dtb.write_misses                   176846                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   37572                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      168                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7516                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              44378                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1065                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   36343                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      314                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  6513                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    38101                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               108090913                       # DTB read accesses
-system.cpu0.dtb.write_accesses               89421058                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    39209                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               107897210                       # DTB read accesses
+system.cpu0.dtb.write_accesses               90088079                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        196915655                       # DTB hits
-system.cpu0.dtb.misses                         596316                       # DTB misses
-system.cpu0.dtb.accesses                    197511971                       # DTB accesses
+system.cpu0.dtb.hits                        197409993                       # DTB hits
+system.cpu0.dtb.misses                         575296                       # DTB misses
+system.cpu0.dtb.accesses                    197985289                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -531,326 +530,332 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    85428                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                85428                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          771                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61190                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        10178                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        75250                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1283.993355                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  9203.446829                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        74460     98.95%     98.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          428      0.57%     99.52% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          166      0.22%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          158      0.21%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839           10      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        75250                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        72139                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        70248     97.38%     97.38% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1514      2.10%     99.48% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          196      0.27%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143          111      0.15%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           47      0.07%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        72139                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 421639244068                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.834946                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.371382                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    69614918048     16.51%     16.51% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   352004823020     83.48%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       17379000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        2056500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4          67500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 421639244068                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        61190     98.76%     98.76% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          771      1.24%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        61961                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    88373                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                88373                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1010                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        63733                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        10354                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        78019                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1154.635409                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  8302.318133                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        77325     99.11%     99.11% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          373      0.48%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          149      0.19%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          144      0.18%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839            7      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607            5      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        78019                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        75097                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 22974.939079                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 20231.234781                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18518.097642                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        68416     91.10%     91.10% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         5120      6.82%     97.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          490      0.65%     98.57% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          809      1.08%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           63      0.08%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           55      0.07%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           56      0.07%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143           27      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911           16      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679           17      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        75097                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 413042823976                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.838558                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.368059                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    66699023100     16.15%     16.15% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   346328877376     83.85%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       13315500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        1543000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4          65000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 413042823976                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        63733     98.44%     98.44% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         1010      1.56%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        64743                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85428                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85428                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        88373                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        88373                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61961                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61961                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       147389                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   231535487                       # ITB inst hits
-system.cpu0.itb.inst_misses                     85428                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        64743                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        64743                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       153116                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   231997623                       # ITB inst hits
+system.cpu0.itb.inst_misses                     88373                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   26943                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              44378                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1065                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   26272                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   216195                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   223051                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               231620915                       # ITB inst accesses
-system.cpu0.itb.hits                        231535487                       # DTB hits
-system.cpu0.itb.misses                          85428                       # DTB misses
-system.cpu0.itb.accesses                    231620915                       # DTB accesses
-system.cpu0.numCycles                       805724204                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               232085996                       # ITB inst accesses
+system.cpu0.itb.hits                        231997623                       # DTB hits
+system.cpu0.itb.misses                          88373                       # DTB misses
+system.cpu0.itb.accesses                    232085996                       # DTB accesses
+system.cpu0.numCycles                       807086065                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          95731684                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     652075833                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  147637418                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          87494471                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    667504198                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               15546378                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   1866411                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              305738                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6228904                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       744813                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       860245                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                231319013                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1833472                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  28917                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         781015182                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.979576                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.220669                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          93861008                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     652896475                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  147707110                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          87751171                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    672171434                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               15342460                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1905506                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              292447                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6425780                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       696882                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       817665                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                231773404                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1782410                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  29765                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         783841952                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.977378                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.220143                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               414945915     53.13%     53.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               142136658     18.20%     71.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                48870776      6.26%     77.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               175061833     22.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               417241550     53.23%     53.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               142387565     18.17%     71.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                48916006      6.24%     77.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               175296831     22.36%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           781015182                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.183236                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.809304                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               113248081                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            377378437                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                245811555                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             39067395                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5509714                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            21219272                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2308032                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             677494422                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             25172258                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5509714                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               150635102                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               57564950                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     243777898                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                246916319                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             76611199                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             659282826                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6463914                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             10193503                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                302591                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                345572                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              40114273                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           11761                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          627680154                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1013922393                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       779757811                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           794183                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            565536193                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                62143943                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          16063927                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14023847                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 79290060                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           107984972                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           92881396                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9789553                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8248701                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 636103677                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           16216212                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                639991449                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2906968                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       58559234                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     38038909                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        288402                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    781015182                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.819435                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.071222                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           783841952                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.183013                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.808955                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               111750908                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            381172853                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                246402586                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             39053255                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5462350                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            21288781                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2252861                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             678905918                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             24756446                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5462350                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               148938841                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               55630896                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     250198036                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                247704695                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             75907134                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             660737654                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              6369939                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10029778                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                264844                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                301380                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              39545548                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           11804                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          629064095                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups           1015658028                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       780465434                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           875541                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            567964584                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                61099508                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          16110257                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      14023115                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 79266160                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           107669777                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           93504359                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          9663954                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         8219387                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 637670623                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           16186083                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                641968825                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2865871                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       57572234                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     37073972                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        286236                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    783841952                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.819003                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.071442                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          434056489     55.58%     55.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          142602713     18.26%     73.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          124298977     15.92%     89.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           71442121      9.15%     98.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8609991      1.10%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               4891      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          436124999     55.64%     55.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          142425457     18.17%     73.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          124936152     15.94%     89.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           71756087      9.15%     98.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            8593482      1.10%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               5775      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      781015182                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      783841952                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               67040735     45.54%     45.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 53703      0.04%     45.58% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  26002      0.02%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              14      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              38206404     25.96%     71.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             41875543     28.45%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               67185359     45.52%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 54880      0.04%     45.56% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  27644      0.02%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              23      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              37910313     25.69%     71.26% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             42413379     28.74%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            436779538     68.25%     68.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1517289      0.24%     68.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                81855      0.01%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  5      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt             23      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         47604      0.01%     68.51% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.51% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.51% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.51% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           110932479     17.33%     85.84% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           90632632     14.16%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               10      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            438393066     68.29%     68.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1458143      0.23%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                76119      0.01%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  8      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         85008      0.01%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           110671978     17.24%     85.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           91284446     14.22%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             639991449                       # Type of FU issued
-system.cpu0.iq.rate                          0.794306                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  147202401                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.230007                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2209837146                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        710527601                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    621905864                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1270303                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            504170                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       467307                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             786402566                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 791283                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2962367                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             641968825                       # Type of FU issued
+system.cpu0.iq.rate                          0.795416                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  147591598                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.229905                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2216794106                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        710999195                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    623995458                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1442965                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            583548                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       537913                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             788669354                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 891059                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2946784                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     13371443                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        16751                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       153989                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      6295959                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     13030035                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        16500                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       154978                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      6224286                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2934112                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4671160                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2912970                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4614756                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5509714                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                7058035                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              5778589                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          652441938                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5462350                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                6648440                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              5673367                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          653983600                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            107984972                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            92881396                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13772451                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 68630                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              5639093                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        153989                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2201982                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3098287                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5300269                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            631633854                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            107665614                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7773689                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts            107669777                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            93504359                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13738155                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 65760                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              5541873                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        154978                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2183890                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      3035421                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5219311                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            633716914                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            107489609                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7688831                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       122049                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   196907522                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               119104624                       # Number of branches executed
-system.cpu0.iew.exec_stores                  89241908                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.783933                       # Inst execution rate
-system.cpu0.iew.wb_sent                     623170550                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    622373171                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                301982038                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                495557723                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       126894                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   197402015                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               119462239                       # Number of branches executed
+system.cpu0.iew.exec_stores                  89912406                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.785191                       # Inst execution rate
+system.cpu0.iew.wb_sent                     625355277                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    624533371                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                303033924                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                497197749                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.772439                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609378                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.773813                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609484                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       51133197                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15927810                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4984345                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    771348242                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.769770                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.572751                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       50242588                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15899847                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4905406                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    774311548                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.770083                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.572660                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    513096769     66.52%     66.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    132148168     17.13%     83.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     58179832      7.54%     91.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     19360594      2.51%     93.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     14004722      1.82%     95.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9477117      1.23%     96.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6473381      0.84%     97.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3935015      0.51%     98.10% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14672644      1.90%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    515220918     66.54%     66.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    132191074     17.07%     83.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     58451829      7.55%     91.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     19702970      2.54%     93.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     14118724      1.82%     95.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      9514083      1.23%     96.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6460440      0.83%     97.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3939203      0.51%     98.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     14712307      1.90%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    771348242                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           504955538                       # Number of instructions committed
-system.cpu0.commit.committedOps             593760630                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    774311548                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           507069048                       # Number of instructions committed
+system.cpu0.commit.committedOps             596284470                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     181198957                       # Number of memory references committed
-system.cpu0.commit.loads                     94613526                       # Number of loads committed
-system.cpu0.commit.membars                    4060839                       # Number of memory barriers committed
-system.cpu0.commit.branches                 113014510                       # Number of branches committed
-system.cpu0.commit.fp_insts                    458000                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                545152087                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            14971844                       # Number of function calls committed.
+system.cpu0.commit.refs                     181919815                       # Number of memory references committed
+system.cpu0.commit.loads                     94639742                       # Number of loads committed
+system.cpu0.commit.membars                    4012038                       # Number of memory barriers committed
+system.cpu0.commit.branches                 113466884                       # Number of branches committed
+system.cpu0.commit.fp_insts                    524978                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                547272509                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            14945710                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       411193864     69.25%     69.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1260833      0.21%     69.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           65173      0.01%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       413008446     69.26%     69.26% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1219700      0.20%     69.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           60724      0.01%     69.48% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
@@ -873,818 +878,821 @@ system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% #
 system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.48% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.48% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        41761      0.01%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       94613526     15.93%     85.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      86585431     14.58%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        75743      0.01%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       94639742     15.87%     85.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      87280073     14.64%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        593760630                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14672644                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1397369391                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1299419087                       # The number of ROB writes
-system.cpu0.timesIdled                        1071653                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       24709022                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93813929115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  504955538                       # Number of Instructions Simulated
-system.cpu0.committedOps                    593760630                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.595634                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.595634                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.626710                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.626710                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               746722296                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              443322911                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   778801                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  335108                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                136612374                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               137527114                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1389482326                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16167899                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          6374252                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          504.525126                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          168612051                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6374762                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            26.449937                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        596284470                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             14712307                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1401646047                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1302545204                       # The number of ROB writes
+system.cpu0.timesIdled                        1046717                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       23244113                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93812546108                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  507069048                       # Number of Instructions Simulated
+system.cpu0.committedOps                    596284470                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.591669                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.591669                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.628271                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.628271                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               748239233                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              444460602                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   860614                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  470540                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                137535879                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               138377705                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1393834331                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              16112974                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          6187008                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.050028                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          169602823                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6187519                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.410473                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1887138000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   504.525126                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.985401                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.985401                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.050028                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986426                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986426                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        375986188                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       375986188                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     87724319                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       87724319                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     75477797                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      75477797                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       231729                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       231729                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       266468                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       266468                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2022541                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      2022541                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2052696                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2052696                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    163202116                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       163202116                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    163433845                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      163433845                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7197565                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7197565                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7724152                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7724152                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       724383                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       724383                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       844788                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       844788                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       278463                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       278463                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       208196                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       208196                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     14921717                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      14921717                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     15646100                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     15646100                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 108620779500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 138974834179                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  74732911806                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  74732911806                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4099802000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4099802000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4408839000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4408839000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3050500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3050500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 247595613679                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 247595613679                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     94921884                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     94921884                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     83201949                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     83201949                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       956112                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       956112                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1111256                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1111256                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2301004                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2301004                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2260892                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2260892                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    178123833                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    178123833                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    179079945                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    179079945                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075826                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.075826                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.092836                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.092836                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.757634                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.757634                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760210                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760210                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.121018                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.121018                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092086                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092086                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.083772                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.083772                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087369                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.087369                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        376921548                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       376921548                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     87937173                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       87937173                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     76339825                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      76339825                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       228046                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       228046                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       267132                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       267132                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1986809                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1986809                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2024617                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      2024617                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    164276998                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       164276998                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    164505044                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      164505044                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6895567                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6895567                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7624089                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7624089                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       725854                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       725854                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       804065                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       804065                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       277240                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       277240                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200055                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       200055                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     14519656                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      14519656                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     15245510                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     15245510                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102037717000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 102037717000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 136358862160                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 136358862160                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  72398693034                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  72398693034                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4092900000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4092900000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4230014500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4230014500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5283500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5283500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 238396579160                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 238396579160                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 238396579160                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 238396579160                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     94832740                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     94832740                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     83963914                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     83963914                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       953900                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       953900                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1071197                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1071197                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2264049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2264049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2224672                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2224672                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    178796654                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    178796654                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    179750554                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    179750554                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.072713                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.072713                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.090802                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.090802                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.760933                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760933                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.750623                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.750623                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.122453                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.122453                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.089926                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.089926                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081208                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.081208                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.084815                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.084815                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14797.581838                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14797.581838                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17885.266313                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17885.266313                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90040.846243                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90040.846243                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14763.021209                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14763.021209                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21144.257829                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21144.257829                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     23148520                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     20510394                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           766944                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         746852                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    30.182803                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    27.462461                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16418.886175                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16418.886175                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15637.166560                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15637.166560                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     22487796                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     20190626                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           731543                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         741822                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    30.740224                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    27.217616                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      4317679                       # number of writebacks
-system.cpu0.dcache.writebacks::total          4317679                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3700903                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3700903                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6185217                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6185217                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         5102                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         5102                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       141775                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       141775                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9886120                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9886120                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9886120                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9886120                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3496662                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3496662                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1538935                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1538935                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       717217                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       717217                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       839686                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       839686                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       136688                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136688                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       208181                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       208181                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5035597                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5035597                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5752814                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5752814                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21352                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        23308                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        44660                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50025996500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50025996500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29968345030                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29968345030                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17752964500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17752964500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  73677446306                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  73677446306                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1889285500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1889285500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4200723000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4200723000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2985500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2985500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  79994341530                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  79994341530                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  97747306030                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  97747306030                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3896297500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3896297500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4053651000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4053651000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7949948500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7949948500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036837                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036837                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018496                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018496                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750139                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.750139                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.755619                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.755619                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059404                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059404                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092079                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092079                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028270                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032124                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032124                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      4210788                       # number of writebacks
+system.cpu0.dcache.writebacks::total          4210788                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3513002                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3513002                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6114706                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6114706                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4602                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4602                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       143782                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       143782                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9627708                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9627708                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9627708                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9627708                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3382565                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3382565                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1509383                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1509383                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       718663                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       718663                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       799463                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       799463                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       133458                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       133458                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200041                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       200041                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4891948                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4891948                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5610611                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5610611                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32342                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32342                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31823                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31823                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        64165                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        64165                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48415097500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  48415097500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29340240291                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29340240291                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16426692500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16426692500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  71393732534                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  71393732534                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1844525500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1844525500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4030091500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4030091500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5165500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5165500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  77755337791                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  77755337791                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94182030291                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  94182030291                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5817539000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5817539000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5518707000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5518707000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11336246000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11336246000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035669                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035669                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017977                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017977                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.753394                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.753394                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.746327                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.746327                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058947                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058947                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.089919                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.089919                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027360                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027360                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031213                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031213                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14313.131455                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14313.131455                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19438.565487                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19438.565487                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.295422                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.295422                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89302.109709                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89302.109709                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.018598                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.018598                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20146.327503                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20146.327503                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15894.555255                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15894.555255                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16786.412441                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16786.412441                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179875.672500                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179875.672500                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173418.816579                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173418.816579                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176673.357750                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176673.357750                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6538162                       # number of replacements
+system.cpu0.icache.tags.replacements          6407339                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.955601                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          224372588                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6538674                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.314693                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs          224970066                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6407851                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.108505                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      17322639000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.955601                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999913                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          309                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          330                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           45                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          137                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        469120906                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       469120906                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    224372588                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      224372588                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    224372588                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       224372588                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    224372588                       # number of overall hits
-system.cpu0.icache.overall_hits::total      224372588                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6918516                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6918516                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6918516                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6918516                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6918516                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6918516                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  73530599413                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  73530599413                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  73530599413                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  73530599413                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  73530599413                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  73530599413                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    231291104                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    231291104                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    231291104                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    231291104                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    231291104                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    231291104                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029913                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029913                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029913                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029913                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029913                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029913                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10628.088366                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10628.088366                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     10842770                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          750                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           802318                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.514305                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets           75                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        469899085                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       469899085                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    224970066                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      224970066                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    224970066                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       224970066                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    224970066                       # number of overall hits
+system.cpu0.icache.overall_hits::total      224970066                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6775541                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6775541                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6775541                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6775541                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6775541                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6775541                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  71079582898                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  71079582898                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  71079582898                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  71079582898                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  71079582898                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  71079582898                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    231745607                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    231745607                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    231745607                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    231745607                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    231745607                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    231745607                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029237                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029237                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029237                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029237                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029237                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029237                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10490.613650                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10490.613650                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10490.613650                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10490.613650                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10490.613650                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10490.613650                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10215206                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          732                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           767906                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              9                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.302678                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets    81.333333                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       379817                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       379817                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       379817                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       379817                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       379817                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       379817                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6538699                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6538699                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6538699                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6538699                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6538699                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6538699                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       367670                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       367670                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       367670                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       367670                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       367670                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       367670                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6407871                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6407871                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6407871                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6407871                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6407871                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6407871                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  66562536735                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  66562536735                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  66562536735                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  66562536735                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  66562536735                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  66562536735                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64388034562                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  64388034562                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64388034562                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  64388034562                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64388034562                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  64388034562                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1863746498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1863746498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1863746498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028270                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028270                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028270                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028270                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027650                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027650                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027650                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027650                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027650                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027650                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10048.272595                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10048.272595                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10048.272595                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10048.272595                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10048.272595                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10048.272595                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8420678                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8427841                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         6477                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8228747                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8235731                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         6331                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1085415                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2879166                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16210.435264                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          21867253                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2894850                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.553847                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage      1065389                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2775717                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16223.891094                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          21402394                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2791423                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            7.667198                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle     16000650500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7399.715112                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    85.098490                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    94.687899                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4348.179928                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3389.288950                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   893.464886                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.451643                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005194                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005779                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.265392                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.206866                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054533                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.989406                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1404                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14188                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          100                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          251                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          434                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           68                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          213                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          757                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4744                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4803                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3671                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.085693                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.865967                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       440722520                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      440722520                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       580486                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       180915                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        761401                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      4317669                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      4317669                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       115526                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       115526                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36643                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        36643                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       998559                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       998559                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5850201                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5850201                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3218899                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3218899                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       227084                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       227084                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       580486                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       180915                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5850201                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4217458                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       10829060                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       580486                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       180915                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5850201                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4217458                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      10829060                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13187                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9856                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        23043                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            5                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            5                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       140809                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       140809                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       171530                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       171530                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       296756                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       296756                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       688482                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       688482                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1127441                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1127441                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       611195                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       611195                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13187                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9856                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       688482                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1424197                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2135722                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13187                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9856                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       688482                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1424197                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2135722                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    534558500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    449764500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    984323000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3072018500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   3072018500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3550746499                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3550746499                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2885498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2885498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16106273500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  16106273500                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  21873259998                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  21873259998                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41772472980                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41772472980                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  70023878999                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  70023878999                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    534558500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    449764500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  21873259998                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  57878746480                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  80736329478                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    534558500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    449764500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  21873259998                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  57878746480                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  80736329478                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       593673                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       190771                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       784444                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      4317674                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      4317674                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       256335                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       256335                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       208173                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       208173                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1295315                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1295315                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6538683                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      6538683                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4346340                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4346340                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       838279                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       838279                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       593673                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       190771                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      6538683                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5641655                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     12964782                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       593673                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       190771                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      6538683                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5641655                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     12964782                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.029375                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.549316                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.549316                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.823978                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.823978                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7115.603862                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    78.900810                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    84.351377                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4177.499611                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3867.898858                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   899.636576                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.434302                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004816                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005148                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.254974                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.236078                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054909                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.990228                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1370                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023          105                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14231                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           95                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          230                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          633                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          412                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           79                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          219                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          777                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4691                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4874                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3670                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.083618                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006409                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.868591                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       429969971                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      429969971                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       556706                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       187543                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        744249                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      4210780                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      4210780                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       112692                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total       112692                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36481                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        36481                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       982818                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       982818                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5746953                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5746953                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3150457                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      3150457                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       210597                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       210597                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       556706                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       187543                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5746953                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      4133275                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       10624477                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       556706                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       187543                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5746953                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      4133275                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      10624477                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12834                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9490                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        22324                       # number of ReadReq misses
+system.cpu0.l2cache.Writeback_misses::writebacks            2                       # number of Writeback misses
+system.cpu0.l2cache.Writeback_misses::total            2                       # number of Writeback misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       137568                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       137568                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       163550                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       163550                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           10                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       289201                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       289201                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       660894                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       660894                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1080002                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1080002                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       587441                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       587441                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12834                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9490                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       660894                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1369203                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2052421                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12834                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9490                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       660894                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1369203                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2052421                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    512484500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    411800500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    924285000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2995269498                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2995269498                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3391228500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3391228500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4985998                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4985998                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15723716499                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  15723716499                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  20507752998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  20507752998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  39428872479                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  39428872479                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  67940497999                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  67940497999                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    512484500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    411800500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20507752998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  55152588978                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  76584626976                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    512484500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    411800500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20507752998                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  55152588978                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  76584626976                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       569540                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       197033                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       766573                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks      4210782                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      4210782                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       250260                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       250260                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       200031                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       200031                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1272019                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1272019                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6407847                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      6407847                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4230459                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      4230459                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       798038                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       798038                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       569540                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       197033                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      6407847                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5502478                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     12676898                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       569540                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       197033                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      6407847                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5502478                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     12676898                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022534                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.048165                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.029122                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.549700                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.549700                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.817623                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.817623                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.229099                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.229099                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.105294                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.105294                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.259400                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.259400                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.729107                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.729107                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.105294                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252443                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.164733                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022213                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.051664                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.105294                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252443                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.164733                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42716.790348                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21816.918663                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21816.918663                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20700.440150                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20700.440150                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 360687.250000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 360687.250000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54274.466228                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54274.466228                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31770.271406                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31770.271406                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37050.695318                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37050.695318                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114568.802099                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114568.802099                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31770.271406                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40639.564948                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37802.827090                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40536.778646                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45633.573458                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31770.271406                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40639.564948                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37802.827090                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         1651                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.227356                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.227356                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.103138                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.103138                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.255292                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.255292                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.736107                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.736107                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022534                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.048165                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.103138                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.248834                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.161902                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022534                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.048165                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.103138                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.248834                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.161902                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 39931.782765                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 43393.097998                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41403.198352                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21773.010424                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21773.010424                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20735.117701                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20735.117701                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 498599.800000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498599.800000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54369.509438                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54369.509438                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31030.321047                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31030.321047                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36508.147651                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36508.147651                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 115655.015566                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 115655.015566                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 39931.782765                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 43393.097998                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31030.321047                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40280.797645                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 37314.287359                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 39931.782765                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 43393.097998                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31030.321047                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40280.797645                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 37314.287359                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         1981                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs              13                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   275.166667                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   152.384615                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1533538                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1533538                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          198                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          201                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18639                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        18639                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.writebacks::writebacks      1508833                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1508833                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            7                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          199                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          206                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18287                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        18287                       # number of ReadExReq MSHR hits
 system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            9                       # number of ReadCleanReq MSHR hits
 system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         6125                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         6125                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          198                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5427                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5427                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            6                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          199                       # number of demand (read+write) MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        24764                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        24974                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          198                       # number of overall MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        23714                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        23929                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            7                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          199                       # number of overall MSHR hits
 system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            9                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        24764                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        24974                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13184                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9658                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        22842                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            5                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            5                       # number of Writeback MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       117912                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total       117912                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       787872                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       787872                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       140809                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       140809                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       171530                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       171530                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278117                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       278117                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       688473                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       688473                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1121316                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1121316                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       611195                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       611195                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13184                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9658                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       688473                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1399433                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2110748                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13184                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9658                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       688473                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1399433                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       787872                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2898620                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        23714                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        23929                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12827                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9291                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        22118                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.Writeback_mshr_misses::writebacks            2                       # number of Writeback MSHR misses
+system.cpu0.l2cache.Writeback_mshr_misses::total            2                       # number of Writeback MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       112445                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.CleanEvict_mshr_misses::total       112445                       # number of CleanEvict MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       792314                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       792314                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       137568                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       137568                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       163550                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       163550                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       270914                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       270914                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       660885                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       660885                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1074575                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1074575                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       587435                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       587435                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12827                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9291                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       660885                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1345489                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      2028492                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12827                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9291                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       660885                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1345489                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       792314                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2820806                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        42646                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        23308                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32342                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        53636                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        31823                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        31823                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        65954                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    838560500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47401942947                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  47401942947                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2887874997                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2887874997                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2620767495                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2620767495                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2495498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2495498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11968940000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11968940000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17742237498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17742237498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34600470980                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34600470980                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  66356708999                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  66356708999                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17742237498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  46569410980                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  65150208978                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    455402500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    383158000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17742237498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  46569410980                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47401942947                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 112552151925                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        64165                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        85459                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    435391500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    348114500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    783506000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  46187185788                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  46187185788                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2827746492                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2827746492                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2511676494                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2511676494                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4277998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4277998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11675388499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11675388499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  16542258498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  16542258498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  32603545979                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  32603545979                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  64414833499                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  64414833499                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    435391500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    348114500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  16542258498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  44278934478                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  61604698976                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    435391500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    348114500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  16542258498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  44278934478                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  46187185788                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 107791884764                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3725362000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5429402500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3873404967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3873404967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5558674000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7262714500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5274604967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5274604967                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1704040500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7598766967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9302807467                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029119                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10833278967                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12537319467                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022522                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.047155                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028853                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.549316                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.549316                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823978                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823978                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.549700                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.549700                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.817623                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.817623                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.214710                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.214710                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.105292                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.257991                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257991                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.729107                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.729107                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248054                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.162806                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022208                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.050626                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.105292                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248054                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.212980                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.212980                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.103137                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.103137                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.254009                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254009                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.736099                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.736099                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022522                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.047155                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.103137                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.244524                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.160015                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022522                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.047155                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.103137                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.244524                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.223576                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 36711.343140                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60164.522850                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.222515                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35423.908129                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58294.042246                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20555.263521                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20555.263521                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15357.239340                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15357.239340                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 427799.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 427799.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43096.290701                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43096.290701                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25030.464450                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25030.464450                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30340.875210                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30340.875210                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 109654.401762                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 109654.401762                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25030.464450                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32909.176127                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30369.702703                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25030.464450                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32909.176127                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38213.150697                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171871.683879                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 135407.459542                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165748.199950                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165748.199950                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168834.706881                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 146705.665489                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq        984567                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     11961948                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq        972246                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11719640                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        38204                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        23308                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      8463420                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict     11561533                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1016095                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       502894                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       380729                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       540434                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1691199                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1306018                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6538699                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6804200                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       945007                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       838279                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19656927                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20547872                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       414026                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1295337                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         41914162                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    418816352                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    645201790                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1526168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4749384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1070293694                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                   11878703                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     38928585                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       1.320254                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.466574                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::WriteReq        38676                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        31823                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      8100286                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict     11177309                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1018919                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       495790                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       366670                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       532232                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq          139                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          247                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1670081                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1283370                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6407871                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      6502663                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       904766                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       798038                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19264194                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20025393                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       428101                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1250579                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         40968267                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    410442912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    629983858                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1576264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4556320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1046559354                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                   11261603                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     37657626                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       1.313855                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.464058                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1          26461563     67.97%     67.97% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2          12467022     32.03%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1          25838573     68.61%     68.61% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2          11819053     31.39%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      38928585                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   18022605428                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      37657626                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   17602075916                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    218178978                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    231593980                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9834328997                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9637654372                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9151913574                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8931019988                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    223594319                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    231432265                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    702320680                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    681669728                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              127974219                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         85721226                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6122377                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            91131353                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               60172902                       # Number of BTB hits
+system.cpu1.branchPred.lookups              121094303                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         80706133                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6142160                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            84960891                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               56341743                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            66.028760                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17085083                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            181731                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            66.314915                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16429988                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            173246                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1714,89 +1722,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   610901                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               610901                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        15580                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3       103695                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       293448                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       317453                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2113.928676                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-32767       312797     98.53%     98.53% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-65535         2424      0.76%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-98303          700      0.22%     99.52% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-131071          857      0.27%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-163839          351      0.11%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::163840-196607          153      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-229375           53      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::229376-262143           19      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-294911           21      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::294912-327679           57      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-360447           14      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   582230                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               582230                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        14388                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94420                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       278308                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       303922                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  1994.445943                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 12173.491739                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-32767       299685     98.61%     98.61% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-65535         2211      0.73%     99.33% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-98303          696      0.23%     99.56% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-131071          740      0.24%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-163839          294      0.10%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::163840-196607          141      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-229375           47      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::229376-262143           22      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-294911           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::294912-327679           44      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-360447           15      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::360448-393215            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       317453                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       338102                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       335377     99.19%     99.19% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1909      0.56%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          302      0.09%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          312      0.09%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          121      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           38      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::491520-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       303922                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       314895                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 18136.229537                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 15585.359240                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14753.917468                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       312363     99.20%     99.20% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1838      0.58%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          299      0.09%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          215      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           97      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           46      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           18      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       338102                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 438848021252                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.580073                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.553130                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 437543459752     99.70%     99.70% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    782991500      0.18%     99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    243923500      0.06%     99.94% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    110155500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     88476500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     41634500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     16681500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     20049000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       649500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 438848021252                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K       103695     86.94%     86.94% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        15580     13.06%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       119275                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       610901                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       314895                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 417361955272                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.556480                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.556703                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 416192825272     99.72%     99.72% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    674141500      0.16%     99.88% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    223425500      0.05%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    105228000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     86739500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     43806500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     16133000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     19234500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       421500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 417361955272                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        94420     86.78%     86.78% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        14388     13.22%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       108808                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       582230                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       610901                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       119275                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       582230                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       108808                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       119275                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       730176                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       108808                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       691038                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    94901630                       # DTB read hits
-system.cpu1.dtb.read_misses                    438242                       # DTB read misses
-system.cpu1.dtb.write_hits                   77470080                       # DTB write hits
-system.cpu1.dtb.write_misses                   172659                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    89807249                       # DTB read hits
+system.cpu1.dtb.read_misses                    419450                       # DTB read misses
+system.cpu1.dtb.write_hits                   72180592                       # DTB write hits
+system.cpu1.dtb.write_misses                   162780                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   42323                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      163                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  7630                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              44378                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1065                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   41875                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      370                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6410                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    42941                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                95339872                       # DTB read accesses
-system.cpu1.dtb.write_accesses               77642739                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    41502                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                90226699                       # DTB read accesses
+system.cpu1.dtb.write_accesses               72343372                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        172371710                       # DTB hits
-system.cpu1.dtb.misses                         610901                       # DTB misses
-system.cpu1.dtb.accesses                    172982611                       # DTB accesses
+system.cpu1.dtb.hits                        161987841                       # DTB hits
+system.cpu1.dtb.misses                         582230                       # DTB misses
+system.cpu1.dtb.accesses                    162570071                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1826,1161 +1835,1148 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    86285                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                86285                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1166                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        62692                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore         9855                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        76430                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1337.426403                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        75617     98.94%     98.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          383      0.50%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303          204      0.27%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          174      0.23%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839            8      0.01%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        76430                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        73713                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        72001     97.68%     97.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1393      1.89%     99.57% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          144      0.20%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143          112      0.15%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           36      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    81350                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                81350                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          844                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        59039                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore         9413                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        71937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1124.310160                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  8422.739912                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535        71675     99.64%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071          232      0.32%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607           13      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        71937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        69296                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 22634.596514                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19851.891028                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18070.710028                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        67837     97.89%     97.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1226      1.77%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          116      0.17%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           77      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           19      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        73713                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 417370190772                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.853526                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.353735                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    61155433348     14.65%     14.65% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   356194673424     85.34%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       18786000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        1262500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          35500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 417370190772                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        62692     98.17%     98.17% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         1166      1.83%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        63858                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        69296                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 391589144496                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.846934                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.360225                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    59961618480     15.31%     15.31% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   331606536516     84.68%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       19274500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        1690500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          24500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 391589144496                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        59039     98.59%     98.59% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          844      1.41%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        59883                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        86285                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        86285                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        81350                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        81350                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63858                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63858                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       150143                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   203133106                       # ITB inst hits
-system.cpu1.itb.inst_misses                     86285                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        59883                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        59883                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       141233                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   191639831                       # ITB inst hits
+system.cpu1.itb.inst_misses                     81350                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              46383                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1087                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   30560                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              44378                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1065                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   29949                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   224551                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   209776                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               203219391                       # ITB inst accesses
-system.cpu1.itb.hits                        203133106                       # DTB hits
-system.cpu1.itb.misses                          86285                       # DTB misses
-system.cpu1.itb.accesses                    203219391                       # DTB accesses
-system.cpu1.numCycles                       708901373                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               191721181                       # ITB inst accesses
+system.cpu1.itb.hits                        191639831                       # DTB hits
+system.cpu1.itb.misses                          81350                       # DTB misses
+system.cpu1.itb.accesses                    191721181                       # DTB accesses
+system.cpu1.numCycles                       657106376                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          79210227                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     569056404                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  127974219                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          77257985                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    596249525                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13297978                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1936888                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              233747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6483042                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       760521                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       721953                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                202886748                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1527721                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  28660                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         692244892                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.964370                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.215604                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          80139865                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     537547218                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  121094303                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          72771731                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    544595085                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13230640                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1750818                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              245014                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      5964311                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       783127                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       735374                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                191409476                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1578665                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  27162                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         640828914                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.984123                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.220773                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               371999522     53.74%     53.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               125145403     18.08%     71.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                42864856      6.19%     78.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               152235111     21.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               338710091     52.85%     52.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               117550572     18.34%     71.20% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                40600676      6.34%     77.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               143967575     22.47%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           692244892                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.180525                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.802730                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                98103528                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            343550458                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                207545620                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             38285921                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4759365                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            18045337                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1925812                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             590182189                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             20993149                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4759365                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               132299037                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               44198902                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     235238981                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                211136719                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             64611888                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             574391592                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5359861                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              9789729                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                401271                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                868513                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              28581746                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           10968                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          549201958                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            896745625                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       678703153                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           702078                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            496570478                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                52631474                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          16637084                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      14688391                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 76542594                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            94434816                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           80595349                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8923483                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7689116                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 551758554                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           16802636                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                558923093                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2479703                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       49836281                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     32327580                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        272404                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    692244892                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.807407                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.056587                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           640828914                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.184284                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.818052                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                96524622                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            306596217                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                198367702                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             34666699                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               4673674                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            17189225                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1979171                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             555902892                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             21032284                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               4673674                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               128741707                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               40944507                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     207984500                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                200380023                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             58104503                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             540647070                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5273833                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              8920508                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                357666                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                869250                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              25304278                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           12220                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          515542885                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            838360476                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       639083471                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           635892                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            463444914                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                52097965                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14931648                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13102843                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 69578208                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            89907304                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           75221964                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          8553187                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         7364919                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 519731744                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15160501                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                524719232                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2440222                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       49181333                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     32199370                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        264903                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    640828914                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.818813                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.060738                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          382813800     55.30%     55.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          135617529     19.59%     74.89% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          105540069     15.25%     90.14% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           60873310      8.79%     98.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7395424      1.07%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               4760      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          351184657     54.80%     54.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          125580577     19.60%     74.40% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           99945390     15.60%     89.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           57229371      8.93%     98.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            6884833      1.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               4086      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      692244892                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      640828914                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               54751854     43.35%     43.35% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 59874      0.05%     43.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   7206      0.01%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              22      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              34635726     27.43%     70.83% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             36835867     29.17%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               51884545     43.66%     43.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 60325      0.05%     43.71% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   6398      0.01%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              22      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              32949736     27.73%     71.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             33928397     28.55%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               22      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            381080184     68.18%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1279374      0.23%     68.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                67457      0.01%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         77518      0.01%     68.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            97747450     17.49%     85.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           78671088     14.08%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            357316080     68.10%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1302107      0.25%     68.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                73183      0.01%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         41368      0.01%     68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            92637950     17.65%     86.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           73348522     13.98%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             558923093                       # Type of FU issued
-system.cpu1.iq.rate                          0.788436                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  126290549                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.225953                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1937670345                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        618057050                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    542680096                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1190983                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            486822                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       443064                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             684478646                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 734974                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2497447                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             524719232                       # Type of FU issued
+system.cpu1.iq.rate                          0.798530                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  118829423                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.226463                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1810487568                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        583794764                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    509259381                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1049453                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            417103                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       385439                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             642894662                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 653971                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2364683                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11391566                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        16442                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       147287                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5480411                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     11367007                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        15961                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       139264                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5290675                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2518337                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      4561530                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2384785                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4103064                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4759365                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                7377288                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1779487                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          568686865                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               4673674                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                6987028                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1738087                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          535009487                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             94434816                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            80595349                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          14436432                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 67561                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1633321                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        147287                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1861843                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2641662                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4503505                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            551808656                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             94901612                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6513481                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             89907304                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            75221964                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12892176                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 53410                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1616074                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        139264                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1829419                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2640296                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4469715                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            517720791                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             89804186                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          6423141                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       125675                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   172371354                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               103407043                       # Number of branches executed
-system.cpu1.iew.exec_stores                  77469742                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.778400                       # Inst execution rate
-system.cpu1.iew.wb_sent                     543849746                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    543123160                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                263131919                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                431737287                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       117242                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   161982461                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                97046647                       # Number of branches executed
+system.cpu1.iew.exec_stores                  72178275                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.787880                       # Inst execution rate
+system.cpu1.iew.wb_sent                     510319956                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    509644820                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                247330259                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                405058762                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.766148                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.609472                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.775590                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610603                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       43653536                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       16530232                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4232753                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    683948716                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.758427                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.554925                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       43050408                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14895598                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4200514                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    632658676                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.767730                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.562752                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    453202569     66.26%     66.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    123078137     18.00%     84.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     49564580      7.25%     91.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     16593049      2.43%     93.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11718092      1.71%     95.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8048900      1.18%     96.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5489767      0.80%     97.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3345988      0.49%     98.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12907634      1.89%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    417403815     65.98%     65.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    113799591     17.99%     83.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     46934435      7.42%     91.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15547292      2.46%     93.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10981139      1.74%     95.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      7643765      1.21%     96.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5190686      0.82%     97.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3150553      0.50%     98.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     12007400      1.90%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    683948716                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           441056280                       # Number of instructions committed
-system.cpu1.commit.committedOps             518724902                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    632658676                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           412964348                       # Number of instructions committed
+system.cpu1.commit.committedOps             485710905                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     158158187                       # Number of memory references committed
-system.cpu1.commit.loads                     83043249                       # Number of loads committed
-system.cpu1.commit.membars                    3695786                       # Number of memory barriers committed
-system.cpu1.commit.branches                  98284315                       # Number of branches committed
-system.cpu1.commit.fp_insts                    431344                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                475340146                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12767541                       # Number of function calls committed.
+system.cpu1.commit.refs                     148471585                       # Number of memory references committed
+system.cpu1.commit.loads                     78540296                       # Number of loads committed
+system.cpu1.commit.membars                    3510647                       # Number of memory barriers committed
+system.cpu1.commit.branches                  92021861                       # Number of branches committed
+system.cpu1.commit.fp_insts                    377145                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                445805015                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            12220081                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       359393863     69.28%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1051243      0.20%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           53001      0.01%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        68608      0.01%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       83043249     16.01%     85.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      75114938     14.48%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       336089825     69.20%     69.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1056611      0.22%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           57564      0.01%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        35320      0.01%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       78540296     16.17%     85.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      69931289     14.40%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        518724902                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12907634                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1229236643                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1133012460                       # The number of ROB writes
-system.cpu1.timesIdled                         937113                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       16656481                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 93910751930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  441056280                       # Number of Instructions Simulated
-system.cpu1.committedOps                    518724902                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.607281                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.607281                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.622169                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.622169                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               651831389                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              384949596                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   687947                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  437000                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                121245693                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               121813302                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1231894475                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              16565900                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5500590                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          430.004525                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          146156295                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5501102                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            26.568548                       # Average number of references to valid blocks.
+system.cpu1.commit.op_class_0::total        485710905                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             12007400                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1145678392                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1065656273                       # The number of ROB writes
+system.cpu1.timesIdled                         931363                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       16277462                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 93962526294                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  412964348                       # Number of Instructions Simulated
+system.cpu1.committedOps                    485710905                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.591194                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.591194                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.628459                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.628459                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               611833579                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              362533704                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   622107                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  321740                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                111613116                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               112230966                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1145938750                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14868837                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5274603                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          426.947513                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          137535053                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5275114                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            26.072432                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8485200468500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.004525                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.839853                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.839853                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          388                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        327866519                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       327866519                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     76697860                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       76697860                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     64975008                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      64975008                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       170492                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       170492                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        54492                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        54492                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1753772                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1753772                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1761808                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1761808                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    141672868                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       141672868                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    141843360                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      141843360                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6400758                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6400758                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      7699637                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      7699637                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       744836                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       744836                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       409878                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       409878                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       258549                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       258549                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       208576                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       208576                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     14100395                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      14100395                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     14845231                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     14845231                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  92687894000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  92687894000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 138325220262                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20294196326                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  20294196326                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4013433500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   4013433500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4392601500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4392601500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3408500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3408500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 231013114262                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 231013114262                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 231013114262                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 231013114262                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     83098618                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     83098618                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     72674645                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     72674645                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       915328                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       915328                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       464370                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       464370                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2012321                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2012321                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1970384                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1970384                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    155773263                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    155773263                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    156688591                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    156688591                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.077026                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.077026                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.105947                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.105947                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.813737                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.813737                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.882654                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.882654                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.128483                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.128483                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105856                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105856                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.090519                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.090519                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.094744                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.094744                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   426.947513                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.833882                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.833882                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        308540922                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       308540922                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     72744707                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       72744707                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     60628902                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      60628902                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       161948                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       161948                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        50338                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        50338                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1624470                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1624470                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1636906                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1636906                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    133373609                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       133373609                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    133535557                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      133535557                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6201374                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6201374                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      6969409                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      6969409                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       662990                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       662990                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       447840                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       447840                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       255439                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       255439                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       200646                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       200646                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     13170783                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      13170783                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     13833773                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     13833773                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  88228717500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  88228717500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 123237994379                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 123237994379                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20350455489                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  20350455489                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3706894000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   3706894000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4288443500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4288443500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      6003000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      6003000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 211466711879                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 211466711879                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 211466711879                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 211466711879                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     78946081                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     78946081                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     67598311                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     67598311                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       824938                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       824938                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       498178                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       498178                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1879909                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1879909                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1837552                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1837552                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    146544392                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    146544392                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    147369330                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    147369330                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.078552                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.078552                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.103100                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.103100                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.803685                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.803685                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.898956                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.898956                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.135878                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.135878                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.109192                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.109192                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.089876                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.089876                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.093871                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.093871                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14227.285356                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14227.285356                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17682.703710                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17682.703710                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45441.352914                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45441.352914                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14511.856060                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14511.856060                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21373.182122                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21373.182122                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      5682783                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     23004045                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           345925                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         792691                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    16.427789                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    29.020192                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16055.743374                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16055.743374                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15286.264411                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15286.264411                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      5662057                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     20000375                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           377912                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         710012                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.982475                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    28.169066                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3566261                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3566261                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3293272                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3293272                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6267237                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      6267237                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         2938                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         2938                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       130878                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       130878                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      9560509                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      9560509                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      9560509                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      9560509                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3107486                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3107486                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1432400                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1432400                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       744751                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       744751                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       406940                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       406940                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       127671                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       127671                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       208566                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       208566                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4539886                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4539886                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5284637                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5284637                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        16935                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        16935                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14896                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31831                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31831                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  43040497000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  43040497000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26400232128                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26400232128                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15655161500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15655161500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19798456326                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19798456326                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1838541000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1838541000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4184106500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4184106500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3337500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3337500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69440729128                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  69440729128                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  85095890628                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  85095890628                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2604403500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2604403500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2300537000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2300537000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4904940500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4904940500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037395                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037395                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019710                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019710                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.813644                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.813644                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.876327                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.876327                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063445                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063445                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105850                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105850                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029144                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.029144                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033727                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033727                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3411546                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3411546                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3176462                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3176462                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5650771                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5650771                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3283                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3283                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       129585                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       129585                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      8827233                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      8827233                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      8827233                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      8827233                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3024912                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3024912                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1318638                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1318638                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       662904                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       662904                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       444557                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       444557                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       125854                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       125854                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       200639                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       200639                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4343550                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4343550                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5006454                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5006454                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         6436                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         6436                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         6853                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         6853                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        13289                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        13289                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40779010000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40779010000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  24146673124                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  24146673124                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13797097500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13797097500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19809664989                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19809664989                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1736527500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1736527500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4087933500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4087933500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5874000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5874000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  64925683124                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  64925683124                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  78722780624                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  78722780624                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    710484000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    710484000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    859770500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    859770500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1570254500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1570254500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.038316                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.038316                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019507                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019507                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.803580                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.803580                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.892366                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.892366                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066947                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066947                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.109188                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.109188                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029640                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.029640                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033972                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033972                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.056639                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.056639                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18311.828663                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18311.828663                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20813.115474                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20813.115474                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44560.461288                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44560.461288                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13797.952389                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13797.952389                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20374.570746                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20374.570746                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14947.608091                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14947.608091                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15724.259251                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15724.259251                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110392.169049                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110392.169049                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125458.996060                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125458.996060                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118161.976070                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 118161.976070                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5403947                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.811782                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          197154720                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5404459                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            36.480010                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements          5512111                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.811781                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          185560716                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5512623                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            33.661057                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     8495886874000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.811782                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.811781                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980101                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.980101                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        411165528                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       411165528                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    197154720                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      197154720                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    197154720                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       197154720                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    197154720                       # number of overall hits
-system.cpu1.icache.overall_hits::total      197154720                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5725810                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5725810                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5725810                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5725810                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5725810                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5725810                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  59819230732                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  59819230732                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  59819230732                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  59819230732                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  59819230732                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  59819230732                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    202880530                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    202880530                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    202880530                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    202880530                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    202880530                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    202880530                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028223                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.028223                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028223                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.028223                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028223                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.028223                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10447.295794                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10447.295794                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      8523796                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          288                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           664103                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              3                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.835051                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        388319278                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       388319278                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    185560716                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      185560716                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    185560716                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       185560716                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    185560716                       # number of overall hits
+system.cpu1.icache.overall_hits::total      185560716                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5842603                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5842603                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5842603                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5842603                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5842603                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5842603                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  60453928731                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  60453928731                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  60453928731                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  60453928731                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  60453928731                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  60453928731                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    191403319                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    191403319                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    191403319                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    191403319                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    191403319                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    191403319                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030525                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.030525                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030525                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.030525                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030525                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.030525                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10347.088230                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10347.088230                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10347.088230                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10347.088230                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10347.088230                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10347.088230                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      8745745                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets           74                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           694595                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.591143                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets           74                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       321342                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       321342                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       321342                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       321342                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       321342                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       321342                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5404468                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5404468                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5404468                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5404468                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5404468                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5404468                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       329963                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       329963                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       329963                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       329963                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       329963                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       329963                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5512640                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5512640                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5512640                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5512640                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5512640                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5512640                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  54260492010                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  54260492010                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  54260492010                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  54260492010                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  54260492010                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  54260492010                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  54827935019                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  54827935019                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  54827935019                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  54827935019                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  54827935019                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  54827935019                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5791998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5791998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5791998                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      5791998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.026639                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.026639                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.026639                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.026639                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028801                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028801                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028801                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.028801                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028801                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.028801                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9945.858068                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9945.858068                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9945.858068                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9945.858068                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9945.858068                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9945.858068                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7840068                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7844426                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         3981                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7331800                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7336274                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         4099                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       944222                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2377748                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13486.772220                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          18876475                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2393818                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.885510                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10140216096000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5055.984886                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    70.053821                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    84.713714                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3027.541847                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  4406.199695                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   842.278257                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.308593                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004276                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005171                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.184786                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.268933                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051409                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.823167                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1281                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           69                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14720                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           30                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          223                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          628                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          392                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           34                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1431                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5385                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4653                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3120                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078186                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.898438                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       375099508                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      375099508                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       592978                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       185889                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        778867                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3566243                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3566243                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        83253                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        83253                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35939                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        35939                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       957303                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       957303                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4781175                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4781175                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2910784                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2910784                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       147109                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       147109                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       592978                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       185889                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4781175                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3868087                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        9428129                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       592978                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       185889                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4781175                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3868087                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       9428129                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12789                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9475                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        22264                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks           18                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total           18                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       144289                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       144289                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       172622                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       172622                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       255780                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       255780                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       623287                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       623287                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1065341                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1065341                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       258817                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       258817                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12789                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9475                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       623287                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1321121                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1966672                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12789                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9475                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       623287                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1321121                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1966672                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    512874500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    430496500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    943371000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3103492000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3103492000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3553775999                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3553775999                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3230499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3230499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  13173602496                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  13173602496                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  17677681000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  17677681000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  35240864484                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  35240864484                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  17868215998                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  17868215998                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    512874500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    430496500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17677681000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  48414466980                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  67035518980                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    512874500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    430496500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17677681000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  48414466980                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  67035518980                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       605767                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       195364                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       801131                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3566261                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3566261                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       227542                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       227542                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       208561                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       208561                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1213083                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1213083                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5404462                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5404462                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3976125                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3976125                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       405926                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       405926                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       605767                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       195364                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5404462                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      5189208                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     11394801                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       605767                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       195364                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5404462                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      5189208                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     11394801                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.027791                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000005                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000005                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.634120                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.634120                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.827681                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.827681                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       897950                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2207622                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13131.101294                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          18758807                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2223617                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            8.436168                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9687561014000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5032.423158                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    78.618743                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    86.333738                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3261.641393                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3759.864250                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   912.220012                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.307155                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004799                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005269                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.199075                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.229484                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.055677                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.801459                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1285                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           80                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14630                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           33                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          250                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          623                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          379                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           53                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1375                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5281                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4801                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3028                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078430                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004883                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.892944                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       369655582                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      369655582                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       548671                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       168948                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        717619                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3411534                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3411534                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        70189                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total        70189                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        33871                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        33871                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       868044                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       868044                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4905635                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4905635                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2835466                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2835466                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       174715                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       174715                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       548671                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       168948                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4905635                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3703510                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        9326764                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       548671                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       168948                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4905635                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3703510                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       9326764                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11848                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8514                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        20362                       # number of ReadReq misses
+system.cpu1.l2cache.Writeback_misses::writebacks           12                       # number of Writeback misses
+system.cpu1.l2cache.Writeback_misses::total           12                       # number of Writeback misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       139128                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       139128                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       166752                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       166752                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           16                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total           16                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       247689                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       247689                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       607002                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       607002                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       976114                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       976114                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       268832                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       268832                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11848                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8514                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       607002                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1223803                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1851167                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11848                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8514                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       607002                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1223803                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1851167                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    446786000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    357242500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    804028500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2996930500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2996930500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3475655499                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3475655499                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5675991                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5675991                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11909522998                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  11909522998                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  17320734000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  17320734000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31800458472                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31800458472                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  17606608999                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  17606608999                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    446786000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    357242500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17320734000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  43709981470                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  61834743970                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    446786000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    357242500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17320734000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  43709981470                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  61834743970                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       560519                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       177462                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       737981                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3411546                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3411546                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       209317                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       209317                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       200623                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       200623                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           16                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           16                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1115733                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1115733                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5512637                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      5512637                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3811580                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3811580                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       443547                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       443547                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       560519                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       177462                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5512637                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4927313                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     11177931                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       560519                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       177462                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5512637                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4927313                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     11177931                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021138                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.047976                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.027591                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000004                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000004                       # miss rate for Writeback accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.664676                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.664676                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.831171                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.831171                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210851                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210851                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.115328                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.115328                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.267934                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.267934                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.637597                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.637597                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.115328                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.254590                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.172594                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021112                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048499                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.115328                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.254590                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.172594                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 42372.035573                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21508.860689                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21508.860689                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20587.039885                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20587.039885                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 646099.800000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 646099.800000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51503.645696                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51503.645696                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28362.024236                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28362.024236                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33079.421973                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33079.421973                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69038.030724                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69038.030724                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28362.024236                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36646.504733                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 34085.764673                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 40102.783642                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45434.986807                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28362.024236                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36646.504733                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 34085.764673                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs         3889                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.221997                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.221997                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.110111                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.110111                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.256092                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.256092                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.606096                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.606096                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021138                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.047976                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110111                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.248371                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.165609                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021138                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.047976                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110111                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.248371                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.165609                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37709.824443                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41959.419779                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39486.715450                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21540.814933                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21540.814933                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20843.261244                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20843.261244                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354749.437500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354749.437500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48082.567244                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48082.567244                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28534.887859                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28534.887859                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32578.631668                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32578.631668                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 65492.980743                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 65492.980743                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37709.824443                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41959.419779                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28534.887859                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35716.517667                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 33403.114884                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37709.824443                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41959.419779                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28534.887859                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35716.517667                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 33403.114884                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         2210                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs              13                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   299.153846                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          170                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1147174                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1147174                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          177                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          180                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        16460                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        16460                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         3382                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         3382                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.writebacks::writebacks      1027358                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1027358                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          142                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total          144                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        12070                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total        12070                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         3614                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         3614                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            3                       # number of InvalidateReq MSHR hits
 system.cpu1.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          177                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        19842                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        20023                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          177                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        19842                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        20023                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12786                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9298                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        22084                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks           18                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total           18                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       111700                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total       111700                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       804888                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       804888                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       144289                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       144289                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       172622                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       172622                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       239320                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       239320                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       623286                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       623286                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1061959                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1061959                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       258814                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       258814                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12786                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9298                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       623286                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1301279                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1946649                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12786                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9298                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       623286                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1301279                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       804888                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2751537                       # number of overall MSHR misses
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          142                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        15684                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total        15828                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            2                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          142                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data        15684                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total        15828                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11846                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8372                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        20218                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::writebacks           12                       # number of Writeback MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::total           12                       # number of Writeback MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       104589                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.CleanEvict_mshr_misses::total       104589                       # number of CleanEvict MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       722741                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       722741                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       139128                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       139128                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       166752                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       166752                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           16                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           16                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       235619                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       235619                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       607002                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       607002                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       972500                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       972500                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       268829                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       268829                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11846                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8372                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       607002                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1208119                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1835339                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11846                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8372                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       607002                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1208119                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       722741                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2558080                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        16935                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17002                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14896                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         6436                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         6503                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         6853                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         6853                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31831                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31898                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    801871000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  50468745441                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  50468745441                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2875133996                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2875133996                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2601766497                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2601766497                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2804499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2804499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9250303496                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9250303496                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13937951500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13937951500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  28711604984                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  28711604984                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16314942498                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16314942498                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13937951500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  37961908480                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  52701730980                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    436116500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    365754500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13937951500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  37961908480                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  50468745441                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 103170476421                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        13289                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        13356                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    375677000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    300105000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    675782000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  38256632769                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  38256632769                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2790814493                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2790814493                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2566482493                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2566482493                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      4901991                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4901991                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8739513998                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8739513998                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13678722000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13678722000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25793385972                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25793385972                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  15993437499                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  15993437499                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    375677000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    300105000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13678722000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34532899970                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  48887403970                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    375677000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    300105000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13678722000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34532899970                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  38256632769                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  87144036739                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5288500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2468909500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2474198000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2188801500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2188801500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    658981000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    664269500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    808356000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    808356000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5288500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   4657711000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   4662999500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027566                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000005                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000005                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1467337000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1472625500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021134                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047176                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027396                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000004                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000004                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.634120                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.634120                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.827681                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.827681                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.664676                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.664676                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.831171                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.831171                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.197282                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.197282                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.115328                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.267084                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.267084                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.637589                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.637589                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250766                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.170837                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021107                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047593                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.115328                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250766                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.211179                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.211179                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.110111                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110111                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.255144                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255144                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.606089                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.606089                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021134                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047176                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.110111                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245188                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.164193                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021134                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047176                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.110111                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245188                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.241473                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.228851                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33424.770007                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52932.700330                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20059.330207                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20059.330207                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15391.014758                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15391.014758                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 306374.437500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 306374.437500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37091.720099                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37091.720099                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22534.887859                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22534.887859                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26522.761925                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26522.761925                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 59492.976944                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 59492.976944                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22534.887859                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28584.021913                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26636.716143                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22534.887859                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28584.021913                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34066.188993                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102389.838409                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102148.162387                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117956.515395                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117956.515395                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 110417.412898                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 110259.471399                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq        997626                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     10426628                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        38204                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        14896                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      7712009                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict     10305258                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1022601                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp           10                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       482744                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       380034                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       500528                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           70                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1988029                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1220428                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5404468                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6543941                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       512654                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       405926                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16212466                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17789160                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       422162                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1316947                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         35740735                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    345886640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    566771243                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1562912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4846136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         919066931                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   12378423                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     35388761                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       1.367817                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.482211                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq        950963                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10318053                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        38676                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         6853                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      7301053                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict     10168977                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       922205                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       460948                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       364065                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       477238                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq          134                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          247                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1860044                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1122762                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5512640                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      6310959                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       550275                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       443547                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16537003                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17033306                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       391276                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1237529                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         35199114                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    352809840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    540363378                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1419696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4484152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         899077066                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                   11781593                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     34442064                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       1.358530                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.479569                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1          22372180     63.22%     63.22% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2          13016581     36.78%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1          22093559     64.15%     64.15% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2          12348505     35.85%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      35388761                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   15228808958                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      34442064                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   14907193441                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    179948989                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    189176968                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8110869278                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8273171683                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8234240098                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7832975507                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    227095399                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    214052518                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    711723893                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    677527956                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40342                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40342                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136642                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136642                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47708                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40376                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40376                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136648                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136648                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47800                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2990,18 +2986,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122642                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231246                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231246                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122682                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231286                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231286                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353968                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47728                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354048                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47820                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3011,18 +3007,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155749                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339000                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339000                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155812                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496835                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36238000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7497058                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36303000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -3042,7 +3038,7 @@ system.iobus.reqLayer16.occupancy               12000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -3050,71 +3046,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           569545477                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           569813871                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92731000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92765000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147942000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147982000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115612                       # number of replacements
-system.iocache.tags.tagsinuse               11.307418                       # Cycle average of tags in use
+system.iocache.tags.replacements               115623                       # number of replacements
+system.iocache.tags.tagsinuse               11.307008                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115628                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115639                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9081354759000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.848836                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.458583                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         9081350424000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.848834                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.458174                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.240552                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466161                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706714                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466136                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706688                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040964                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040964                       # Number of data accesses
+system.iocache.tags.tag_accesses              1041144                       # Number of tag accesses
+system.iocache.tags.data_accesses             1041144                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8895                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8932                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8915                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8952                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8895                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8935                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8915                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8955                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8895                       # number of overall misses
-system.iocache.overall_misses::total             8935                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8915                       # number of overall misses
+system.iocache.overall_misses::total             8955                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1662593136                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1667788136                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1625113033                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1630308033                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12635360341                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12635360341                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12635282838                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12635282838                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1662593136                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1668157136                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1625113033                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1630677033                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1662593136                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1668157136                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1625113033                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1630677033                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8895                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8932                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8915                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8952                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8895                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8935                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8915                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8955                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8895                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8935                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8915                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8955                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3129,54 +3125,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 186720.570533                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 182289.740101                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 182116.625670                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118387.703677                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118387.703677                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 186913.224958                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 186699.175825                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 182289.740101                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 182096.821106                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 186913.224958                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 186699.175825                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32654                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 182289.740101                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 182096.821106                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         30957                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3383                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3475                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.652380                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.908489                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106702                       # number of writebacks
-system.iocache.writebacks::total               106702                       # number of writebacks
+system.iocache.writebacks::writebacks          106693                       # number of writebacks
+system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8895                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8932                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8915                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8952                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8895                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8935                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8915                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8955                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8895                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8935                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8915                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8955                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1217843136                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1221188136                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1179363033                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1182708033                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7298960341                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7298960341                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7298882838                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7298882838                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1217843136                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1221407136                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1179363033                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1182927033                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1217843136                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1221407136                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1179363033                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1182927033                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3191,614 +3187,623 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132289.740101                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 132116.625670                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68387.703677                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68387.703677                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 136699.175825                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 132289.740101                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 132096.821106                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 136699.175825                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 132289.740101                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 132096.821106                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1760747                       # number of replacements
-system.l2c.tags.tagsinuse                63871.601453                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6095006                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1821172                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.346749                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1604376                       # number of replacements
+system.l2c.tags.tagsinuse                63973.571253                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5805157                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1664778                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.487046                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   18326.572985                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   182.034797                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   268.280441                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4619.393037                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9002.087865                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   179.474155                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   242.215899                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2745.232497                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8268.941513                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8662.499555                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.279641                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002778                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004094                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.070486                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.137361                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173567                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002739                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003696                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.041889                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.126174                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.132179                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.974603                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        11384                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          237                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        48804                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1357                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          826                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9193                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          233                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2623                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5288                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        40501                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.173706                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003616                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.744690                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 76795315                       # Number of tag accesses
-system.l2c.tags.data_accesses                76795315                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2680735                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2680735                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           32943                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           31048                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               63991                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6336                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5767                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12103                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           174506                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           154775                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               329281                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6806                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4586                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       614111                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       638498                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       286433                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6534                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4346                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       583459                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       618336                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       287570                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3050679                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6806                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4586                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              614111                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              813004                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       286433                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6534                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4346                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              583459                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              773111                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       287570                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3379960                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6806                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4586                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             614111                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             813004                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       286433                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6534                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4346                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             583459                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             773111                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       287570                       # number of overall hits
-system.l2c.overall_hits::total                3379960                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         48112                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         44467                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             92579                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        10023                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         8706                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18729                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         523780                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         170521                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             694301                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2882                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2624                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        74362                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       179746                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       302363                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2755                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2528                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        39827                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       128012                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       323843                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total        1058942                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2882                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2624                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             74362                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            703526                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       302363                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2755                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2528                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             39827                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            298533                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       323843                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1753243                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2882                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2624                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            74362                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           703526                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       302363                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2755                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2528                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            39827                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           298533                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       323843                       # number of overall misses
-system.l2c.overall_misses::total              1753243                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    280230500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    263754000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    543984500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     55711000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     50228500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    105939500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  68581440500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  18910817992                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  87492258492                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    268423000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    251208500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6463422502                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  17884384500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    254889500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    239052000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3438315000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  12527996000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 129202961347                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    268423000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    251208500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6463422502                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  86465825000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    254889500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    239052000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3438315000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  31438813992                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    216695219839                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    268423000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    251208500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6463422502                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  86465825000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  42388472929                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    254889500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    239052000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3438315000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  31438813992                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  45486797416                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   216695219839                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2680735                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2680735                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        81055                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        75515                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          156570                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        16359                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        14473                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30832                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       698286                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       325296                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1023582                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9688                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7210                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       688473                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       818244                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       588796                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9289                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6874                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       623286                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       746348                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       611413                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4109621                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9688                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7210                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          688473                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1516530                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       588796                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         9289                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6874                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          623286                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1071644                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       611413                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             5133203                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9688                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7210                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         688473                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1516530                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       588796                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         9289                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6874                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         623286                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1071644                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       611413                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            5133203                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.593572                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.588850                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.591295                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.612690                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.601534                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.607453                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.750094                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.524203                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.678305                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.108010                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.219673                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.063898                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171518                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.257674                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.108010                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.463905                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.063898                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.278575                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.341550                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.297481                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.363939                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.108010                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.463905                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.296587                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.367763                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.063898                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.278575                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.341550                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5824.544812                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5931.454787                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5875.895181                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5558.315873                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5769.411900                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5656.441882                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130935.584597                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 110900.229250                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 126014.881862                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86918.352142                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 99498.094533                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86331.257690                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97865.793832                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 122011.367334                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 86918.352142                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 122903.524532                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86331.257690                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 105311.017516                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 123596.797386                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93137.751561                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95734.946646                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 86918.352142                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 122903.524532                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92518.874773                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94561.708861                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86331.257690                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 105311.017516                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 123596.797386                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             12094                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   16659.203027                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   347.238411                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   480.079854                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4726.149973                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    13722.940289                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19518.694683                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    39.930664                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    37.878689                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2515.843694                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3528.824222                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2396.787747                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.254199                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.005298                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.007325                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.072115                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.209395                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.297832                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000609                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000578                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.038389                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.053846                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.036572                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.976159                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10879                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          220                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49303                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1360                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          633                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8884                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          213                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2421                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4883                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        41670                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.166000                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.752304                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 72712060                       # Number of tag accesses
+system.l2c.tags.data_accesses                72712060                       # Number of data accesses
+system.l2c.Writeback_hits::writebacks         2536205                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2536205                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data           30090                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           27013                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               57103                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          6458                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          6165                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             12623                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           162036                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           153866                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               315902                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6626                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4489                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       594958                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       614676                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       296621                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6612                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4192                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       566970                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       555261                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       284702                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2935107                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6626                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4489                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              594958                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              776712                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       296621                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          6612                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4192                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              566970                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              709127                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       284702                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3251009                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         6626                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         4489                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             594958                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             776712                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       296621                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         6612                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4192                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             566970                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             709127                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       284702                       # number of overall hits
+system.l2c.overall_hits::total                3251009                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         47588                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         43593                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             91181                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         9906                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data        10331                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           20237                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         509249                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         164886                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             674135                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2732                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2383                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        65927                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       171520                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       297602                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2128                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1988                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        40032                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       112082                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       243379                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         939773                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         2732                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         2383                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             65927                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            680769                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       297602                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2128                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         1988                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             40032                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            276968                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       243379                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1613908                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         2732                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         2383                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            65927                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           680769                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       297602                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2128                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         1988                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            40032                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           276968                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       243379                       # number of overall misses
+system.l2c.overall_misses::total              1613908                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    285345500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    229148000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    514493500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     53588000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data     57099500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    110687500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  66726621996                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data  17979484499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  84706106495                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    253095500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    219982000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5658543002                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  16552075998                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  41040485814                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    202746500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    183043000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3466352000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  10969692499                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  33324994201                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 111871010514                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    253095500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    219982000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   5658543002                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  83278697994                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  41040485814                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    202746500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    183043000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   3466352000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  28949176998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  33324994201                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    196577117009                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    253095500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    219982000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   5658543002                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  83278697994                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  41040485814                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    202746500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    183043000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3466352000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  28949176998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  33324994201                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   196577117009                       # number of overall miss cycles
+system.l2c.Writeback_accesses::writebacks      2536205                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2536205                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        77678                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        70606                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          148284                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        16364                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        16496                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         32860                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       671285                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       318752                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           990037                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9358                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6872                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       660885                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       786196                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       594223                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8740                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6180                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       607002                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       667343                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       528081                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3874880                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         9358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6872                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          660885                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1457481                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       594223                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         8740                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6180                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          607002                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          986095                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       528081                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4864917                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         9358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6872                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         660885                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1457481                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       594223                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         8740                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6180                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         607002                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         986095                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       528081                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4864917                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.612632                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.617412                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.614908                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.605353                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.626273                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.615855                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.758618                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.517286                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.680919                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.291943                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.346769                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.099756                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.218164                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.500825                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.243478                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.321683                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.065950                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.167953                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.460874                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.242530                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.291943                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.346769                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.099756                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.467086                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.500825                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.243478                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.321683                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.065950                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.280874                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.460874                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.331744                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.291943                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.346769                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.099756                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.467086                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.500825                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.243478                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.321683                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.065950                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.280874                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.460874                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.331744                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  5996.165000                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5256.532012                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5642.551628                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5409.650717                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5527.006098                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5469.560706                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 131029.461022                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109041.910769                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 125651.548273                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92641.105417                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92313.050776                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85830.433692                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96502.308757                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95275.610902                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92073.943662                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86589.528377                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97872.026722                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 119040.460318                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92641.105417                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92313.050776                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 85830.433692                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 122330.332307                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95275.610902                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92073.943662                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 86589.528377                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 104521.738966                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 121801.934812                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92641.105417                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92313.050776                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 85830.433692                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 122330.332307                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95275.610902                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92073.943662                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 86589.528377                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 104521.738966                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 121801.934812                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              7662                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      115                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       92                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    105.165217                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     83.282609                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1358225                       # number of writebacks
-system.l2c.writebacks::total                  1358225                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          229                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           34                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          211                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           37                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          511                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            229                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            211                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             37                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                511                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           229                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            34                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           211                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            37                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               511                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        57055                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        57055                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        48112                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        44467                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        92579                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10023                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8706                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18729                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       523780                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       170521                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        694301                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2882                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2624                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        74133                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       179712                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2755                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2528                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        39616                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       127975                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total      1058431                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         2882                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2624                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        74133                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       703492                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2755                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2528                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        39616                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       298496                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1752732                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         2882                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         2624                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        74133                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       703492                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       302363                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2755                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2528                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        39616                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       298496                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       323843                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1752732                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1246552                       # number of writebacks
+system.l2c.writebacks::total                  1246552                       # number of writebacks
+system.l2c.ReadExReq_mshr_hits::cpu0.data            3                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total               3                       # number of ReadExReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          217                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           87                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher           35                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          178                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           73                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher            8                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          598                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            217                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             90                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher           35                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            178                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             73                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher            8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                601                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           217                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            90                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher           35                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           178                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            73                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher            8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               601                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        52518                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        52518                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        47588                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        43593                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        91181                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9906                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        10331                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        20237                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       509246                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       164886                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        674132                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2732                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2383                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        65710                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       171433                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       297567                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2128                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1988                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        39854                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       112009                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       243371                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       939175                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         2732                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         2383                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        65710                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       680679                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       297567                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2128                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         1988                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        39854                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       276895                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       243371                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1613307                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         2732                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         2383                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        65710                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       680679                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       297567                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2128                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         1988                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        39854                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       276895                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       243371                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1613307                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21352                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32342                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16933                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        59646                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        23308                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14896                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38204                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6434                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        60137                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        31823                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         6853                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38676                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        44660                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        64165                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31829                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        97850                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1000759503                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    924536001                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1925295504                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    208161502                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    180991502                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    389153004                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  63343640500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  17205607992                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  80549248492                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5703318002                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  16083965000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3027081000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11244495000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 118577752347                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   5703318002                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  79427605500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3027081000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  28450102992                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 199127000839                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    239603000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    224968500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   5703318002                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  79427605500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39364842929                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    227339500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    213772000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3027081000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  28450102992                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  42248367416                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 199127000839                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13287                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        98813                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    990436504                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    906238506                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1896675010                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    205762002                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    214626501                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    420388503                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  61634019996                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  16330624499                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  77964644495                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    225775500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    196152000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4984045002                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14830916998                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  38062777880                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    181466500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    163163000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   3054573000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9843412999                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  30890783215                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total 102433066094                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    225775500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    196152000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   4984045002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  76464936994                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  38062777880                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    181466500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    163163000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3054573000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  26174037498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  30890783215                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 180397710589                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    225775500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    196152000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   4984045002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  76464936994                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  38062777880                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    181466500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    163163000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3054573000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  26174037498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  30890783215                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 180397710589                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3340995000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4976486500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4081500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2164071000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6829895500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3477095533                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1935550000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5412645533                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    543120500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6844436500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4733537033                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    691840500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5425377533                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1320748000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6818090533                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9710023533                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4081500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4099621000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12242541033                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1234961000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12269814033                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.593572                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.588850                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.591295                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.612690                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.601534                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.607453                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.750094                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.524203                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.678305                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.219631                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.171468                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.257550                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.463883                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.278540                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.341450                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.297481                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.363939                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.107677                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.463883                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.513528                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.296587                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.367763                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.063560                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.278540                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.529663                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.341450                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20800.621529                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.508332                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.244332                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20768.382919                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20789.283483                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20778.098350                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120935.584597                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 100900.229250                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 116014.881862                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112904.774326                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95311.504985                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 113609.496968                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76933.592354                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112904.774326                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76410.566438                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95311.504985                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 113609.496968                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.612632                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.617412                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.614908                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.605353                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.626273                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.615855                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.758614                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.517286                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.680916                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.291943                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.346769                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.099427                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.218054                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.500767                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.243478                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.321683                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.065657                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.167843                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.460859                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.242375                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.291943                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.346769                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.099427                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.467024                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.500767                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.243478                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.321683                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.065657                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.280800                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.460859                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.331621                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.291943                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.346769                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.099427                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.467024                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.500767                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.243478                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.321683                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.065657                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.280800                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.460859                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.331621                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.736488                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.624458                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20801.208695                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20771.451847                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20774.997677                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20773.261995                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121029.954081                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99041.910769                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 115651.896802                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75849.109755                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86511.447609                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76644.075877                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87880.554232                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109067.070667                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75849.109755                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112336.265691                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76644.075877                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94526.941613                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 111818.587900                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75849.109755                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112336.265691                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76644.075877                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94526.941613                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 111818.587900                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153870.709913                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84414.128070                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 113814.066215                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148745.782390                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100954.399533                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140277.627805                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151328.972695                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 92945.059080                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 124172.062714                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               59646                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1127009                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38204                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38204                       # Transaction distribution
-system.membus.trans_dist::Writeback           1464927                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           280718                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           444619                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         331926                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          118163                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            708914                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           687449                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1067363                       # Transaction distribution
+system.membus.trans_dist::ReadReq               60137                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1008264                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38676                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38676                       # Transaction distribution
+system.membus.trans_dist::Writeback           1353245                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           256072                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           446472                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         317458                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          117838                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            689582                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           667715                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        948127                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122642                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122682                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25116                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6087631                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6235467                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342027                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342027                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6577494                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155749                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27002                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5660502                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5810264                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342643                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342643                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6152907                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    198978048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    199184601                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7249472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7249472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               206434073                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           682959                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4505681                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        54004                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    182936448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    183146836                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7268096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7268096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190414932                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           670794                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4218827                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4505681    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4218827    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4505681                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98301494                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4218827                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            97993999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21116985                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            22746984                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         10136025529                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9381331556                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         9507659574                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8783305125                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          229108938                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229295864                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3842,60 +3847,60 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq              59648                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           5069827                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38204                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38204                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          4145743                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1638680                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          501758                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        344029                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         845787                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          136                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          136                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1170821                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1170821                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      5017419                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              60139                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4816420                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38676                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38676                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          3889503                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1527175                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          497158                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        330081                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         827239                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          247                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          247                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1142368                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1142368                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4763508                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9001938                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7449274                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16451212                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    278573838                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    222195147                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              500768985                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3698425                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         14333755                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.138980                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.345926                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8767118                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6899331                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15666449                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    271825986                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    202528722                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              474354708                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3515812                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         13605383                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.134927                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.341646                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               12341651     86.10%     86.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                1992104     13.90%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               11769647     86.51%     86.51% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                1835736     13.49%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           14333755                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9346036195                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           13605383                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8891301093                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2541000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2589000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5271518855                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5132723331                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4504542320                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4211299918                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4738                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   14670                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   14252                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    7288                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
index 026d5a2a0..11a1cd43d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -201,7 +201,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -542,7 +542,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -652,7 +652,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -740,7 +740,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1155,9 +1155,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
index a2bc54e0f..231e72707 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 10:59:42
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:57:07
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51323721423000 because m5_exit instruction encountered
+Exiting @ tick 51562169701000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 02e1510aa..591f883e9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,141 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.323721                       # Number of seconds simulated
-sim_ticks                                51323721423000                       # Number of ticks simulated
-final_tick                               51323721423000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.562170                       # Number of seconds simulated
+sim_ticks                                51562169701000                       # Number of ticks simulated
+final_tick                               51562169701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 120356                       # Simulator instruction rate (inst/s)
-host_op_rate                                   141420                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7238849372                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 678076                       # Number of bytes of host memory used
-host_seconds                                  7090.04                       # Real time elapsed on the host
-sim_insts                                   853325819                       # Number of instructions simulated
-sim_ops                                    1002674190                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  82472                       # Simulator instruction rate (inst/s)
+host_op_rate                                    96938                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3850541751                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 726532                       # Number of bytes of host memory used
+host_seconds                                 13390.89                       # Real time elapsed on the host
+sim_insts                                  1104366834                       # Number of instructions simulated
+sim_ops                                    1298086167                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       203200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       189632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5727200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          73778504                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        419776                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             80318312                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5727200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5727200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68723904                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       657984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       557504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           6634080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         148649160                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        417792                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            156916520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      6634080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6634080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    139624832                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68744484                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3175                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         2963                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             105440                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1152802                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6559                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1270939                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1073811                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         139645412                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker        10281                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         8711                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             119610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2322656                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6528                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2467786                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         2181638                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1076384                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3959                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3695                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               111590                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1437513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8179                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1564935                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          111590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             111590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1339028                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1339429                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1339028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3695                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              111590                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1437914                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8179                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2904365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1270939                       # Number of read requests accepted
-system.physmem.writeReqs                      1076384                       # Number of write requests accepted
-system.physmem.readBursts                     1270939                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1076384                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 81299584                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40512                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  68742976                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  80318312                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               68744484                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      633                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         142017                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               76590                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               80112                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               82312                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               76894                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               75148                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               84486                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               75307                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               76047                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               76921                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              104197                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              75653                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              81028                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              74845                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              77383                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              76622                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              76761                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               64108                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67910                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               69982                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               67432                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               65959                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               70786                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64733                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               66187                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67287                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               71812                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65064                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              69201                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              65082                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              66370                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66024                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              66172                       # Per bank write bursts
+system.physmem.num_writes::total              2184211                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker          12761                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker          10812                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               128662                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2882911                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3043249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          128662                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             128662                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2707893                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2708292                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2707893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker         12761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker         10812                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              128662                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2883310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5751541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2467786                       # Number of read requests accepted
+system.physmem.writeReqs                      2184211                       # Number of write requests accepted
+system.physmem.readBursts                     2467786                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2184211                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                157889856                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     48448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 139644224                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 156916520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              139645412                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      757                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         155211                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              149005                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              156339                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              155955                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              150628                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              148084                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              159303                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              149188                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              152515                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              150862                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              179370                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             150320                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             155893                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             152080                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             155961                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             150556                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             150970                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              132106                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              138501                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              137398                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              135602                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              133392                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              140433                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              132940                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              137025                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              135656                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              141181                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             134433                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             138339                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             136301                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             138853                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             135122                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             134659                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51323720227500                       # Total gap between requests
+system.physmem.numWrRetry                          21                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51562168447500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1249654                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2446501                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1073811                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    646219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    339232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    151287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    128129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       489                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       502                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       533                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       812                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       936                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      392                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      192                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2181638                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1276105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    831313                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    193469                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    160610                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       761                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       490                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       829                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       946                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      413                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      181                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      164                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      120                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -159,164 +159,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    11927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    14439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    31518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    44897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    53343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    63481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    63532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    67021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    67803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    70464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    69167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    70329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    66867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    85010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    86471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    65847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    69713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    62929                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       481355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      311.708207                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.914901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     339.146013                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         186832     38.81%     38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       113175     23.51%     62.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        45398      9.43%     71.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23450      4.87%     76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18101      3.76%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11671      2.42%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10460      2.17%     84.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8315      1.73%     86.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        63953     13.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         481355                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61522                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.647411                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      265.936082                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          61519    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    20208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    23029                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    68337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   107857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   119474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   131451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   131860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   135328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   136231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   138984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   139007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   140497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   136343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   166652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   162914                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   137438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   145049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   131294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      409                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       55                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       938073                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      317.175418                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     184.850858                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.830774                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         348981     37.20%     37.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       217922     23.23%     60.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        89990      9.59%     70.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        51985      5.54%     75.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        41514      4.43%     79.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        28050      2.99%     82.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        24686      2.63%     85.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        20558      2.19%     87.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       114387     12.19%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         938073                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples        129462                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        19.055908                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      183.344638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047         129459    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61522                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61522                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.458942                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.948779                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.823778                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           58490     95.07%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             664      1.08%     96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             448      0.73%     96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             190      0.31%     97.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             308      0.50%     97.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             527      0.86%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             143      0.23%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              33      0.05%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              36      0.06%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.03%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              32      0.05%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              22      0.04%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             426      0.69%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              45      0.07%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              33      0.05%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              35      0.06%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              13      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            31      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total          129462                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples        129462                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.853911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.595936                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        4.789289                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19          125866     97.22%     97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1229      0.95%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             433      0.33%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             197      0.15%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             330      0.25%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             524      0.40%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             121      0.09%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              23      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              39      0.03%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              16      0.01%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              43      0.03%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              23      0.02%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             425      0.33%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              36      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              42      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              37      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              19      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            35      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61522                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    31530968444                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55349205944                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6351530000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       24821.55                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total          129462                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    61876185756                       # Total ticks spent queuing
+system.physmem.totMemAccLat              108132979506                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  12335145000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25081.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  43571.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.58                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.34                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.56                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.34                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43831.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.06                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.71                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.04                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.71                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.31                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1047361                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    815697                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.94                       # Row buffer hit rate for writes
-system.physmem.avgGap                     21864788.20                       # Average gap between requests
-system.physmem.pageHitRate                      79.47                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1828287720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  997577625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4889757600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3480388560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1226219398425                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29718601656750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34308233025720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.467372                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49439480717043                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713811840000                       # Time in different power states
+system.physmem.avgWrQLen                        25.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    2056722                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1654173                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.81                       # Row buffer hit rate for writes
+system.physmem.avgGap                     11083878.27                       # Average gap between requests
+system.physmem.pageHitRate                      79.82                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3550765680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1937421750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                9523885800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               7046332560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3367790100480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1313489115900                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29785116936750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34488454558920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.871313                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49548907375208                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1721774080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    170428636707                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    291487862292                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1810756080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  988011750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5018598000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3479837760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352215959040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1228704019020                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29716422156750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34308639338400                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.475289                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49435820968594                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713811840000                       # Time in different power states
+system.physmem_1.actEnergy                 3541066200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1932129375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                9718893600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               7092645120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3367790100480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1316895447015                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29782128927000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34489099208790                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.883816                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49543906734220                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1721774080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    174088371406                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    296486485780                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -340,15 +337,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               225557622                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         150824960                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12221670                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            159273353                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               104130221                       # Number of BTB hits
+system.cpu.branchPred.lookups               288825634                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         198097109                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          13566789                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            207338959                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               136913226                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.378307                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30957399                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             344598                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             66.033526                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                37451224                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             402112                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -379,87 +376,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    951838                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                951838                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16475                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       156308                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       435006                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       516832                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  1986.510123                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-32767       508349     98.36%     98.36% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-65535         5443      1.05%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-98303         1244      0.24%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::98304-131071         1085      0.21%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-163839          165      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::163840-196607          178      0.03%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-229375          121      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::229376-262143           54      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-294911           95      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::294912-327679            7      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-360447            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::360448-393215           38      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-425983           41      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::425984-458751            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       516832                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       485267                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       475094     97.90%     97.90% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         9290      1.91%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          546      0.11%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          199      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           82      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           20      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       485267                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 776250627376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.722476                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.519579                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  774163165376     99.73%     99.73% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1120728500      0.14%     99.88% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     435636500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     187638500      0.02%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     148036000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    113935000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     26323500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     52542500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2621500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 776250627376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        156309     90.46%     90.46% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         16475      9.54%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       172784                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       951838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                   1430156                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong               1430156                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        30793                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       273791                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       677378                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       752778                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2375.228819                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       746726     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         4359      0.58%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          685      0.09%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          394      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          311      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215          120      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751          171      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       752778                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       802636                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       783977     97.68%     97.68% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071        16023      2.00%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1555      0.19%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          558      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          316      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          129      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           37      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           22      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       802636                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 1044763922448                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.739319                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.520240                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  1040800473448     99.62%     99.62% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    2579873000      0.25%     99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     637994000      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     271834500      0.03%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     201274500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    132884500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     46819000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     89469000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      3255500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19        45000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 1044763922448                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        273792     89.89%     89.89% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         30793     10.11%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       304585                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data      1430156                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       951838                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       172784                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total      1430156                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       304585                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       172784                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1124622                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       304585                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1734741                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    170417440                       # DTB read hits
-system.cpu.dtb.read_misses                     677013                       # DTB read misses
-system.cpu.dtb.write_hits                   148384109                       # DTB write hits
-system.cpu.dtb.write_misses                    274825                       # DTB write misses
-system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
+system.cpu.dtb.read_hits                    217117628                       # DTB read hits
+system.cpu.dtb.read_misses                    1002788                       # DTB read misses
+system.cpu.dtb.write_hits                   192115888                       # DTB write hits
+system.cpu.dtb.write_misses                    427368                       # DTB write misses
+system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               39714                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1025                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72556                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid               63203                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1203                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    87986                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10696                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                  15675                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     70061                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                171094453                       # DTB read accesses
-system.cpu.dtb.write_accesses               148658934                       # DTB write accesses
+system.cpu.dtb.perms_faults                     85972                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                218120416                       # DTB read accesses
+system.cpu.dtb.write_accesses               192543256                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         318801549                       # DTB hits
-system.cpu.dtb.misses                          951838                       # DTB misses
-system.cpu.dtb.accesses                     319753387                       # DTB accesses
+system.cpu.dtb.hits                         409233516                       # DTB hits
+system.cpu.dtb.misses                         1430156                       # DTB misses
+system.cpu.dtb.accesses                     410663672                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -489,877 +483,877 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    162167                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                162167                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1433                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       122178                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17760                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       144407                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1087.128740                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  7079.961036                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       143546     99.40%     99.40% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          491      0.34%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303          245      0.17%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           86      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839           14      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    177415                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                177415                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1441                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       130680                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        19804                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       157611                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1499.045117                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 10189.386950                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       155888     98.91%     98.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          579      0.37%     99.27% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          739      0.47%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          292      0.19%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           35      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           38      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375           19      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       144407                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       141371                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 27408.566821                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       138940     98.28%     98.28% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071         2106      1.49%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607          209      0.15%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           62      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           27      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           18      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       157611                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       151925                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29463.087050                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       146250     96.26%     96.26% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         4800      3.16%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          534      0.35%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          196      0.13%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           80      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           44      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           15      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       141371                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 655988501088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.936740                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.243710                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     41542191152      6.33%      6.33% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    614402729936     93.66%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        43110500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          467500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total       151925                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 920206753364                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.948994                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.220270                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     46987798652      5.11%      5.11% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    873167595712     94.89%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        50573500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          783500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 655988501088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        122178     98.84%     98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1433      1.16%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       123611                       # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 920206753364                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        130680     98.91%     98.91% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1441      1.09%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       132121                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162167                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       162167                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       177415                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       177415                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123611                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       123611                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       285778                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    358625455                       # ITB inst hits
-system.cpu.itb.inst_misses                     162167                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       132121                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       132121                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       309536                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    461294711                       # ITB inst hits
+system.cpu.itb.inst_misses                     177415                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               39714                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1025                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53363                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               63203                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1203                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    62159                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    372145                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    458083                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                358787622                       # ITB inst accesses
-system.cpu.itb.hits                         358625455                       # DTB hits
-system.cpu.itb.misses                          162167                       # DTB misses
-system.cpu.itb.accesses                     358787622                       # DTB accesses
-system.cpu.numCycles                       1590418745                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                461472126                       # ITB inst accesses
+system.cpu.itb.hits                         461294711                       # DTB hits
+system.cpu.itb.misses                          177415                       # DTB misses
+system.cpu.itb.accesses                     461472126                       # DTB accesses
+system.cpu.numCycles                       2141240199                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          646410999                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1006402404                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225557622                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135087620                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     866562323                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26107474                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3678311                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                25439                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9275413                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1023850                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          676                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 358236204                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6112300                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   49056                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1540030748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.765724                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.157325                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          785638694                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1289733601                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   288825634                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          174364450                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1267374465                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29210356                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    4418623                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                28241                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles      12152128                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1217886                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          633                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 460817774                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6728045                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   53516                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         2085435848                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.725171                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.139838                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                979927440     63.63%     63.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                215057699     13.96%     77.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70955696      4.61%     82.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                274089913     17.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1366680941     65.53%     65.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                278589155     13.36%     78.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 86788366      4.16%     83.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                353377386     16.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1540030748                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.141823                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.632791                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                525466953                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             519947088                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 434864784                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50506307                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9245616                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33796734                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3867997                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1090931528                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29050280                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9245616                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                570424085                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                50840114                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      363017689                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 440398811                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             106104433                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1071115355                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6801917                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5040663                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 343395                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 645255                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               54344412                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20434                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1018974666                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1651092433                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1266893179                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1473696                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             953236782                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65737881                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           27206823                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23528426                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 103688094                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            174464093                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           151959443                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9931077                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9032567                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1035787653                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27506074                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1051526043                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3293799                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60619533                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33780075                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         314140                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1540030748                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.682795                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.925415                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           2085435848                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.134887                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.602330                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                612239538                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             852574124                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 529946172                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              80118083                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10557931                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             41219534                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               4107385                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1403247413                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              32566835                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               10557931                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                674962554                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                85247440                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      550746700                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 547461697                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             216459526                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1379612307                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               7971383                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7360618                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 963827                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1074082                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents              133209723                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            22971                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1329803577                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2195861380                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1637517470                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1437183                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1251935276                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 77868298                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           43546894                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       39087703                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 166786807                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            221659276                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           196613901                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12565776                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11015266                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1326936815                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            43849103                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1356961205                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4098709                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        72699747                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41430931                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         372473                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    2085435848                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.650685                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.914510                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           888949202     57.72%     57.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           336251490     21.83%     79.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           235798342     15.31%     94.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72468185      4.71%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6544331      0.42%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19198      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0          1239320860     59.43%     59.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           449936886     21.58%     81.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           291017288     13.95%     94.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            95682212      4.59%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9449903      0.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               28699      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1540030748                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      2085435848                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                58035888     35.01%     35.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  99674      0.06%     35.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26738      0.02%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              574      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44566242     26.88%     61.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              63041416     38.03%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                73477453     34.17%     34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  90486      0.04%     34.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26768      0.01%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              385      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               57876005     26.91%     61.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              83594438     38.87%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             724142674     68.87%     68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2543730      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122779      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 376      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121012      0.01%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            174312709     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           150282706     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                31      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             937288786     69.07%     69.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2936989      0.22%     69.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                129444      0.01%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 372      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         114407      0.01%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            221949724     16.36%     85.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194541406     14.34%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1051526043                       # Type of FU issued
-system.cpu.iq.rate                           0.661163                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   165770532                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157648                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3809671307                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1123107931                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1033541701                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2475857                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             947397                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       910004                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1215741366                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1555198                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4333965                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1356961205                       # Type of FU issued
+system.cpu.iq.rate                           0.633727                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   215065535                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.158491                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5016097714                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1442740685                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1335189379                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2424787                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             927446                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       888349                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1570502436                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1524273                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5709357                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13839303                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14833                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       143349                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6338712                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     16902439                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24350                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       184211                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8196884                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2540349                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1552925                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      3577769                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1870440                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9245616                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6389360                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               5797347                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1063516239                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               10557931                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12374030                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7706525                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1371058602                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             174464093                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            151959443                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           23100216                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  59008                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               5663632                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         143349                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3667729                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5111764                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8779493                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1040328227                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             170406440                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10257681                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             221659276                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            196613901                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           38550114                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 178028                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               7343410                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         184211                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4239042                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5703306                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              9942348                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1343677933                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             217120223                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          11882036                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222512                       # number of nop insts executed
-system.cpu.iew.exec_refs                    318786335                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                197400349                       # Number of branches executed
-system.cpu.iew.exec_stores                  148379895                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.654122                       # Inst execution rate
-system.cpu.iew.wb_sent                     1035262700                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1034451705                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 440415620                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 712619707                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        272684                       # number of nop insts executed
+system.cpu.iew.exec_refs                    409245203                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                255119365                       # Number of branches executed
+system.cpu.iew.exec_stores                  192124980                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.627523                       # Inst execution rate
+system.cpu.iew.wb_sent                     1337102879                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1336077728                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 573421420                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 940568778                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.650427                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618023                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.623974                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.609654                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51498978                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        27191934                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8413549                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1528028900                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.656188                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.286676                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        62140410                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        43476630                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9519542                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   2071346493                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.626687                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.267080                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1013092181     66.30%     66.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    289858237     18.97%     85.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    121052617      7.92%     93.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36682667      2.40%     95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28563883      1.87%     97.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14105791      0.92%     98.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8655946      0.57%     98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4198069      0.27%     99.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11819509      0.77%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1395640231     67.38%     67.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    393909449     19.02%     86.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    150461425      7.26%     93.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     44316735      2.14%     95.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     35977476      1.74%     97.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     18232281      0.88%     98.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10892931      0.53%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5452952      0.26%     99.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     16463013      0.79%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1528028900                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            853325819                       # Number of instructions committed
-system.cpu.commit.committedOps             1002674190                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   2071346493                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1104366834                       # Number of instructions committed
+system.cpu.commit.committedOps             1298086167                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      306245520                       # Number of memory references committed
-system.cpu.commit.loads                     160624789                       # Number of loads committed
-system.cpu.commit.membars                     6977905                       # Number of memory barriers committed
-system.cpu.commit.branches                  190474151                       # Number of branches committed
-system.cpu.commit.fp_insts                     896785                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 921116747                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25400785                       # Number of function calls committed.
+system.cpu.commit.refs                      393173853                       # Number of memory references committed
+system.cpu.commit.loads                     204756836                       # Number of loads committed
+system.cpu.commit.membars                     9104821                       # Number of memory barriers committed
+system.cpu.commit.branches                  246834909                       # Number of branches committed
+system.cpu.commit.fp_insts                     874964                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1186447841                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             30876862                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        694059947     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2158876      0.22%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98131      0.01%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111674      0.01%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       160624789     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      145620731     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        902159630     69.50%     69.50% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2542825      0.20%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           103949      0.01%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       105868      0.01%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       204756836     15.77%     85.49% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      188417017     14.51%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1002674190                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11819509                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2562796067                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2120254358                       # The number of ROB writes
-system.cpu.timesIdled                         8129447                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        50387997                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101057024238                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   853325819                       # Number of Instructions Simulated
-system.cpu.committedOps                    1002674190                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.863788                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.863788                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.536542                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.536542                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1231590969                       # number of integer regfile reads
-system.cpu.int_regfile_writes               735370525                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462122                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   782688                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 226859046                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                227515194                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2534481060                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               27245755                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9758519                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.983709                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           284707567                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9759031                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.173754                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total        1298086167                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              16463013                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3405665880                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2734432791                       # The number of ROB writes
+system.cpu.timesIdled                         9009507                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        55804351                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100983102115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                  1104366834                       # Number of Instructions Simulated
+system.cpu.committedOps                    1298086167                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.938885                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.938885                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.515760                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.515760                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1596434625                       # number of integer regfile reads
+system.cpu.int_regfile_writes               940526203                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1424965                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   765828                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 311708448                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                312593649                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              3410532874                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               44362921                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements          13614186                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.983787                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           360288791                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          13614698                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             26.463223                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1642601500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.983709                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.983787                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1243872376                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1243872376                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    147964440                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147964440                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128940955                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128940955                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       380183                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        380183                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       324678                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       324678                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3327415                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3327415                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3725844                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3725844                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     276905395                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        276905395                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    277285578                       # number of overall hits
-system.cpu.dcache.overall_hits::total       277285578                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9612542                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9612542                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11385353                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11385353                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1184834                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1184834                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1232047                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1232047                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       450033                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       450033                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1595334423                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1595334423                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    186468319                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       186468319                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    162903680                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      162903680                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       463393                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        463393                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       334025                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       334025                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4787397                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4787397                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      5271269                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      5271269                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     349371999                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        349371999                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    349835392                       # number of overall hits
+system.cpu.dcache.overall_hits::total       349835392                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12723000                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12723000                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     18625078                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     18625078                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      2035956                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      2035956                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1270469                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1270469                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       547335                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       547335                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20997895                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20997895                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22182729                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22182729                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 144669003500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 330867751444                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  63675897168                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  63675897168                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6433485000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6433485000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     31348078                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       31348078                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     33384034                       # number of overall misses
+system.cpu.dcache.overall_misses::total      33384034                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 203343916000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 979374659621                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  74427778402                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  74427778402                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8800618500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   8800618500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       251000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       251000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 475536754944                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 475536754944                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 475536754944                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 475536754944                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    157576982                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    157576982                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    140326308                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    140326308                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1565017                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1565017                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1556725                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1556725                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3777448                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3777448                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3725851                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3725851                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    297903290                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    297903290                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    299468307                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    299468307                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061002                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.061002                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081135                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081135                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.757074                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.757074                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791435                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791435                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119137                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119137                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070486                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070486                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074074                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074074                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1182718575621                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1182718575621                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    199191319                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    199191319                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    181528758                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    181528758                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2499349                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2499349                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5334732                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      5334732                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      5271276                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      5271276                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    380720077                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    380720077                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    383219426                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    383219426                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.063873                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.063873                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.102601                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.102601                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.814595                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.814595                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791819                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791819                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.102598                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.102598                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.082339                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.082339                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.087115                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.087115                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22646.877458                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21437.252150                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     35158879                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37728.583412                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35427.671072                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     46020939                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1606955                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           2096301                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.879193                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.953402                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7549082                       # number of writebacks
-system.cpu.dcache.writebacks::total           7549082                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4467834                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4467834                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9360902                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9360902                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7079                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7079                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219205                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219205                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13828736                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13828736                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13828736                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13828736                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5144708                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5144708                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2024451                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2024451                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1178103                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1178103                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224968                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1224968                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230828                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       230828                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks     10299062                       # number of writebacks
+system.cpu.dcache.writebacks::total          10299062                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5706012                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5706012                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15543150                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total     15543150                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7171                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7171                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       263403                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       263403                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     21249162                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     21249162                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     21249162                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     21249162                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7016988                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7016988                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3081928                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      3081928                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2029224                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      2029224                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1263298                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1263298                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       283932                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       283932                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7169159                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7169159                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8347262                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8347262                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75818409500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75818409500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  57062160713                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  57062160713                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20148080000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20148080000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  62191648168                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  62191648168                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3063087000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3063087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     10098916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     10098916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     12128140                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     12128140                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  32373018500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  32373018500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  72874671402                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  72874671402                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   4076865500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   4076865500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       244000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       244000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 132880570213                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 153028650213                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5828327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5828327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5707957967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5707957967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11536285467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11536285467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032649                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032649                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014427                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014427                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.752773                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.752773                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786888                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786888                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061107                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061107                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024065                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024065                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027874                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027874                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 254057212172                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 286430230672                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5829096500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5829096500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5708243467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5708243467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11537339967                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11537339967                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035227                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035227                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016978                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016978                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.811901                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.811901                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787350                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787350                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.053223                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.053223                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026526                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026526                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031648                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031648                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15042093                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.944879                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           342405629                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15042605                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.762389                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements          16756542                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.945135                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           443237235                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          16757054                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             26.450785                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       17214303500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.944879                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999892                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.945135                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999893                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999893                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         373257734                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        373257734                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    342405629                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       342405629                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     342405629                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        342405629                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    342405629                       # number of overall hits
-system.cpu.icache.overall_hits::total       342405629                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15809279                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15809279                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15809279                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15809279                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15809279                       # number of overall misses
-system.cpu.icache.overall_misses::total      15809279                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208403044384                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208403044384                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208403044384                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208403044384                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208403044384                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    358214908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    358214908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    358214908                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    358214908                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    358214908                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    358214908                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044134                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044134                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044134                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044134                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044134                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044134                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13182.324405                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13182.324405                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        15030                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         477553750                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        477553750                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    443237235                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       443237235                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     443237235                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        443237235                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    443237235                       # number of overall hits
+system.cpu.icache.overall_hits::total       443237235                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     17559241                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      17559241                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     17559241                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       17559241                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     17559241                       # number of overall misses
+system.cpu.icache.overall_misses::total      17559241                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 232141013891                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 232141013891                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 232141013891                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 232141013891                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 232141013891                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    460796476                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    460796476                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    460796476                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    460796476                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    460796476                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    460796476                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.038106                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.038106                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.038106                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.038106                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.038106                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.038106                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13220.446937                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13220.446937                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        15959                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1210                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1225                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    12.421488                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    13.027755                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       766453                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       766453                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       766453                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       766453                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       766453                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       766453                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15042826                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15042826                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15042826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15042826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15042826                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15042826                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       801966                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       801966                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       801966                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       801966                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       801966                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       801966                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16757275                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     16757275                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     16757275                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     16757275                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     16757275                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     16757275                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21295                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 186915451392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 186915451392                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 208567956898                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 208567956898                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1594412000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1594412000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   1594412000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041994                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.041994                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041994                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.041994                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036366                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036366                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036366                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.036366                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036366                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.036366                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1148683                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65278.817014                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46198537                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1210914                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.151790                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          2345734                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65318.237935                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           55622573                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2409067                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.088844                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      15659706000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   301.460755                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   460.210435                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7626.713626                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567520                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004600                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007022                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.116374                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300560                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996076                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          380                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61851                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          379                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          530                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2690                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5173                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53395                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.005798                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.943771                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        410382726                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       410382726                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       788948                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       299798                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1088746                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7549082                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7549082                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9455                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9455                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   265.508156                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   348.644093                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6890.433367                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.546517                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004051                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005320                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.105140                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.335649                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996677                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          240                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63093                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          240                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2664                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5217                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003662                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962723                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        506469360                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       506469360                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1313351                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       329734                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1643085                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks     10299062                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total     10299062                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        12887                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        12887                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1576072                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1576072                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14958434                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14958434                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6296354                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6296354                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       732370                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       732370                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       788948                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       299798                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14958434                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7872426                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        23919606                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       788948                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       299798                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14958434                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7872426                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23919606                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3175                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         2963                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6138                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34552                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34552                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1723701                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1723701                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     16658716                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     16658716                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      8894179                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      8894179                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       672751                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       672751                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker      1313351                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       329734                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     16658716                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     10617880                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        28919681                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker      1313351                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       329734                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     16658716                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data     10617880                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       28919681                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker        10281                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         8711                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        18992                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data        47777                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        47777                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       407912                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       407912                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        84184                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        84184                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       253746                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       253746                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       492598                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       492598                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         3175                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         2963                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        84184                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       661658                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        751980                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         3175                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         2963                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        84184                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       661658                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       751980                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    276956000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    265379500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    542335500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    544075000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total    544075000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data      1312732                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total      1312732                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        98354                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        98354                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       420801                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       420801                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       590547                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       590547                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker        10281                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         8711                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        98354                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1733533                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1850879                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker        10281                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         8711                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        98354                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1733533                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1850879                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    914040000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    769017500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1683057500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    621639500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total    621639500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  36032836500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  36032836500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   7082572500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   7082572500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  22536354000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  22536354000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  51203919000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total  51203919000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    276956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    265379500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   7082572500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  58569190500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  66194098500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    276956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    265379500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   7082572500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  58569190500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  66194098500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       792123                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       302761                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1094884                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      7549082                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      7549082                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        44007                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        44007                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 120138160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 120138160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8298337000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   8298337000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  37547469500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  37547469500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  62416970000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total  62416970000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    914040000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    769017500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   8298337000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 157685629500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 167667024000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    914040000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    769017500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   8298337000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 157685629500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 167667024000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker      1323632                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       338445                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1662077                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks     10299062                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total     10299062                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        60664                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        60664                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            7                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            7                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1983984                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1983984                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15042618                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     15042618                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6550100                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6550100                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224968                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1224968                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       792123                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       302761                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     15042618                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      8534084                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     24671586                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       792123                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       302761                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     15042618                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8534084                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     24671586                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.009787                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.005606                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.785148                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.785148                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      3036433                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      3036433                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     16757070                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     16757070                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      9314980                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      9314980                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1263298                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1263298                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker      1323632                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       338445                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     16757070                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     12351413                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     30770560                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker      1323632                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       338445                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     16757070                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     12351413                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     30770560                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007767                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.025738                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.011427                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787568                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787568                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.205602                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.205602                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005596                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005596                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038739                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038739                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402131                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402131                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.009787                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005596                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.077531                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.030480                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004008                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.009787                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005596                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.077531                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.030480                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.432327                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.432327                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005869                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005869                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.045175                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.045175                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.467465                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.467465                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.025738                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005869                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.140351                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060151                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.007767                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.025738                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005869                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.140351                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060151                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88905.748468                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88281.196189                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 88619.287068                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13011.271114                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13011.271114                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91517.659355                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91517.659355                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84372.135348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84372.135348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89228.565284                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89228.565284                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 105693.484177                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 105693.484177                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88905.748468                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88281.196189                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84372.135348                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90962.000435                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 90587.782346                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88905.748468                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88281.196189                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84372.135348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90962.000435                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 90587.782346                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1368,194 +1362,194 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       967181                       # number of writebacks
-system.cpu.l2cache.writebacks::total           967181                       # number of writebacks
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3175                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2963                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6138                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1073                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1073                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34552                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34552                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      2075008                       # number of writebacks
+system.cpu.l2cache.writebacks::total          2075008                       # number of writebacks
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        10281                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         8711                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        18992                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1261                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1261                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        47777                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        47777                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       407912                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       407912                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        84184                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        84184                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       253725                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       253725                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       492598                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       492598                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3175                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2963                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        84184                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       661637                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       751959                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3175                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2963                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        84184                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       661637                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       751959                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1312732                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total      1312732                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        98354                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        98354                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       420779                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       420779                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       590547                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       590547                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        10281                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         8711                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        98354                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1733511                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1850857                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker        10281                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         8711                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        98354                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1733511                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1850857                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54973                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54987                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88669                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    235749500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    480955500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    717374500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    717374500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88690                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    811230000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    681907500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1493137500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    993052500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    993052500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       161500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       161500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31953716500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31953716500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   6240732500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   6240732500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  19997854000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  19997854000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  46277939000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  46277939000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    235749500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   6240732500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  51951570500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  58673258500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    245206000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    235749500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   6240732500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  51951570500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  58673258500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107010840000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107010840000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7314797000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7314797000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33338388000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33338388000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  56511500000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  56511500000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    811230000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    681907500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7314797000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140349228000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 149157162500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    811230000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    681907500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7314797000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140349228000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 149157162500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5407344500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6735569000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5315951000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5315951000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5407939500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6736164000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5316157000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5316157000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1328224500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10723295500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12051520000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10724096500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12052321000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007767                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.025738                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.011427                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785148                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785148                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787568                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787568                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.205602                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.205602                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005596                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038736                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038736                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402131                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402131                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030479                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004008                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009787                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005596                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077529                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030479                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.432327                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.432327                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005869                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005869                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.045172                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.045172                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.467465                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.467465                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007767                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.025738                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005869                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.140349                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060150                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007767                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.025738                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005869                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.140349                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060150                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        1633565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23227278                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8622904                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     17438576                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        44010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2244083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      28317103                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback     12480720                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict     20347986                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        60667                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        44017                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1983984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1983984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15042826                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6558947                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1331632                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1224968                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45167572                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29499463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       732865                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1940611                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          77340511                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    963068272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1029563294                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2422088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6336984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2001390638                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1864369                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     52693428                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.056141                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.230194                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        60674                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      3036433                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      3036433                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     16757275                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      9323830                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1369962                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1263298                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50310988                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     41099763                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       807461                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3043712                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          95261924                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1072793136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1449869810                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2707560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10589056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2535959562                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     3104722                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     65657900                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.072586                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.259455                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           49735173     94.39%     94.39% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            2958255      5.61%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           60892075     92.74%     92.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            4765825      7.26%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       52693428                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    33222815494                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       65657900                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    41856500497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1182000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1150500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22592032956                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   25164199957                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13487423434                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   19241199390                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     430634727                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     469526277                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1148958035                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1720822991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1574,11 +1568,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1595,11 +1589,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1628,71 +1622,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           568813596                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568892559                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115455                       # number of replacements
-system.iocache.tags.tagsinuse               10.423947                       # Cycle average of tags in use
+system.iocache.tags.replacements               115458                       # number of replacements
+system.iocache.tags.tagsinuse               10.449705                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13095311635000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544418                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.879529                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221526                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429971                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651497                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13095311633000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.528028                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.921676                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.220502                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.432605                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653107                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039623                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039650                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8810                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8847                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8810                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8850                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8810                       # number of overall misses
-system.iocache.overall_misses::total             8850                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
+system.iocache.overall_misses::total             8853                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1621911166                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1626980166                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1615020135                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1620089135                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12610487430                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12610487430                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12610143424                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12610143424                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1621911166                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1627331166                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1615020135                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1620440135                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1621911166                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1627331166                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1615020135                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1620440135                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8810                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8847                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8810                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8850                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8810                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8850                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1707,54 +1701,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183901.906409                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183060.919209                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183879.227797                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 183254.298763                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183038.533266                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 184098.883768                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183879.227797                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31681                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 183254.298763                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183038.533266                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31319                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3345                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3376                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.471151                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.276955                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8810                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8810                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8850                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8810                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8850                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1181411166                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1184630166                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1174370135                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1177589135                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7277287430                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7277287430                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7276943424                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7276943424                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1181411166                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1184831166                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1174370135                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1177790135                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1181411166                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1184831166                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1174370135                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1177790135                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1769,72 +1763,72 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 133038.533266                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133879.227797                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 133038.533266                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54973                       # Transaction distribution
-system.membus.trans_dist::ReadResp             407867                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::Writeback           1073811                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           187846                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35358                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54987                       # Transaction distribution
+system.membus.trans_dist::ReadResp             601962                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33703                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33703                       # Transaction distribution
+system.membus.trans_dist::Writeback           2181638                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           277040                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            48552                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           35361                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            899707                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           899707                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        352894                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           48555                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1902507                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1902507                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        546975                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3753956                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3883578                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341714                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4225292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      7371150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      7500814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341657                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341657                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7842471                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    141818700                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    141988686                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7244096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7244096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               149232782                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2955                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2747442                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    289319820                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    289489890                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7242112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7242112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               296732002                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2989                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5154600                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2747442    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5154600    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2747442                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           104159500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5154600                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           104456000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5443500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5495500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7279924206                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         14230820482                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6776038462                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        13100845399                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228860056                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228852771                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1845,11 +1839,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -1878,17 +1872,17 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16150                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    20008                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
index cc1edf626..160a8ac7f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -322,7 +322,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -761,9 +761,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
index 1d5cc7d19..96cb18ee3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
@@ -6,7 +6,7 @@
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "highest_el_is_64": false, 
-        "kernel": "/work/gem5/dist/binaries/vmlinux.aarch64.20140821", 
+        "kernel": "/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821", 
         "iobus": {
             "slave": {
                 "peer": [
@@ -68,7 +68,7 @@
             "frontend_latency": 2
         }, 
         "symbolfile": "", 
-        "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", 
+        "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", 
         "have_large_asid_64": false, 
         "phys_addr_range_64": 40, 
         "have_lpae": false, 
@@ -87,7 +87,7 @@
         "multi_proc": true, 
         "early_kernel_symbols": false, 
         "panic_on_oops": true, 
-        "dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb", 
+        "dtb_filename": "/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb", 
         "enable_context_switch_stats_dump": false, 
         "work_begin_ckpt_count": 0, 
         "clk_domain": {
@@ -108,30 +108,33 @@
         ], 
         "realview": {
             "hdlcd": {
-                "dma": {
-                    "peer": "system.membus.slave[0]", 
-                    "role": "MASTER"
-                }, 
-                "pixel_clock": 7299, 
                 "vnc": "system.vncserver", 
+                "pxl_clk": "system.realview.realview_io.osc_pxl", 
                 "name": "hdlcd", 
+                "workaround_dma_line_count": true, 
+                "amba_id": 1314816, 
                 "pio": {
                     "peer": "system.iobus.master[5]", 
                     "role": "SLAVE"
                 }, 
-                "amba_id": 1314816, 
                 "pio_latency": 10000, 
                 "clk_domain": "system.clk_domain", 
                 "system": "system", 
                 "gic": "system.realview.gic", 
                 "int_num": 117, 
                 "eventq_index": 0, 
+                "pixel_buffer_size": 2048, 
                 "cxx_class": "HDLcd", 
                 "enable_capture": true, 
                 "path": "system.realview.hdlcd", 
                 "pio_addr": 721420288, 
                 "workaround_swap_rb": true, 
-                "type": "HDLcd"
+                "type": "HDLcd", 
+                "pixel_chunk": 32, 
+                "dma": {
+                    "peer": "system.membus.slave[0]", 
+                    "role": "MASTER"
+                }
             }, 
             "mmc_fake": {
                 "name": "mmc_fake", 
@@ -893,7 +896,7 @@
                 "MSIXCAPNextCapability": 0, 
                 "PXCAPLinkCtrl": 0, 
                 "Revision": 0, 
-                "hardware_address": "<m5.params.EthernetAddr object at 0x7fd02360a190>", 
+                "hardware_address": "<m5.params.EthernetAddr object at 0x511b690>", 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
                 "platform": "system.realview", 
@@ -1176,7 +1179,7 @@
             "clk_domain": "system.clk_domain", 
             "write_buffers": 8, 
             "response_latency": 50, 
-            "cxx_class": "BaseCache", 
+            "cxx_class": "Cache", 
             "size": 1024, 
             "tags": {
                 "name": "tags", 
@@ -1210,7 +1213,7 @@
             "prefetch_on_access": false, 
             "path": "system.iocache", 
             "name": "iocache", 
-            "type": "BaseCache", 
+            "type": "Cache", 
             "sequential_access": false, 
             "assoc": 8
         }, 
@@ -1416,7 +1419,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 32768, 
                     "tags": {
                         "name": "tags", 
@@ -1450,7 +1453,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu.icache", 
                     "name": "icache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 1
                 }, 
@@ -1505,7 +1508,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 20, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 4194304, 
                     "tags": {
                         "name": "tags", 
@@ -1539,7 +1542,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu.l2cache", 
                     "name": "l2cache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 8
                 }, 
@@ -1586,7 +1589,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 32768, 
                     "tags": {
                         "name": "tags", 
@@ -1620,7 +1623,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu.dcache", 
                     "name": "dcache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 4
                 }, 
@@ -1701,7 +1704,7 @@
                     "eventq_index": 0, 
                     "cxx_class": "RawDiskImage", 
                     "path": "system.cf0.image.child", 
-                    "image_file": "/work/gem5/dist/disks/linaro-minimal-aarch64.img", 
+                    "image_file": "/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img", 
                     "type": "RawDiskImage"
                 }, 
                 "path": "system.cf0.image", 
@@ -1741,7 +1744,7 @@
             "system.realview.vram"
         ], 
         "work_begin_cpu_id_exit": -1, 
-        "boot_loader": "/work/gem5/dist/binaries/boot_emm.arm64", 
+        "boot_loader": "/scratch/nilay/GEM5/system/binaries/boot_emm.arm64", 
         "num_work_ids": 16
     }, 
     "time_sync_period": 100000000000, 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index 35e369985..3b35220e8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1040961                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1223300                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            54038486240                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 670940                       # Number of bytes of host memory used
-host_seconds                                   945.83                       # Real time elapsed on the host
+host_inst_rate                                 926984                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1089358                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48121696814                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 716268                       # Number of bytes of host memory used
+host_seconds                                  1062.12                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -210,7 +210,7 @@ system.cpu.itb.inst_accesses                985174158                       # IT
 system.cpu.itb.hits                         985047321                       # DTB hits
 system.cpu.itb.misses                          126837                       # DTB misses
 system.cpu.itb.accesses                     985174158                       # DTB accesses
-system.cpu.numCycles                     102222322140                       # number of cpu cycles simulated
+system.cpu.numCycles                     102222325018                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   984570519                       # Number of instructions committed
@@ -230,8 +230,8 @@ system.cpu.num_cc_register_writes           263829403                       # nu
 system.cpu.num_mem_refs                     352465606                       # number of memory refs
 system.cpu.num_load_insts                   184180431                       # Number of load instructions
 system.cpu.num_store_insts                  168285175                       # Number of store instructions
-system.cpu.num_idle_cycles               101064643603.520065                       # Number of idle cycles
-system.cpu.num_busy_cycles               1157678536.479939                       # Number of busy cycles
+system.cpu.num_idle_cycles               101064646448.926407                       # Number of idle cycles
+system.cpu.num_busy_cycles               1157678569.073592                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.011325                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.988675                       # Percentage of idle cycles
 system.cpu.Branches                         220088562                       # Number of branches fetched
@@ -271,7 +271,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1157666593                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    19653                       # number of quiesce instructions executed
 system.cpu.dcache.tags.replacements          11612141                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           340776008                       # Total number of references to valid blocks.
@@ -787,13 +787,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 0ef1481b3..51a633a32 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -212,7 +212,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -322,7 +322,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -440,7 +440,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -516,7 +516,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[3]
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -626,7 +626,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -739,7 +739,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -774,7 +774,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1125,9 +1125,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 34d0b7d0d..f07b9fa73 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.216814                       # Nu
 sim_ticks                                47216814145000                       # Number of ticks simulated
 final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 990548                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1165292                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            47947296122                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 681164                       # Number of bytes of host memory used
-host_seconds                                   984.77                       # Real time elapsed on the host
+host_inst_rate                                 873779                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1027923                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            42295108650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 724108                       # Number of bytes of host memory used
+host_seconds                                  1116.37                       # Real time elapsed on the host
 sim_insts                                   975457230                       # Number of instructions simulated
 sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -241,7 +241,7 @@ system.cpu0.itb.inst_accesses               497757770                       # IT
 system.cpu0.itb.hits                        497696393                       # DTB hits
 system.cpu0.itb.misses                          61377                       # DTB misses
 system.cpu0.itb.accesses                    497757770                       # DTB accesses
-system.cpu0.numCycles                     94433641544                       # number of cpu cycles simulated
+system.cpu0.numCycles                     94433643486                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.committedInsts                  497466384                       # Number of instructions committed
@@ -261,8 +261,8 @@ system.cpu0.num_cc_register_writes          133531045                       # nu
 system.cpu0.num_mem_refs                    178459396                       # number of memory refs
 system.cpu0.num_load_insts                   92737001                       # Number of load instructions
 system.cpu0.num_store_insts                  85722395                       # Number of store instructions
-system.cpu0.num_idle_cycles              93848337191.325058                       # Number of idle cycles
-system.cpu0.num_busy_cycles              585304352.674931                       # Number of busy cycles
+system.cpu0.num_idle_cycles              93848339121.288452                       # Number of idle cycles
+system.cpu0.num_busy_cycles              585304364.711543                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.006198                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.993802                       # Percentage of idle cycles
 system.cpu0.Branches                        111287587                       # Number of branches fetched
@@ -302,7 +302,7 @@ system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                 585300003                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13253                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   15195                       # number of quiesce instructions executed
 system.cpu0.dcache.tags.replacements          6272773                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          500.885315                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs          172015769                       # Total number of references to valid blocks.
@@ -767,7 +767,7 @@ system.cpu1.itb.inst_accesses               478309003                       # IT
 system.cpu1.itb.hits                        478248118                       # DTB hits
 system.cpu1.itb.misses                          60885                       # DTB misses
 system.cpu1.itb.accesses                    478309003                       # DTB accesses
-system.cpu1.numCycles                     94433634550                       # number of cpu cycles simulated
+system.cpu1.numCycles                     94433635490                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                  477990846                       # Number of instructions committed
@@ -787,8 +787,8 @@ system.cpu1.num_cc_register_writes          126112608                       # nu
 system.cpu1.num_mem_refs                    171406825                       # number of memory refs
 system.cpu1.num_load_insts                   90251973                       # Number of load instructions
 system.cpu1.num_store_insts                  81154852                       # Number of store instructions
-system.cpu1.num_idle_cycles              93870750285.000458                       # Number of idle cycles
-system.cpu1.num_busy_cycles              562884264.999552                       # Number of busy cycles
+system.cpu1.num_idle_cycles              93870751219.397461                       # Number of idle cycles
+system.cpu1.num_busy_cycles              562884270.602548                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.005961                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.994039                       # Percentage of idle cycles
 system.cpu1.Branches                        106497601                       # Number of branches fetched
@@ -828,7 +828,7 @@ system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                 562879339                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    6259                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    7199                       # number of quiesce instructions executed
 system.cpu1.dcache.tags.replacements          5945049                       # number of replacements
 system.cpu1.dcache.tags.tagsinuse          438.290639                       # Cycle average of tags in use
 system.cpu1.dcache.tags.total_refs          165346662                       # Total number of references to valid blocks.
@@ -1551,13 +1551,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
index cc1edf626..160a8ac7f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -322,7 +322,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -761,9 +761,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
index 343cfe408..31e7c1fe5 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 11:06:10
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 03:06:20
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 51111152682000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index 5d4303b7e..47d983423 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1034678                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1215917                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            53712340974                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 668604                       # Number of bytes of host memory used
-host_seconds                                   951.57                       # Real time elapsed on the host
+host_inst_rate                                 921297                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1082675                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            47826467843                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 712064                       # Number of bytes of host memory used
+host_seconds                                  1068.68                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -210,7 +210,7 @@ system.cpu.itb.inst_accesses                985174158                       # IT
 system.cpu.itb.hits                         985047321                       # DTB hits
 system.cpu.itb.misses                          126837                       # DTB misses
 system.cpu.itb.accesses                     985174158                       # DTB accesses
-system.cpu.numCycles                     102222322140                       # number of cpu cycles simulated
+system.cpu.numCycles                     102222325018                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   984570519                       # Number of instructions committed
@@ -230,8 +230,8 @@ system.cpu.num_cc_register_writes           263829403                       # nu
 system.cpu.num_mem_refs                     352465606                       # number of memory refs
 system.cpu.num_load_insts                   184180431                       # Number of load instructions
 system.cpu.num_store_insts                  168285175                       # Number of store instructions
-system.cpu.num_idle_cycles               101064643603.520065                       # Number of idle cycles
-system.cpu.num_busy_cycles               1157678536.479939                       # Number of busy cycles
+system.cpu.num_idle_cycles               101064646448.926407                       # Number of idle cycles
+system.cpu.num_busy_cycles               1157678569.073592                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.011325                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.988675                       # Percentage of idle cycles
 system.cpu.Branches                         220088562                       # Number of branches fetched
@@ -271,7 +271,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1157666593                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    19653                       # number of quiesce instructions executed
 system.cpu.dcache.tags.replacements          11612141                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           340776008                       # Total number of references to valid blocks.
@@ -787,13 +787,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 11e85042f..351e6eb6d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -208,7 +208,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -318,7 +318,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -432,7 +432,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -508,7 +508,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[3]
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -618,7 +618,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -731,7 +731,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -766,7 +766,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1181,9 +1181,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
index 76a99086b..2db4f0fce 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 11:24:22
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 02:37:28
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 47456679626500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 11d99eddf..05fb68c75 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.456680                       # Nu
 sim_ticks                                47456679626500                       # Number of ticks simulated
 final_tick                               47456679626500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 617984                       # Simulator instruction rate (inst/s)
-host_op_rate                                   726985                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            33898978760                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 711884                       # Number of bytes of host memory used
-host_seconds                                  1399.94                       # Real time elapsed on the host
+host_inst_rate                                 503190                       # Simulator instruction rate (inst/s)
+host_op_rate                                   591944                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27602071667                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 755208                       # Number of bytes of host memory used
+host_seconds                                  1719.32                       # Real time elapsed on the host
 sim_insts                                   865142471                       # Number of instructions simulated
 sim_ops                                    1017738631                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -625,7 +625,7 @@ system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                 502778486                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   14022                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   15090                       # number of quiesce instructions executed
 system.cpu0.dcache.tags.replacements          5233253                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          480.798924                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs          147607157                       # Total number of references to valid blocks.
@@ -1613,7 +1613,7 @@ system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                 515545598                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5256                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    7070                       # number of quiesce instructions executed
 system.cpu1.dcache.tags.replacements          5176711                       # number of replacements
 system.cpu1.dcache.tags.tagsinuse          457.282743                       # Cycle average of tags in use
 system.cpu1.dcache.tags.total_refs          152806636                       # Total number of references to valid blocks.
@@ -3222,13 +3222,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
index b1ceb0f38..aef164157 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -208,7 +208,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -318,7 +318,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -406,7 +406,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -821,9 +821,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
index 608cdb063..602235712 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
@@ -1,16 +1,18 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  7 2015 10:13:08
-gem5 started Aug  7 2015 11:22:13
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 00:24:53
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 51832458543500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 829b00030..f9e8bd96f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.832459                       # Nu
 sim_ticks                                51832458543500                       # Number of ticks simulated
 final_tick                               51832458543500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 643815                       # Simulator instruction rate (inst/s)
-host_op_rate                                   756535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            37796716864                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 668604                       # Number of bytes of host memory used
-host_seconds                                  1371.35                       # Real time elapsed on the host
+host_inst_rate                                 536175                       # Simulator instruction rate (inst/s)
+host_op_rate                                   630049                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31477440084                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 712068                       # Number of bytes of host memory used
+host_seconds                                  1646.65                       # Real time elapsed on the host
 sim_insts                                   882895003                       # Number of instructions simulated
 sim_ops                                    1037473525                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -584,7 +584,7 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1038060895                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16280                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    19158                       # number of quiesce instructions executed
 system.cpu.dcache.tags.replacements          10067650                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.966034                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           306351638                       # Total number of references to valid blocks.
@@ -1588,13 +1588,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
index ab5c7b693..140fedafe 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -511,7 +511,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -546,7 +546,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -897,9 +897,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index bd6e6276d..25d466362 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1034928                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1216210                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            53725315382                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 668860                       # Number of bytes of host memory used
-host_seconds                                   951.34                       # Real time elapsed on the host
+host_inst_rate                                 916811                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1077403                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            47593586653                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 712068                       # Number of bytes of host memory used
+host_seconds                                  1073.91                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -228,7 +228,7 @@ system.cpu0.itb.inst_accesses               493628912                       # IT
 system.cpu0.itb.hits                        493558289                       # DTB hits
 system.cpu0.itb.misses                          70623                       # DTB misses
 system.cpu0.itb.accesses                    493628912                       # DTB accesses
-system.cpu0.numCycles                     98036732821                       # number of cpu cycles simulated
+system.cpu0.numCycles                     98036734134                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.committedInsts                  493343054                       # Number of instructions committed
@@ -248,8 +248,8 @@ system.cpu0.num_cc_register_writes          132723498                       # nu
 system.cpu0.num_mem_refs                    176296730                       # number of memory refs
 system.cpu0.num_load_insts                   91967123                       # Number of load instructions
 system.cpu0.num_store_insts                  84329607                       # Number of store instructions
-system.cpu0.num_idle_cycles              96926191341.047134                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1110541479.952863                       # Number of busy cycles
+system.cpu0.num_idle_cycles              96926192639.173721                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1110541494.826277                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.011328                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.988672                       # Percentage of idle cycles
 system.cpu0.Branches                        110281342                       # Number of branches fetched
@@ -289,7 +289,7 @@ system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                 579643698                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16775                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   19653                       # number of quiesce instructions executed
 system.cpu0.dcache.tags.replacements         11612141                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.999719                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs          340775537                       # Total number of references to valid blocks.
@@ -612,7 +612,7 @@ system.cpu1.itb.inst_accesses               491545246                       # IT
 system.cpu1.itb.hits                        491475383                       # DTB hits
 system.cpu1.itb.misses                          69863                       # DTB misses
 system.cpu1.itb.accesses                    491545246                       # DTB accesses
-system.cpu1.numCycles                     97463064529                       # number of cpu cycles simulated
+system.cpu1.numCycles                     97463066094                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                  491227465                       # Number of instructions committed
@@ -632,8 +632,8 @@ system.cpu1.num_cc_register_writes          131105905                       # nu
 system.cpu1.num_mem_refs                    176168876                       # number of memory refs
 system.cpu1.num_load_insts                   92213308                       # Number of load instructions
 system.cpu1.num_store_insts                  83955568                       # Number of store instructions
-system.cpu1.num_idle_cycles              96357044010.669601                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1106020518.330400                       # Number of busy cycles
+system.cpu1.num_idle_cycles              96357045557.909821                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1106020536.090176                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.011348                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.988652                       # Percentage of idle cycles
 system.cpu1.Branches                        109807220                       # Number of branches fetched
@@ -1080,13 +1080,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
index 92fcc1d90..fed55ceb4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1610,7 +1610,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1645,7 +1645,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -2060,9 +2060,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
index d502db8d0..4873ce7b9 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
@@ -23,8 +23,6 @@ warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11735, Bank: 6
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -41,28 +39,16 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8760, Bank: 1
-WARNING: Bank is not active!
-Command: 1, Timestamp: 5113, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8082, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10604, Bank: 7
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9156, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -75,14 +61,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -125,6 +109,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -149,14 +135,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -165,8 +149,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -175,10 +157,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -199,6 +181,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -209,10 +193,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7012, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10303, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -229,22 +209,28 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6518, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12331, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9979, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8446, Bank: 6
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10805, Bank: 3
+Command: 0, Timestamp: 6448, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10161, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11757, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -261,6 +247,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6479, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 6
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -273,12 +269,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7980, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -291,32 +289,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11719, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10011, Bank: 1
+Command: 0, Timestamp: 7906, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11449, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -335,18 +323,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6626, Bank: 3
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -369,28 +349,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9676, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10242, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10403, Bank: 7
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11427, Bank: 7
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -413,8 +387,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9256, Bank: 6
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -423,28 +395,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9641, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -453,10 +415,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -477,10 +435,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -493,24 +449,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6826, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7179, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8996, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11485, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -523,10 +471,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -535,20 +491,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10203, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -573,6 +531,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -593,12 +555,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -611,8 +567,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -633,8 +587,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8213, Bank: 7
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -643,6 +603,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -651,6 +615,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -667,10 +635,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -681,10 +657,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -705,10 +677,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6550, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -719,8 +689,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7188, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -729,12 +699,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7000, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -751,18 +729,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -779,8 +759,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10397, Bank: 4
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -799,16 +789,24 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7532, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7045, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -827,10 +825,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7487, Bank: 6
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -845,10 +839,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -861,10 +851,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -873,8 +859,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -891,14 +875,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10743, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -907,6 +891,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -923,14 +909,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -939,10 +917,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -961,18 +947,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -995,10 +973,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1007,10 +981,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9050, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11416, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8249, Bank: 1
 WARNING: Bank is already active!
-Command: 0, Timestamp: 11000, Bank: 4
+Command: 0, Timestamp: 9760, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1027,14 +1009,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1043,10 +1017,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1071,20 +1041,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1095,6 +1067,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1125,14 +1099,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7339, Bank: 7
+Command: 0, Timestamp: 7036, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1149,10 +1117,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12368, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1165,24 +1129,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7706, Bank: 7
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1217,6 +1175,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1232,15 +1198,23 @@ warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7794, Bank: 5
+Command: 0, Timestamp: 8714, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10622, Bank: 2
+Command: 0, Timestamp: 7453, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 8145, Bank: 1
+Command: 0, Timestamp: 6792, Bank: 5
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 7
+Command: 0, Timestamp: 10152, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1261,16 +1235,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11476, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1281,16 +1255,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1305,6 +1277,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9430, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1321,10 +1295,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1345,6 +1315,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1365,8 +1339,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10803, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index 5a4eed10a..17066f3b8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,192 +1,192 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.316635                       # Number of seconds simulated
-sim_ticks                                51316634750000                       # Number of ticks simulated
-final_tick                               51316634750000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.276903                       # Number of seconds simulated
+sim_ticks                                51276903265000                       # Number of ticks simulated
+final_tick                               51276903265000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 261197                       # Simulator instruction rate (inst/s)
-host_op_rate                                   306920                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15666770859                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 680896                       # Number of bytes of host memory used
-host_seconds                                  3275.51                       # Real time elapsed on the host
-sim_insts                                   855554018                       # Number of instructions simulated
-sim_ops                                    1005318688                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 195122                       # Simulator instruction rate (inst/s)
+host_op_rate                                   229284                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            11700811305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 723460                       # Number of bytes of host memory used
+host_seconds                                  4382.34                       # Real time elapsed on the host
+sim_insts                                   855091424                       # Number of instructions simulated
+sim_ops                                    1004800608                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        86272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        87040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2475252                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         44191944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        26688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        26112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           701824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          6588352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        27264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        23232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          1769600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          8688000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker        64576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker        58944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst          1797376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data         16165440                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        417344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             83195260                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2475252                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       701824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      1769600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst      1797376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6744052                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     70299712                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        83904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        91648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2486836                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         43860424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        20800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        20224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           650944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          6302784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        33152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        28032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          1597440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          8824832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker        64832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker        59456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst          1836416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data         15839168                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        414400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             82215292                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2486836                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       650944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      1597440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst      1836416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6571636                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69835456                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70320292                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1348                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1360                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             79083                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            690512                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          417                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          408                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10966                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            102943                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker          426                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker          363                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             27650                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            135750                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker         1009                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker          921                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst             28084                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data            252585                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6521                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1340346                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1098433                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69856036                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1311                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1432                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             79264                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            685332                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          316                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             98481                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker          518                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker          438                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             24960                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            137888                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker         1013                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker          929                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst             28694                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data            247487                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6475                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1325034                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1091179                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1101006                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1696                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               48235                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              861162                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           520                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           509                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               13676                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              128386                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           531                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker           453                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               34484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              169302                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1258                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker          1149                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst               35025                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data              315014                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8133                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1621214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          48235                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          13676                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          34484                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst          35025                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             131420                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1369921                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1093752                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1636                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1787                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               48498                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              855364                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           394                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               12695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              122917                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           647                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker           547                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               31153                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              172102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker          1160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst               35814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data              308895                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1603359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          48498                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          12695                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          31153                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst          35814                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             128160                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1361928                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1370322                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1369921                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1696                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              48235                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             861563                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          520                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              13676                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             128386                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          531                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker          453                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              34484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             169302                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1258                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker         1149                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst              35025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data             315014                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8133                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2991536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        565119                       # Number of read requests accepted
-system.physmem.writeReqs                       485303                       # Number of write requests accepted
-system.physmem.readBursts                      565119                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     485303                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 36124864                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     42752                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  31057472                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  36167616                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               31059392                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      668                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          65964                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               37092                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               38221                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               34232                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               34199                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               32555                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               36931                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               31211                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               33972                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               32403                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               38255                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              35917                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              41761                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              35252                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              36878                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              32220                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              33352                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               29650                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               31742                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               28889                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               30829                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               29399                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               32279                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               27374                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               30609                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               28675                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               32426                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              29991                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              34263                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              30290                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              31646                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              28165                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              29046                       # Per bank write bursts
+system.physmem.bw_write::total                1362329                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1361928                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1636                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1787                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              48498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             855765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          406                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              12695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             122917                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker          547                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              31153                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             172102                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker         1160                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst              35814                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data             308895                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2965689                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        552891                       # Number of read requests accepted
+system.physmem.writeReqs                       477788                       # Number of write requests accepted
+system.physmem.readBursts                      552891                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     477788                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 35353984                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     31040                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  30577024                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  35385024                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               30578432                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      485                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       2                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          65706                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               34049                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               38611                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               36089                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               33688                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               32444                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               38213                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               33143                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               35180                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               30999                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               38487                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              32534                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              34124                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              34391                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              36689                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              30748                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              33017                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               28228                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               31813                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               30334                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               30276                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               29074                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               32329                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               29378                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               31367                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               28134                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               32950                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              28173                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              29809                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              29393                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              31102                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              26687                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              28719                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51315634470500                       # Total gap between requests
+system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51275902957500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  565119                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  552891                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 485303                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    399408                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    101730                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     37111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23215                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       366                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       310                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       421                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       535                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      237                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       87                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       82                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       69                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       46                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 477788                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    390834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    101245                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     36261                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     22580                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       241                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       135                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       154                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       255                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      116                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -198,188 +198,189 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       570                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                       568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       567                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                       563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     7847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     8616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    19482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    23454                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    26479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    28098                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    28044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    29307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    29679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    31078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    30832                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    30867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    29853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    30684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    32884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    28794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    28945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    27599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        6                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       278814                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      240.955476                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     145.236301                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     282.316846                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         127586     45.76%     45.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        69517     24.93%     70.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        25415      9.12%     79.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        12865      4.61%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         9508      3.41%     87.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         5843      2.10%     89.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4935      1.77%     91.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3869      1.39%     93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19276      6.91%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         278814                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         27347                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.639193                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       13.469110                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-31            24770     90.58%     90.58% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-63            2374      8.68%     99.26% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-95             169      0.62%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-127             20      0.07%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-159             3      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::160-191             2      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::192-223             2      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::224-255             2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::8                       560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      558                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     7763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     8554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    19132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    23245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    26278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    27645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    27593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    28722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    29357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    30518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    30179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    30394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    29233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    29969                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    32125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    28250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    28349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    27090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       274210                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      240.439605                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     144.938897                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     282.109659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         125716     45.85%     45.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        68438     24.96%     70.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        25021      9.12%     79.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        12508      4.56%     84.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         9258      3.38%     87.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         5639      2.06%     89.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4828      1.76%     91.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3908      1.43%     93.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        18894      6.89%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         274210                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         26911                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.526067                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       11.794562                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-31            24375     90.58%     90.58% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-63            2332      8.67%     99.24% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-95             174      0.65%     99.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-127             18      0.07%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-159             4      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::160-191             2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::192-223             2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::224-255             1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::256-287             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::320-351             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::704-735             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::736-767             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::928-959             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           27347                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         27347                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.745018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.170209                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.144032                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                15      0.05%      0.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                12      0.04%      0.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                8      0.03%      0.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              33      0.12%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           25607     93.64%     93.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             450      1.65%     95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             306      1.12%     96.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             171      0.63%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             124      0.45%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             194      0.71%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              52      0.19%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.04%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              30      0.11%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              23      0.08%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              22      0.08%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              11      0.04%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             180      0.66%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              15      0.05%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              25      0.09%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              19      0.07%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            14      0.05%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           27347                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    11691794846                       # Total ticks spent queuing
-system.physmem.totMemAccLat               22275251096                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2822255000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20713.57                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::544-575             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-799             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           26911                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         26911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.753558                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.172751                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.257743                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                17      0.06%      0.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 9      0.03%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               13      0.05%      0.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              46      0.17%      0.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           25176     93.55%     93.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             431      1.60%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             320      1.19%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             165      0.61%     97.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             117      0.43%     97.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             198      0.74%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              59      0.22%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              19      0.07%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              21      0.08%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              16      0.06%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              22      0.08%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.04%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             188      0.70%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              14      0.05%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              18      0.07%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              10      0.04%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               4      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.05%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           26911                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    11450608424                       # Total ticks spent queuing
+system.physmem.totMemAccLat               21808220924                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2762030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20728.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39463.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.70                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.61                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.70                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.61                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39478.61                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.69                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.69                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     432443                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    338466                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.61                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.74                       # Row buffer hit rate for writes
-system.physmem.avgGap                     48852398.82                       # Average gap between requests
-system.physmem.pageHitRate                      73.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1049600160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  571056750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2171551200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               1560196080                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3312990217680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1178995763115                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29844954866250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34342293251235                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.290653                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48908598729306                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1693757780000                       # Time in different power states
+system.physmem.avgWrQLen                         9.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     422970                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    332991                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.57                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  69.69                       # Row buffer hit rate for writes
+system.physmem.avgGap                     49749633.94                       # Average gap between requests
+system.physmem.pageHitRate                      73.38                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1067305680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  580820625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                2194982400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1573337520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3310526753040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1179597405240                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           30106177853250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34601718457755                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              666.680244                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48870107005920                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1692498340000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    121315217444                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    123346652830                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1058233680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  575746875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                2231096400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               1584372960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3312990217680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1180768405545                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           30633804913500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             35133012986640                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              665.617184                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48905982752444                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1693757780000                       # Time in different power states
+system.physmem_1.actEnergy                 1005699240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  547226625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                2113714200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1522586160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3310526753040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1176042513600                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29757652392000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34249410884865                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.428862                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48875263841452                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1692498340000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    123922534306                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    118168635298                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -439,47 +440,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    91446                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong                91446                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples        91446                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          91446    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        91446                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 388607264328                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.523233                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -203332229172    -52.32%    -52.32% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   591939493500    152.32%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 388607264328                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        66855     84.61%     84.61% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        12161     15.39%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        79016                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        91446                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    90619                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong                90619                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples        90619                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          90619    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        90619                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 391820506288                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.505623                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -198113446712    -50.56%    -50.56% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   589933953000    150.56%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 391820506288                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        66457     84.78%     84.78% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11934     15.22%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        78391                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90619                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        91446                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        79016                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90619                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78391                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        79016                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       170462                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78391                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       169010                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    64637193                       # DTB read hits
-system.cpu0.dtb.read_misses                     69043                       # DTB read misses
-system.cpu0.dtb.write_hits                   58569418                       # DTB write hits
-system.cpu0.dtb.write_misses                    22403                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1193                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    64357240                       # DTB read hits
+system.cpu0.dtb.read_misses                     68494                       # DTB read misses
+system.cpu0.dtb.write_hits                   58282336                       # DTB write hits
+system.cpu0.dtb.write_misses                    22125                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              16284                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    407                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   42446                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              16028                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    418                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   42200                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2875                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  2748                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     7756                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                64706236                       # DTB read accesses
-system.cpu0.dtb.write_accesses               58591821                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     7647                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                64425734                       # DTB read accesses
+system.cpu0.dtb.write_accesses               58304461                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        123206611                       # DTB hits
-system.cpu0.dtb.misses                          91446                       # DTB misses
-system.cpu0.dtb.accesses                    123298057                       # DTB accesses
+system.cpu0.dtb.hits                        122639576                       # DTB hits
+system.cpu0.dtb.misses                          90619                       # DTB misses
+system.cpu0.dtb.accesses                    122730195                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -509,695 +510,695 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    53719                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                53719                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        53719                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          53719    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        53719                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 388607264328                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.523329                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -203369594172    -52.33%    -52.33% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   591976858500    152.33%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 388607264328                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        46750     94.94%     94.94% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2490      5.06%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        49240                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    53743                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                53743                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        53743                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          53743    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        53743                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 391820506288                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.505732                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -198156351712    -50.57%    -50.57% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   589976858000    150.57%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 391820506288                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        46842     94.98%     94.98% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2476      5.02%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        49318                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53719                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53719                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53743                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53743                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49240                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49240                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       102959                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   343542724                       # ITB inst hits
-system.cpu0.itb.inst_misses                     53719                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49318                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49318                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       103061                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   342266306                       # ITB inst hits
+system.cpu0.itb.inst_misses                     53743                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1193                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              16284                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    407                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   30063                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              16028                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    418                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   29888                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               343596443                       # ITB inst accesses
-system.cpu0.itb.hits                        343542724                       # DTB hits
-system.cpu0.itb.misses                          53719                       # DTB misses
-system.cpu0.itb.accesses                    343596443                       # DTB accesses
-system.cpu0.numCycles                       414507923                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               342320049                       # ITB inst accesses
+system.cpu0.itb.hits                        342266306                       # DTB hits
+system.cpu0.itb.misses                          53743                       # DTB misses
+system.cpu0.itb.accesses                    342320049                       # DTB accesses
+system.cpu0.numCycles                       413032183                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  343392928                       # Number of instructions committed
-system.cpu0.committedOps                    403926056                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            371010641                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                350352                       # Number of float alu accesses
-system.cpu0.num_func_calls                   20655596                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     52208909                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   371010641                       # number of integer instructions
-system.cpu0.num_fp_insts                       350352                       # number of float instructions
-system.cpu0.num_int_register_reads          542983655                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         294627893                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              558017                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             311708                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            89970579                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           89777589                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    123282310                       # number of memory refs
-system.cpu0.num_load_insts                   64695790                       # Number of load instructions
-system.cpu0.num_store_insts                  58586520                       # Number of store instructions
-system.cpu0.num_idle_cycles              404635948.136490                       # Number of idle cycles
-system.cpu0.num_busy_cycles              9871974.863510                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023816                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976184                       # Percentage of idle cycles
-system.cpu0.Branches                         76586966                       # Number of branches fetched
+system.cpu0.committedInsts                  342117440                       # Number of instructions committed
+system.cpu0.committedOps                    402438329                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            369654139                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                360090                       # Number of float alu accesses
+system.cpu0.num_func_calls                   20604842                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     52004192                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   369654139                       # number of integer instructions
+system.cpu0.num_fp_insts                       360090                       # number of float instructions
+system.cpu0.num_int_register_reads          540778381                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         293614649                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              575012                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             316800                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads            89609832                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           89403726                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    122714331                       # number of memory refs
+system.cpu0.num_load_insts                   64415463                       # Number of load instructions
+system.cpu0.num_store_insts                  58298868                       # Number of store instructions
+system.cpu0.num_idle_cycles              403076556.915137                       # Number of idle cycles
+system.cpu0.num_busy_cycles              9955626.084863                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024104                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975896                       # Percentage of idle cycles
+system.cpu0.Branches                         76323262                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                279907726     69.26%     69.26% # Class of executed instruction
-system.cpu0.op_class::IntMult                  889275      0.22%     69.48% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    42026      0.01%     69.49% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             46880      0.01%     69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
-system.cpu0.op_class::MemRead                64695790     16.01%     85.50% # Class of executed instruction
-system.cpu0.op_class::MemWrite               58586520     14.50%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                278992555     69.28%     69.28% # Class of executed instruction
+system.cpu0.op_class::IntMult                  883395      0.22%     69.50% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    42520      0.01%     69.51% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             46836      0.01%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::MemRead                64415463     16.00%     85.52% # Class of executed instruction
+system.cpu0.op_class::MemWrite               58298868     14.48%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 404168217                       # Class of executed instruction
+system.cpu0.op_class::total                 402679638                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16558                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          9753179                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999716                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          295582609                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9753691                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.304693                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   19432                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          9760108                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          295125268                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9760620                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.236324                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.786963                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.350548                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.889749                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data     3.972456                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970287                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010450                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011503                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.007759                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   495.144128                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     6.012482                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     7.237282                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data     3.605825                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.967078                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.011743                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.014135                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.007043                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1252278840                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1252278840                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     60369359                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     19140658                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     26830987                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data     45818234                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      152159238                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     55384084                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     17587575                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     23765695                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data     38719665                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     135457019                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       164079                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        46225                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        81077                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data       111985                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       403366                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       132348                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data        44500                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu2.data        54331                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu3.data        98773                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       329952                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1446319                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       438478                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       586341                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       962737                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3433875                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1538701                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       475697                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       636200                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1104802                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3755400                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    115753443                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     36728233                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     50596682                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     84537899                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       287616257                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    115917522                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     36774458                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     50677759                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     84649884                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      288019623                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2092041                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       624638                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       970441                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data      3415331                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7102451                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       840568                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       251537                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       625226                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      3495089                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5212420                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       514907                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       141320                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       198621                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data       334446                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1189294                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       668357                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       105494                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu2.data       155232                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu3.data       298331                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1227414                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        93062                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        37431                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        50097                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       180259                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       360849                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data            4                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2932609                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       876175                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1595667                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      6910420                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      12314871                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3447516                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1017495                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1794288                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      7244866                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     13504165                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9754171500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15346689000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  52027511000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  77128371500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6989966000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  16964216500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  96846252035                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 120800434535                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   2685222500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   4289017000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  10724214307                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  17698453807                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    525769500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    711390500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2241356000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3478516000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       142500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       142500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  16744137500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  32310905500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 148873763035                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 197928806035                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  16744137500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  32310905500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 148873763035                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 197928806035                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     62461400                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     19765296                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data     27801428                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data     49233565                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    159261689                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     56224652                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     17839112                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     24390921                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data     42214754                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    140669439                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       678986                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       187545                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       279698                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       446431                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1592660                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       800705                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       149994                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       209563                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       397104                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1557366                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1539381                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       475909                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       636438                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1142996                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3794724                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1538701                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       475697                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       636200                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1104806                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3755404                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    118686052                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     37604408                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     52192349                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     91448319                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    299931128                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    119365038                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     37791953                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     52472047                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     91894750                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    301523788                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033493                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031603                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.034906                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.069370                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.044596                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014950                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014100                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.025634                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.082793                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.037054                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.758347                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.753526                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.710127                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.749155                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.746734                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.834711                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.703321                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.740741                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.751267                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788135                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060454                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078652                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.078715                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.157707                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095092                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.tags.tag_accesses       1250683612                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1250683612                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     60097226                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     19336059                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data     26622949                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data     45749144                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      151805378                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     55100568                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     17719150                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data     23754745                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data     38783251                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     135357714                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       162930                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        47086                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        80309                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu3.data       113101                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       403426                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       133083                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data        44114                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu2.data        53448                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu3.data        99458                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       330103                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1446448                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       433739                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       576979                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       973119                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3430285                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1540849                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       470550                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data       624581                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1118875                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3754855                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    115197794                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     37055209                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data     50377694                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data     84532395                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       287163092                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    115360724                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     37102295                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data     50458003                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data     84645496                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      287566518                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2087825                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       630392                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       947372                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data      3467801                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7133390                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       834937                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       250601                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       634589                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      3517753                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      5237880                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       509202                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       138531                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       204192                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data       336844                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1188769                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       666802                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       108292                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu2.data       153513                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu3.data       298278                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1226885                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        95086                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        37006                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        47829                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       182134                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       362055                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data            3                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2922762                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       880993                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1581961                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      6985554                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      12371270                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3431964                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1019524                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1786153                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      7322398                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     13560039                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9653717000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15011038000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  51609854500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  76274609500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6907191500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17274882500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  96691175707                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 120873249707                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   2640856500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   4379642000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  10567870242                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  17588368742                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    538982000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    669036000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2261145500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3469163500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       130000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       130000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  16560908500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  32285920500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 148301030207                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 197147859207                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  16560908500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  32285920500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 148301030207                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 197147859207                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     62185051                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     19966451                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data     27570321                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data     49216945                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    158938768                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     55935505                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     17969751                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data     24389334                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data     42301004                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    140595594                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       672132                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       185617                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       284501                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       449945                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1592195                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       799885                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       152406                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       206961                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       397736                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1556988                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1541534                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       470745                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       624808                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1155253                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3792340                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1540849                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       470550                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       624581                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1118878                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3754858                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    118120556                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     37936202                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data     51959655                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     91517949                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    299534362                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    118792688                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     38121819                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data     52244156                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     91967894                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    301126557                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033574                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031573                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.034362                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.070459                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.044881                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014927                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.013946                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.026019                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.083160                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.037255                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.757592                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.746327                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.717720                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.748634                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.746623                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.833622                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.710549                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.741748                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.749940                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.787986                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061683                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078612                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.076550                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.157657                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095470                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024709                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023300                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.030573                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.075566                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.041059                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028882                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.026924                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034195                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.078839                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.044786                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15615.719024                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15814.139139                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15233.519387                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10859.402128                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27789.017123                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27132.935131                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27709.237743                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23175.499007                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25453.793581                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27629.721965                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35947.368215                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14419.302539                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14046.365312                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14200.261493                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12434.086509                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9639.810558                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        35625                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        35625                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19110.494479                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20249.153175                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21543.374069                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16072.340996                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16456.235657                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18007.647323                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20548.863572                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14656.871123                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     12269651                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        11721                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           884921                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            303                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.865250                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    38.683168                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024744                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023223                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.030446                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076330                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.041302                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028890                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.026744                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034189                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.079619                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.045031                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15313.831711                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15844.924697                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14882.588274                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.617325                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27562.505736                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27222.158752                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27486.630161                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23076.750461                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24386.441288                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 28529.453532                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35429.600044                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14335.792468                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14564.719235                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13988.082544                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12414.735854                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9581.868777                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 43333.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 43333.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18798.002368                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20408.796740                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21229.673438                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15935.943457                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16243.765228                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18075.674648                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20253.068763                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14538.885855                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     12171442                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         9970                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           893773                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            243                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.618046                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    41.028807                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7530303                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7530303                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3244                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       107323                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1868973                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      1979540                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         2183                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       273456                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2901507                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3177146                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           23                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2180                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         2203                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8289                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        11291                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       111071                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       130651                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         5427                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       380779                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      4770480                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      5156686                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         5427                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       380779                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      4770480                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      5156686                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       621394                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       863118                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1546358                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3030870                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       249354                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       351770                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       593582                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1194706                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       141097                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       198504                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       329326                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       668927                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       105494                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       155209                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       296151                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       556854                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        29142                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        38806                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        69188                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137136                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       870748                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1214888                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2139940                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4225576                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1011845                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1413392                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2469266                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4894503                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6330                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4869                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         4820                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16019                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         5775                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4397                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         4483                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14655                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        12105                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         9266                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data         9303                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        30674                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9061716000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12702209500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  23634658500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45398584000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6664052500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9037887500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17334765406                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33036705406                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2466765500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2966502500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   5024621000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10457889000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   2579728500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   4133451000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10340882807                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  17054062307                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    376111500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    502612000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    917608500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1796332000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       138500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       138500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  15725768500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  21740097000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  40969423906                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  78435289406                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  18192534000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  24706599500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  45994044906                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  88893178406                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1115432000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    821405500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    838200500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2775038000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1040608000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    744829000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data    810242500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2595679500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2156040000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1566234500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1648443000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5370717500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031439                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031046                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031409                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019031                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013978                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014422                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014061                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008493                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.752337                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.709708                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.737686                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.420006                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.703321                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.740632                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.745777                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.357561                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061234                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.060974                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.060532                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036139                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.writebacks::writebacks      7547308                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7547308                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3607                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       105383                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1896936                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2005926                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         2163                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       278391                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2919937                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3200491                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           20                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2253                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         2273                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8701                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10746                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       111791                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       131238                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         5770                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       383774                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      4816873                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      5206417                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         5770                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       383774                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      4816873                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      5206417                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       626785                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       841989                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1570865                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3039639                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       248438                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       356198                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       597816                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1202452                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       138310                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       204087                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       332211                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       674608                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       108292                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       153493                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       296025                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       557810                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        28305                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        37083                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        70343                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       135731                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            3                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       875223                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      1198187                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data      2168681                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4242091                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1013533                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      1402274                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data      2500892                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4916699                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5947                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4621                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         4770                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        15338                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         5383                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4193                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         4437                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14013                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        11330                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         8814                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data         9207                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        29351                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   8948924500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12450643000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  23749051500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45148619000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6583355500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9198762000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17328942473                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33111059973                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2410482500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3025654000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   5045013000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10481149500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   2532564500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   4225854500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10181517242                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  16939936242                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    374149000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    474867500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    928593000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1777609500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       127000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       127000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  15532280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  21649405000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  41077993973                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  78259678973                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  17942762500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  24675059000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  46123006973                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  88740828473                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1021104000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    786468000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    830220000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2637792000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    943050500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    717793000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data    802384000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2463227500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1964154500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1504261000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1632604000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5101019500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031392                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.030540                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031917                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019125                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013825                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014605                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014132                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008553                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.745136                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.717351                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.738337                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.423697                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.710549                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.741652                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.744275                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.358262                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060128                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.059351                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.060890                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.035791                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023155                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023277                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023401                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.014088                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026774                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.026936                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.026871                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.016233                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14582.883002                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14716.654617                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15284.079431                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14978.730200                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26725.268093                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25692.604543                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29203.657466                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27652.581812                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17482.763631                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14944.295833                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15257.286093                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15633.827010                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24453.793581                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26631.516214                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34917.602193                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30625.733688                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12906.166358                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12951.914652                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13262.538301                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13098.909112                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        34625                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        34625                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18060.068470                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17894.733506                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19145.127390                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18562.034952                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17979.566040                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17480.358952                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18626.606006                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18161.839600                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176213.586098                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168701.067981                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 173900.518672                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173234.159436                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180191.861472                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 169394.814646                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180736.671872                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177119.037871                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178111.524164                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 169030.271962                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177194.775879                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175090.222990                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023071                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023060                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023697                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.014162                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026587                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.026841                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027193                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.016328                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14277.502652                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14787.180118                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15118.454800                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14853.283235                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26498.987675                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25824.855839                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 28987.083773                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27536.284170                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17428.114381                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14825.314694                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15186.170837                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15536.651655                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23386.441288                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 27531.252240                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34394.112801                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30368.649257                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13218.477301                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12805.530836                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13200.929730                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13096.562318                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 42333.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 42333.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17746.654281                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18068.469279                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18941.464408                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18448.373449                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17703.185293                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17596.460464                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18442.622462                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18048.863368                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171700.689423                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170194.330232                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174050.314465                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171977.572043                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 175190.507152                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171188.409254                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180839.305837                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175781.595661                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173358.737864                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170667.233946                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177322.037580                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173793.720827                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         15815402                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.974774                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          560516546                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         15815914                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.440035                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10320548500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   470.983323                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     3.370310                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    25.740928                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst    11.880214                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.919889                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.006583                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.050275                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.023204                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         15787116                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.974790                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          559161583                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         15787628                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.417707                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10320304500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   471.137124                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     3.371284                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    26.901455                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst    10.564927                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.920190                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.006585                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.052542                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.020635                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        592508619                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       592508619                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    338062772                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    107390355                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     66013680                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst     49049739                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      560516546                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    338062772                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    107390355                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     66013680                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst     49049739                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       560516546                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    338062772                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    107390355                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     66013680                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst     49049739                       # number of overall hits
-system.cpu0.icache.overall_hits::total      560516546                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5529192                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1696190                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      3915157                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst      5035545                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     16176084                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5529192                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1696190                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      3915157                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst      5035545                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      16176084                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5529192                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1696190                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst      3915157                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst      5035545                       # number of overall misses
-system.cpu0.icache.overall_misses::total     16176084                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22827874500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52925900000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  65832917354                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 141586691854                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  22827874500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  52925900000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst  65832917354                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 141586691854                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  22827874500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  52925900000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst  65832917354                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 141586691854                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    343591964                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    109086545                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     69928837                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst     54085284                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    576692630                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    343591964                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    109086545                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     69928837                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst     54085284                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    576692630                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    343591964                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    109086545                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     69928837                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst     54085284                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    576692630                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016092                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015549                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.055988                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.093104                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028050                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016092                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015549                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.055988                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.093104                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028050                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016092                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015549                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.055988                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.093104                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028050                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13458.323950                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13518.206294                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13073.642943                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8752.841037                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13458.323950                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13518.206294                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13073.642943                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8752.841037                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13458.323950                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13518.206294                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13073.642943                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8752.841037                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        40592                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        591095135                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       591095135                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    336798799                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    107446320                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     66160424                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst     48756040                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      559161583                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    336798799                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    107446320                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst     66160424                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst     48756040                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       559161583                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    336798799                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    107446320                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     66160424                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst     48756040                       # number of overall hits
+system.cpu0.icache.overall_hits::total      559161583                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5516825                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1724189                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst      3891179                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst      5013652                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     16145845                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5516825                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1724189                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst      3891179                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu3.inst      5013652                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      16145845                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5516825                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1724189                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst      3891179                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst      5013652                       # number of overall misses
+system.cpu0.icache.overall_misses::total     16145845                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  23134479500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52416586500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  65622518853                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 141173584853                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  23134479500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst  52416586500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst  65622518853                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 141173584853                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  23134479500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst  52416586500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst  65622518853                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 141173584853                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    342315624                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    109170509                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     70051603                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst     53769692                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    575307428                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    342315624                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    109170509                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     70051603                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst     53769692                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    575307428                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    342315624                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    109170509                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     70051603                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst     53769692                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    575307428                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016116                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015794                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.055547                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.093243                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028065                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016116                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015794                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.055547                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.093243                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028065                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016116                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015794                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.055547                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.093243                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028065                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.600681                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13470.618160                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13088.766203                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8743.647970                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13417.600681                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13470.618160                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13088.766203                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8743.647970                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13417.600681                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13470.618160                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13088.766203                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8743.647970                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        43982                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3092                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             3227                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.128072                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.629377                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       360095                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       360095                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst       360095                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       360095                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst       360095                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       360095                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1696190                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3915157                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4675450                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10286797                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1696190                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      3915157                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst      4675450                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10286797                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1696190                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      3915157                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst      4675450                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10286797                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21131684500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  49010743000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58303327383                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 128445754883                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21131684500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  49010743000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58303327383                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 128445754883                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21131684500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  49010743000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58303327383                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 128445754883                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015549                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.055988                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.086446                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017838                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015549                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.055988                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.086446                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017838                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015549                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.055988                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.086446                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017838                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12458.323950                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12518.206294                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12470.099645                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12486.467351                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12458.323950                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12518.206294                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12470.099645                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12486.467351                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12458.323950                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12518.206294                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.099645                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12486.467351                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       358138                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       358138                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst       358138                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       358138                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst       358138                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       358138                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1724189                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3891179                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4655514                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10270882                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1724189                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      3891179                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst      4655514                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10270882                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1724189                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      3891179                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst      4655514                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10270882                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21410290500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48525407500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58117116880                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 128052814880                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21410290500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48525407500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58117116880                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 128052814880                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21410290500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48525407500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58117116880                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 128052814880                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015794                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.055547                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.086582                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017853                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015794                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.055547                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.086582                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017853                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015794                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.055547                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.086582                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017853                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12417.600681                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12470.618160                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12483.501689                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12467.557789                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12417.600681                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12470.618160                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12483.501689                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12467.557789                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12417.600681                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12470.618160                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12483.501689                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12467.557789                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1228,67 +1229,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    31331                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                31331                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4585                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        22783                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walks                    32157                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                32157                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4670                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23647                       # Level at which table walker walks with long descriptors terminate
 system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        31326                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          31326    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        31326                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        27373                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24398.385270                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21301.040403                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13057.600682                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        17904     65.41%     65.41% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         9272     33.87%     99.28% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          108      0.39%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071           61      0.22%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839            4      0.01%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           12      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375            1      0.00%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143            5      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        27373                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2726095120                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.627697                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.483419                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1014934000     37.23%     37.23% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1711161120     62.77%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2726095120                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        22783     83.25%     83.25% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         4585     16.75%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        27368                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31331                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::samples        32152                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          32152    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        32152                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        28322                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24465.680390                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21462.893478                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 12624.124225                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        18193     64.24%     64.24% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535         9967     35.19%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303           97      0.34%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071           42      0.15%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839            3      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607            9      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            2      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        28322                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -3003382012                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     1.339073                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1018364500    -33.91%    -33.91% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -4021746512    133.91%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -3003382012                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        23647     83.51%     83.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         4670     16.49%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        28317                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        32157                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31331                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27368                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        32157                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        28317                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27368                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        58699                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        28317                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        60474                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    20435080                       # DTB read hits
-system.cpu1.dtb.read_misses                     24017                       # DTB read misses
-system.cpu1.dtb.write_hits                   18473169                       # DTB write hits
-system.cpu1.dtb.write_misses                     7314                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1184                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    20628760                       # DTB read hits
+system.cpu1.dtb.read_misses                     24754                       # DTB read misses
+system.cpu1.dtb.write_hits                   18600606                       # DTB write hits
+system.cpu1.dtb.write_misses                     7403                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1180                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               5397                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    130                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   17737                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               5222                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    123                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   17774                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   965                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   948                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2574                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                20459097                       # DTB read accesses
-system.cpu1.dtb.write_accesses               18480483                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     2501                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                20653514                       # DTB read accesses
+system.cpu1.dtb.write_accesses               18608009                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         38908249                       # DTB hits
-system.cpu1.dtb.misses                          31331                       # DTB misses
-system.cpu1.dtb.accesses                     38939580                       # DTB accesses
+system.cpu1.dtb.hits                         39229366                       # DTB hits
+system.cpu1.dtb.misses                          32157                       # DTB misses
+system.cpu1.dtb.accesses                     39261523                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1318,135 +1320,134 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    20082                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                20082                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          956                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17736                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        20082                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          20082    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        20082                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        18692                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27635.592767                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24782.304535                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 14713.760053                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767         9635     51.55%     51.55% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         8833     47.26%     98.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           80      0.43%     99.23% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          115      0.62%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839            1      0.01%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           12      0.06%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375            3      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            3      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            4      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        18692                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    20715                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                20715                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          930                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        18416                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        20715                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          20715    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        20715                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        19346                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27414.659361                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24764.281979                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 13419.535342                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767         9905     51.20%     51.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         9256     47.84%     99.04% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303           65      0.34%     99.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071           99      0.51%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839            1      0.01%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607            7      0.04%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143            4      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            4      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        19346                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        17736     94.89%     94.89% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          956      5.11%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        18692                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        18416     95.19%     95.19% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          930      4.81%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        19346                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20082                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20082                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20715                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20715                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18692                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18692                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        38774                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   109086545                       # ITB inst hits
-system.cpu1.itb.inst_misses                     20082                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        19346                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        19346                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        40061                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   109170509                       # ITB inst hits
+system.cpu1.itb.inst_misses                     20715                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1184                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1180                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               5397                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    130                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   13123                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               5222                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    123                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   13293                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               109106627                       # ITB inst accesses
-system.cpu1.itb.hits                        109086545                       # DTB hits
-system.cpu1.itb.misses                          20082                       # DTB misses
-system.cpu1.itb.accesses                    109106627                       # DTB accesses
-system.cpu1.numCycles                      1184099170                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               109191224                       # ITB inst accesses
+system.cpu1.itb.hits                        109170509                       # DTB hits
+system.cpu1.itb.misses                          20715                       # DTB misses
+system.cpu1.itb.accesses                    109191224                       # DTB accesses
+system.cpu1.numCycles                      1180099422                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  109009230                       # Number of instructions committed
-system.cpu1.committedOps                    127862448                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            117464588                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                115738                       # Number of float alu accesses
-system.cpu1.num_func_calls                    6440342                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     16554986                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   117464588                       # number of integer instructions
-system.cpu1.num_fp_insts                       115738                       # number of float instructions
-system.cpu1.num_int_register_reads          169322185                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          93148708                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              190671                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              89412                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            28259298                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           28158154                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     38905190                       # number of memory refs
-system.cpu1.num_load_insts                   20434165                       # Number of load instructions
-system.cpu1.num_store_insts                  18471025                       # Number of store instructions
-system.cpu1.num_idle_cycles              1158563290.473996                       # Number of idle cycles
-system.cpu1.num_busy_cycles              25535879.526004                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.021566                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.978434                       # Percentage of idle cycles
-system.cpu1.Branches                         24332682                       # Number of branches fetched
+system.cpu1.committedInsts                  109095321                       # Number of instructions committed
+system.cpu1.committedOps                    128047126                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            117680197                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                117915                       # Number of float alu accesses
+system.cpu1.num_func_calls                    6450893                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     16554916                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   117680197                       # number of integer instructions
+system.cpu1.num_fp_insts                       117915                       # number of float instructions
+system.cpu1.num_int_register_reads          169047923                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          93200008                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              191658                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              96888                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            28194465                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           28098874                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     39226015                       # number of memory refs
+system.cpu1.num_load_insts                   20627300                       # Number of load instructions
+system.cpu1.num_store_insts                  18598715                       # Number of store instructions
+system.cpu1.num_idle_cycles              1154150302.947621                       # Number of idle cycles
+system.cpu1.num_busy_cycles              25949119.052379                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021989                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978011                       # Percentage of idle cycles
+system.cpu1.Branches                         24363890                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 88740475     69.36%     69.36% # Class of executed instruction
-system.cpu1.op_class::IntMult                  271069      0.21%     69.57% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    11362      0.01%     69.58% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             11625      0.01%     69.59% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
-system.cpu1.op_class::MemRead                20434165     15.97%     85.56% # Class of executed instruction
-system.cpu1.op_class::MemWrite               18471025     14.44%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 88601672     69.15%     69.15% # Class of executed instruction
+system.cpu1.op_class::IntMult                  269277      0.21%     69.36% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    11730      0.01%     69.37% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             13579      0.01%     69.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.38% # Class of executed instruction
+system.cpu1.op_class::MemRead                20627300     16.10%     85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite               18598715     14.52%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 127939763                       # Class of executed instruction
+system.cpu1.op_class::total                 128122314                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               40521416                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28118087                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          2031475                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            29676837                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               20868777                       # Number of BTB hits
+system.cpu2.branchPred.lookups               40464780                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28154198                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          1978898                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            29418306                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               20974527                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            70.320085                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4994532                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            335745                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            71.297535                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4946229                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            331686                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1476,62 +1477,64 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    95252                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong                95252                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         7000                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        29929                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        95252                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          95252    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        95252                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples        36929                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 24871.388340                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 22228.503196                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 11289.834647                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767        23698     64.17%     64.17% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::32768-65535        13086     35.44%     99.61% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-98303           84      0.23%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::98304-131071           38      0.10%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-163839            4      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::163840-196607            9      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-229375            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::229376-262143            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-294911            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-360447            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total        36929                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks                    93767                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong                93767                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6983                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        29518                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        93767                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          93767    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        93767                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples        36501                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 24922.262404                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 22135.996220                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 12304.178118                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767        23409     64.13%     64.13% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-65535        12906     35.36%     99.49% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-98303           87      0.24%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::98304-131071           74      0.20%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-163839            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::163840-196607            7      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-229375            3      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::229376-262143            4      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-294911            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::294912-327679            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-360447            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total        36501                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000228500                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000228500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000228500                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        29929     81.04%     81.04% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M         7000     18.96%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        36929                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        95252                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K        29518     80.87%     80.87% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M         6983     19.13%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        36501                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93767                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        95252                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        36929                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93767                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        36501                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        36929                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       132181                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        36501                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       130268                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    29009718                       # DTB read hits
-system.cpu2.dtb.read_misses                     79511                       # DTB read misses
-system.cpu2.dtb.write_hits                   25340544                       # DTB write hits
-system.cpu2.dtb.write_misses                    15741                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1184                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    28765084                       # DTB read hits
+system.cpu2.dtb.read_misses                     78268                       # DTB read misses
+system.cpu2.dtb.write_hits                   25322239                       # DTB write hits
+system.cpu2.dtb.write_misses                    15499                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1180                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid               6565                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    192                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   22319                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       74                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  2265                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid               6709                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    189                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   22277                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                       76                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  2199                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                     3693                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                29089229                       # DTB read accesses
-system.cpu2.dtb.write_accesses               25356285                       # DTB write accesses
+system.cpu2.dtb.perms_faults                     3811                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                28843352                       # DTB read accesses
+system.cpu2.dtb.write_accesses               25337738                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         54350262                       # DTB hits
-system.cpu2.dtb.misses                          95252                       # DTB misses
-system.cpu2.dtb.accesses                     54445514                       # DTB accesses
+system.cpu2.dtb.hits                         54087323                       # DTB hits
+system.cpu2.dtb.misses                          93767                       # DTB misses
+system.cpu2.dtb.accesses                     54181090                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1561,87 +1564,85 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                    27224                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                27224                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1814                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22841                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples        27224                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0          27224    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        27224                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        24655                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 27863.922125                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 25521.619222                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 11746.072802                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        11779     47.78%     47.78% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        12711     51.56%     99.33% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303           67      0.27%     99.60% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::98304-131071           84      0.34%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839            1      0.00%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607            5      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                    27119                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                27119                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1817                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22640                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples        27119                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0          27119    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        27119                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        24457                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 28043.607147                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25574.105463                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 12475.611214                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        11681     47.76%     47.76% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535        12550     51.31%     99.08% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303           85      0.35%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071          123      0.50%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607            7      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375            6      0.02%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walkCompletionTime::262144-294911            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walkCompletionTime::294912-327679            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::327680-360447            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        24655                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total        24457                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000202500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000202500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000202500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        22841     92.64%     92.64% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         1814      7.36%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        24655                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K        22640     92.57%     92.57% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         1817      7.43%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        24457                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27224                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27224                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27119                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27119                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24655                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24655                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total        51879                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    69987684                       # ITB inst hits
-system.cpu2.itb.inst_misses                     27224                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24457                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24457                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total        51576                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    70111472                       # ITB inst hits
+system.cpu2.itb.inst_misses                     27119                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1184                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1180                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid               6565                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    192                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   17001                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid               6709                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    189                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   16886                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                    55845                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                    56888                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                70014908                       # ITB inst accesses
-system.cpu2.itb.hits                         69987684                       # DTB hits
-system.cpu2.itb.misses                          27224                       # DTB misses
-system.cpu2.itb.accesses                     70014908                       # DTB accesses
-system.cpu2.numCycles                      6727315780                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                70138591                       # ITB inst accesses
+system.cpu2.itb.hits                         70111472                       # DTB hits
+system.cpu2.itb.misses                          27119                       # DTB misses
+system.cpu2.itb.accesses                     70138591                       # DTB accesses
+system.cpu2.numCycles                      6662793368                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                  148611673                       # Number of instructions committed
-system.cpu2.committedOps                    174373358                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                     14098587                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                     1631                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                 95904949193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             45.267748                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.022091                       # IPC: instructions per cycle
+system.cpu2.committedInsts                  148437005                       # Number of instructions committed
+system.cpu2.committedOps                    174093973                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                     14341019                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                     1575                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                 95890004718                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             44.886337                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.022278                       # IPC: instructions per cycle
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                      276122031                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     6451193749                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               75051711                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted         50745018                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect          3426540                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups            51416576                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits               36523401                       # Number of BTB hits
+system.cpu2.tickCycles                      276177864                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     6386615504                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               74718826                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted         50589890                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect          3325419                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups            50396966                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits               36328478                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            71.034293                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                9845099                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect            104872                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            72.084653                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                9777895                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect            104949                       # Number of incorrect RAS predictions.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1671,91 +1672,91 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                   518940                       # Table walker walks requested
-system.cpu3.dtb.walker.walksLong               518940                       # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8603                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        51054                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore       322381                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples       196559                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean  2153.353446                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 12453.010606                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535       195431     99.43%     99.43% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071          797      0.41%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607          204      0.10%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143           65      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679           34      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751           11      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total       196559                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples       238895                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 21937.397183                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18018.053356                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.644026                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-32767       188060     78.72%     78.72% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-65535        46353     19.40%     98.12% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-98303         3667      1.53%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::98304-131071          466      0.20%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-163839           68      0.03%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::163840-196607           89      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-229375          102      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::229376-262143           32      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-294911           22      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::294912-327679           17      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-360447           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::360448-393215            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total       238895                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -25404728884                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     1.186676                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -25965813384    102.21%    102.21% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7    315763500     -1.24%    100.97% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11    105079500     -0.41%    100.55% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15     65519000     -0.26%    100.29% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19     25638000     -0.10%    100.19% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23     14396000     -0.06%    100.14% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27     12378500     -0.05%    100.09% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31     18510000     -0.07%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35      3399500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39       261000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43        34500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47        99500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51         5500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -25404728884                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K        51054     85.58%     85.58% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M         8603     14.42%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total        59657                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       518940                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks                   514773                       # Table walker walks requested
+system.cpu3.dtb.walker.walksLong               514773                       # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8632                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        50765                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore       320483                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples       194290                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean  2154.802100                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 11919.135471                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-32767       190271     97.93%     97.93% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-65535         2868      1.48%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-98303          495      0.25%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::98304-131071          352      0.18%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-163839          145      0.07%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::163840-196607           61      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-229375           39      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::229376-262143           16      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-294911           21      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::360448-393215            8      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-425983            9      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total       194290                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples       239173                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 21856.421921                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 17938.758794                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.793116                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535       234615     98.09%     98.09% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071         4213      1.76%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607          180      0.08%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143          137      0.06%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679           10      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total       239173                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -26483974220                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.370007                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -27038933220    102.10%    102.10% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7    309842500     -1.17%    100.93% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11    102710000     -0.39%    100.54% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15     66075500     -0.25%    100.29% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19     25941500     -0.10%    100.19% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23     14268000     -0.05%    100.14% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27     12970500     -0.05%    100.09% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31     19273500     -0.07%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35      3639000     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39       190500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43        29000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47         8000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::48-51        11000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -26483974220                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K        50765     85.47%     85.47% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M         8632     14.53%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total        59397                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       514773                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       518940                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        59657                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       514773                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        59397                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        59657                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total       578597                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        59397                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total       574170                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                    58887686                       # DTB read hits
-system.cpu3.dtb.read_misses                    354452                       # DTB read misses
-system.cpu3.dtb.write_hits                   46401949                       # DTB write hits
-system.cpu3.dtb.write_misses                   164488                       # DTB write misses
-system.cpu3.dtb.flush_tlb                        1183                       # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits                    58948022                       # DTB read hits
+system.cpu3.dtb.read_misses                    349619                       # DTB read misses
+system.cpu3.dtb.write_hits                   46411302                       # DTB write hits
+system.cpu3.dtb.write_misses                   165154                       # DTB write misses
+system.cpu3.dtb.flush_tlb                        1180                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid              11695                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid                    298                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                   29305                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                       75                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                  5086                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid              11984                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid                    297                       # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries                   29239                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                       79                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                  5206                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                    31208                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                59242138                       # DTB read accesses
-system.cpu3.dtb.write_accesses               46566437                       # DTB write accesses
+system.cpu3.dtb.perms_faults                    31663                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                59297641                       # DTB read accesses
+system.cpu3.dtb.write_accesses               46576456                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                        105289635                       # DTB hits
-system.cpu3.dtb.misses                         518940                       # DTB misses
-system.cpu3.dtb.accesses                    105808575                       # DTB accesses
+system.cpu3.dtb.hits                        105359324                       # DTB hits
+system.cpu3.dtb.misses                         514773                       # DTB misses
+system.cpu3.dtb.accesses                    105874097                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1785,380 +1786,384 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                    61371                       # Table walker walks requested
-system.cpu3.itb.walker.walksLong                61371                       # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1880                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41824                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore         8320                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples        53051                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1484.693974                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  7949.697617                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-32767        52591     99.13%     99.13% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-65535          303      0.57%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-98303           95      0.18%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-131071           39      0.07%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-163839            8      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::163840-196607           10      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::229376-262143            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total        53051                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples        52024                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 27951.877979                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 24094.893737                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 16939.258391                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-65535        51107     98.24%     98.24% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-131071          782      1.50%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walks                    60795                       # Table walker walks requested
+system.cpu3.itb.walker.walksLong                60795                       # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1936                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41390                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore         8352                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples        52443                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1489.417081                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  8610.325599                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767        51982     99.12%     99.12% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535          282      0.54%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303          109      0.21%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071           37      0.07%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839            7      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607           13      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total        52443                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples        51678                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 27642.962189                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 23739.857132                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 16715.530485                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-65535        50770     98.24%     98.24% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-131071          774      1.50%     99.74% # Table walker service (enqueue to completion) latency
 system.cpu3.itb.walker.walkCompletionTime::131072-196607           83      0.16%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-262143           28      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-327679           17      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-393215            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total        52024                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -25407358384                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     1.082792                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0     2146509568     -8.45%     -8.45% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1   -27591517452    108.60%    100.15% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2       32946500     -0.13%    100.02% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3        4144000     -0.02%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         483500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5          75500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -25407358384                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K        41824     95.70%     95.70% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M         1880      4.30%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total        43704                       # Table walker page sizes translated
+system.cpu3.itb.walker.walkCompletionTime::196608-262143           35      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-327679            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-393215            9      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total        51678                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -30778988516                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.762645                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.421863                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -7265808116     23.61%     23.61% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1   -23547141900     76.50%    100.11% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2       29216500     -0.09%    100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3        4017500     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         490000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5         170000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6          67500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -30778988516                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K        41390     95.53%     95.53% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M         1936      4.47%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total        43326                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        61371                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total        61371                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        60795                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total        60795                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43704                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43704                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total       105075                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                    54222751                       # ITB inst hits
-system.cpu3.itb.inst_misses                     61371                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43326                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43326                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total       104121                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                    53907663                       # ITB inst hits
+system.cpu3.itb.inst_misses                     60795                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                        1183                       # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb                        1180                       # Number of times complete TLB was flushed
 system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid              11695                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid                    298                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                   22112                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid              11984                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid                    297                       # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries                   22179                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                   119556                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                   120136                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                54284122                       # ITB inst accesses
-system.cpu3.itb.hits                         54222751                       # DTB hits
-system.cpu3.itb.misses                          61371                       # DTB misses
-system.cpu3.itb.accesses                     54284122                       # DTB accesses
-system.cpu3.numCycles                       362116242                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                53968458                       # ITB inst accesses
+system.cpu3.itb.hits                         53907663                       # DTB hits
+system.cpu3.itb.misses                          60795                       # DTB misses
+system.cpu3.itb.accesses                     53968458                       # DTB accesses
+system.cpu3.numCycles                       361864421                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         140692068                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                     333606704                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   75051711                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches          46368500                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    200357205                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                7729147                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                   1466432                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                5775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles             2417                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles      3039056                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        93220                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles         3908                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                 54085330                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes              2111003                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                  24755                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples         349524457                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.117326                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.359483                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles         140139481                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                     332397649                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   74718826                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches          46106373                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                    200741121                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                7544543                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                   1439697                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                5770                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles             2171                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles      3065576                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        88539                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles         4142                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                 53769751                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes              2045312                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                  24414                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples         349258578                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.114486                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.357052                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0               267214314     76.45%     76.45% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                10401691      2.98%     79.43% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                10376538      2.97%     82.40% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 7732436      2.21%     84.61% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                15785532      4.52%     89.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                 5057577      1.45%     90.57% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 5498876      1.57%     92.14% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                 4902371      1.40%     93.55% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                22555122      6.45%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0               267245928     76.52%     76.52% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                10321823      2.96%     79.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                10331128      2.96%     82.43% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 7716473      2.21%     84.64% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                15764851      4.51%     89.15% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                 5041778      1.44%     90.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 5511234      1.58%     92.18% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                 4828224      1.38%     93.56% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                22497139      6.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total           349524457                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.207259                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.921270                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               115102148                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            163151118                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                 60941298                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              7267408                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles               3060603                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved            11237446                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred               815602                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts             364546839                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts              2510722                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles               3060603                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               119327697                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles               12479500                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles     131448496                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                 63890938                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             19315280                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             355739076                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                49184                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents               1032074                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                774475                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               9071524                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents            2005                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          339501197                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            543916726                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       420235861                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups           502563                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps            283815673                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                55685519                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts           8092119                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts       6958081                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 40275448                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads            57221877                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores           48841814                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          7500676                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         8056084                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                 337690712                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded            8109511                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                336678168                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued           492039                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined       46643392                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     29867606                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved        195066                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples    349524457                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.963246                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.677033                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total           349258578                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.206483                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.918570                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles               114369930                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles            164038042                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                 60584469                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              7298385                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles               2965812                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved            11163267                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred               817702                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts             363461294                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts              2524053                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles               2965812                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles               118569176                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles               12281642                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles     132557510                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                 63592874                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles             19289346                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts             354946625                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                42029                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents               1018488                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                787978                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               8985547                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents            1997                       # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands          338843996                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            543179256                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups       419420785                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups           479701                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps            284856001                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                53987990                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts           8148289                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts       7010381                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                 40518568                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads            57083242                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores           48761213                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          7628593                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         8153720                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                 337135094                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded            8186679                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                336664947                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued           479828                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined       45100588                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     28943367                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved        197497                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples    349258578                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.963942                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.678060                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0          218668838     62.56%     62.56% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1           53919118     15.43%     77.99% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2           24783168      7.09%     85.08% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3           17648409      5.05%     90.13% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4           13036700      3.73%     93.86% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5            9178789      2.63%     96.48% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6            6241479      1.79%     98.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7            3625780      1.04%     99.31% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8            2422176      0.69%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0          218381855     62.53%     62.53% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1           54040442     15.47%     78.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2           24694063      7.07%     85.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3           17645756      5.05%     90.12% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4           13020798      3.73%     93.85% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5            9160873      2.62%     96.47% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6            6234653      1.79%     98.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7            3637468      1.04%     99.30% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8            2442670      0.70%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total      349524457                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total      349258578                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                1699142     25.95%     25.95% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                 17812      0.27%     26.22% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                   1053      0.02%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.24% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead               2601719     39.74%     65.97% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite              2227949     34.03%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                1713190     25.96%     25.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                 16354      0.25%     26.20% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                   1162      0.02%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead               2637813     39.97%     66.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite              2231741     33.81%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               12      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu            228602725     67.90%     67.90% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult              820222      0.24%     68.14% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                38384      0.01%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   5      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc         43257      0.01%     68.17% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu            228589817     67.90%     67.90% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult              839294      0.25%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                38427      0.01%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                187      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc         41560      0.01%     68.17% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.17% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.17% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.17% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead            60130906     17.86%     86.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite           47042657     13.97%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead            60136646     17.86%     86.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite           47019015     13.97%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total             336678168                       # Type of FU issued
-system.cpu3.iq.rate                          0.929752                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                    6547675                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.019448                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads        1029252740                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes        392488113                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses    324616709                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads             667767                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes            333618                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses       297362                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses             342868261                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                 357570                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads         2662931                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total             336664947                       # Type of FU issued
+system.cpu3.iq.rate                          0.930362                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                    6600260                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.019605                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads        1029031717                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes        390494788                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses    324869188                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads             636843                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes            315952                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses       284328                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses             342924564                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                 340642                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads         2686629                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      9411324                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses        12714                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation       384094                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores      5127738                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      9062852                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses        11957                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation       394369                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores      4946237                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads      2090075                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      3953629                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads      2102231                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked      3983237                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles               3060603                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                8381523                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles              3212246                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts          345878827                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts          1059491                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts             57221877                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts            48841814                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts           6807675                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                123383                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents              3041851                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents        384094                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect       1583894                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect      1359451                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts             2943345                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts            332673161                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts             58878878                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts          3493066                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles               2965812                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                8240311                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles              3183987                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts          345400316                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts          1015101                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts             57083242                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts            48761213                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts           6857312                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                127001                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents              3008020                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents        394369                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect       1508943                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect      1318655                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts             2827598                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts            332842425                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts             58939894                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts          3314806                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        78604                       # number of nop insts executed
-system.cpu3.iew.exec_refs                   105279838                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                61795726                       # Number of branches executed
-system.cpu3.iew.exec_stores                  46400960                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.918692                       # Inst execution rate
-system.cpu3.iew.wb_sent                     325632326                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                    324914071                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                160314385                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                278113551                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        78543                       # number of nop insts executed
+system.cpu3.iew.exec_refs                   105350305                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                61793426                       # Number of branches executed
+system.cpu3.iew.exec_stores                  46410411                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.919799                       # Inst execution rate
+system.cpu3.iew.wb_sent                     325835982                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                    325153516                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                160610684                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                278606679                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      0.897265                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.576435                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      0.898551                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.576478                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts       46667653                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls        7914445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts          2622372                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples    341617018                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.875708                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.868271                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts       45121096                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls        7989182                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts          2518769                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples    341571330                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.878941                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.873545                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0    232826047     68.15%     68.15% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1     52669534     15.42%     83.57% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2     19043564      5.57%     89.15% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      8581535      2.51%     91.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4      6262304      1.83%     93.49% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5      3681580      1.08%     94.57% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6      3506851      1.03%     95.60% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7      2207487      0.65%     96.24% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8     12838116      3.76%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0    232593389     68.10%     68.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1     52799684     15.46%     83.55% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2     18973015      5.55%     89.11% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      8542771      2.50%     91.61% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4      6283805      1.84%     93.45% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5      3713979      1.09%     94.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6      3487678      1.02%     95.56% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7      2200102      0.64%     96.20% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8     12976907      3.80%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total    341617018                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts           254540187                       # Number of instructions committed
-system.cpu3.commit.committedOps             299156826                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total    341571330                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts           255441658                       # Number of instructions committed
+system.cpu3.commit.committedOps             300221180                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      91524628                       # Number of memory references committed
-system.cpu3.commit.loads                     47810552                       # Number of loads committed
-system.cpu3.commit.membars                    2044329                       # Number of memory barriers committed
-system.cpu3.commit.branches                  56838517                       # Number of branches committed
-system.cpu3.commit.fp_insts                    284474                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                274963169                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             7559690                       # Number of function calls committed.
+system.cpu3.commit.refs                      91835365                       # Number of memory references committed
+system.cpu3.commit.loads                     48020389                       # Number of loads committed
+system.cpu3.commit.membars                    2080926                       # Number of memory barriers committed
+system.cpu3.commit.branches                  57030615                       # Number of branches committed
+system.cpu3.commit.fp_insts                    272912                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                275960484                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             7595427                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu       206931641     69.17%     69.17% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult         635252      0.21%     69.38% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv           28375      0.01%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc        36930      0.01%     69.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu       207669074     69.17%     69.17% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult         652533      0.22%     69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv           28496      0.01%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.40% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc        35712      0.01%     69.41% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.41% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.41% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.41% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead       47810552     15.98%     85.39% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite      43714076     14.61%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead       48020389     16.00%     85.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite      43814976     14.59%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total        299156826                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events             12838116                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                   672513030                       # The number of ROB reads
-system.cpu3.rob.rob_writes                  699568614                       # The number of ROB writes
-system.cpu3.timesIdled                        2366771                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                       12591785                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                 98718850803                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                  254540187                       # Number of Instructions Simulated
-system.cpu3.committedOps                    299156826                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.422629                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.422629                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.702924                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.702924                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads               392099204                       # number of integer regfile reads
-system.cpu3.int_regfile_writes              232294349                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                   578128                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                  349384                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                 70503993                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                71192448                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads              655577760                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes               7960975                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40269                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40269                       # Transaction distribution
+system.cpu3.commit.op_class_0::total        300221180                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events             12976907                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                   671801943                       # The number of ROB reads
+system.cpu3.rob.rob_writes                  698382232                       # The number of ROB writes
+system.cpu3.timesIdled                        2359266                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                       12605843                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                 98651627369                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                  255441658                       # Number of Instructions Simulated
+system.cpu3.committedOps                    300221180                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.416623                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.416623                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.705904                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.705904                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads               392429814                       # number of integer regfile reads
+system.cpu3.int_regfile_writes              232475172                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                   557185                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                  341168                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                 70618800                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                71286741                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads              655702130                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes               8023774                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40266                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40266                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136539                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136539                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47694                       # Packet count per connected master and slave (bytes)
@@ -2177,11 +2182,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353616                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353610                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47714                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2198,12 +2203,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155706                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492064                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             14862000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492040                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13439000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2223,70 +2228,70 @@ system.iobus.reqLayer16.occupancy                4000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            10142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             9713000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy               45000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            18725000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            18683000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy                1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           244315631                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           237657786                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            45003000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            43053000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            69196000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            55076000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115462                       # number of replacements
-system.iocache.tags.tagsinuse               10.425339                       # Cycle average of tags in use
+system.iocache.tags.replacements               115459                       # number of replacements
+system.iocache.tags.tagsinuse               10.421040                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115478                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13087689855509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544644                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.880695                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221540                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430043                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651584                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13087689445509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.547391                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.873649                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221712                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429603                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651315                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039677                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039650                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
-system.iocache.overall_misses::total             8856                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide    902834218                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    902834218                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   5365256413                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5365256413                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide    902834218                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    902834218                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide    902834218                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    902834218                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
+system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide    399236664                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    399236664                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   5327578122                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5327578122                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide    399236664                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    399236664                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide    399236664                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    399236664                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2300,505 +2305,504 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 102408.600045                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 101980.596182                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 50300.536385                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 50300.536385                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 102408.600045                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 101946.049910                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 102408.600045                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 101946.049910                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         17834                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 45300.880971                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 45111.487458                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 49947.293576                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 49947.293576                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 45300.880971                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 45096.200610                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 45300.880971                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 45096.200610                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          7536                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 1976                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                  866                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.025304                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.702079                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide         4982                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         4982                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        45408                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        45408                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         4982                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         4982                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         4982                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         4982                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide    653734218                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    653734218                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3094856413                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3094856413                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    653734218                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    653734218                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    653734218                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    653734218                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.565109                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.562747                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.425711                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.425711                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.565109                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.562556                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.565109                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.562556                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131219.232838                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 131219.232838                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68156.633479                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68156.633479                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 131219.232838                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131219.232838                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 131219.232838                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131219.232838                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::realview.ide         2210                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         2210                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        45088                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        45088                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         2210                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         2210                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         2210                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         2210                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide    288736664                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    288736664                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3073178122                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3073178122                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide    288736664                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    288736664                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide    288736664                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    288736664                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.250766                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.249718                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.422711                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.422711                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.250766                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.249633                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.250766                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.249633                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130650.074208                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 130650.074208                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68159.557355                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68159.557355                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 130650.074208                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 130650.074208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 130650.074208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 130650.074208                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1197494                       # number of replacements
-system.l2c.tags.tagsinuse                65334.177646                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   47583797                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1260356                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    37.754251                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1184273                       # number of replacements
+system.l2c.tags.tagsinuse                65309.557565                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   47546139                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1247279                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    38.119891                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36625.887647                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   129.652823                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   192.600178                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3297.722493                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    10271.458508                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    44.360816                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    62.862423                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      734.403230                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2295.121948                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    38.166542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker    55.564036                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2274.574548                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3138.217003                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    98.389522                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker   140.202266                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     1940.354614                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     3994.639050                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.558867                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001978                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002939                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.050319                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.156730                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000677                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000959                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.011206                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.035021                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   36497.090356                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   128.195847                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   207.365343                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3477.103411                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    10892.259737                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    41.622029                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    64.439339                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      663.388118                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2525.804190                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    38.130985                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker    52.876796                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2102.725425                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2793.262675                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker   102.733184                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.itb.walker   141.240216                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst     2056.053767                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data     3525.266147                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.556901                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001956                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003164                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.053056                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.166203                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000635                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000983                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.010122                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.038541                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000848                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.034707                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.047885                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001501                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.itb.walker     0.002139                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.029607                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.060953                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996920                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          305                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62557                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          304                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          569                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2827                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5128                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53917                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004654                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.954544                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                421629401                       # Number of tag accesses
-system.l2c.tags.data_accesses               421629401                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       162534                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       110569                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        55382                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        41930                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       157494                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        59360                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker       299154                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker       112124                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 998547                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         7530303                       # number of Writeback hits
-system.l2c.Writeback_hits::total              7530303                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            3865                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1247                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data            1535                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data            2775                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9422                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu3.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           634082                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           192446                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data           277703                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data           471607                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1575838                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       5493197                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       1685224                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst       3887506                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst       4647283                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          15713210                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      2580953                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       758591                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data      1060227                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data      1868057                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6267828                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       284671                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data        86494                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu2.data       126322                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu3.data       229482                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           726969                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        162534                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        110569                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             5493197                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3215035                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         55382                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker         41930                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             1685224                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              951037                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        157494                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         59360                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst             3887506                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data             1337930                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker        299154                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker        112124                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst             4647283                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data             2339664                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24555423                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       162534                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       110569                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            5493197                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3215035                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        55382                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker        41930                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            1685224                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             951037                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       157494                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        59360                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst            3887506                       # number of overall hits
-system.l2c.overall_hits::cpu2.data            1337930                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker       299154                       # number of overall hits
-system.l2c.overall_hits::cpu3.itb.walker       112124                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst            4647283                       # number of overall hits
-system.l2c.overall_hits::cpu3.data            2339664                       # number of overall hits
-system.l2c.overall_hits::total               24555423                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1348                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1360                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker          417                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker          408                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker          426                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker          363                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker         1018                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.itb.walker          932                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 6272                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         14062                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4585                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data          5739                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data          9908                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             34294                       # number of UpgradeReq misses
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.000807                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.032085                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.042622                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001568                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.itb.walker     0.002155                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.031373                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.053791                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996545                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          327                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62679                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          327                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          606                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2840                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5162                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53967                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004990                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.956406                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                421248793                       # Number of tag accesses
+system.l2c.tags.data_accesses               421248793                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker       162889                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       111955                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        57699                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker        43341                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker       155107                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        59126                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.dtb.walker       295251                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.itb.walker       109680                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 995048                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         7547308                       # number of Writeback hits
+system.l2c.Writeback_hits::total              7547308                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            3780                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            1173                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data            1572                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data            2840                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                9365                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu3.data             1                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           632256                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           192717                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data           281149                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3.data           476183                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1582305                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       5480649                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst       1714018                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst       3866218                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst       4626735                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          15687620                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      2570779                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       762751                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data      1043289                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data      1899052                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          6275871                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       287062                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data        90395                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu2.data       123163                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu3.data       231327                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           731947                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker        162889                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker        111955                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             5480649                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             3203035                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         57699                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker         43341                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             1714018                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              955468                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker        155107                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker         59126                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst             3866218                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data             1324438                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.dtb.walker        295251                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.itb.walker        109680                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst             4626735                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data             2375235                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                24540844                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       162889                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker       111955                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            5480649                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            3203035                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        57699                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker        43341                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            1714018                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             955468                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker       155107                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker        59126                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst            3866218                       # number of overall hits
+system.l2c.overall_hits::cpu2.data            1324438                       # number of overall hits
+system.l2c.overall_hits::cpu3.dtb.walker       295251                       # number of overall hits
+system.l2c.overall_hits::cpu3.itb.walker       109680                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst            4626735                       # number of overall hits
+system.l2c.overall_hits::cpu3.data            2375235                       # number of overall hits
+system.l2c.overall_hits::total               24540844                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker         1311                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker         1432                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker          325                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker          316                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker          518                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.itb.walker          438                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.dtb.walker         1014                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.itb.walker          938                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 6292                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data         13809                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4442                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data          5676                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data         10160                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             34087                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu3.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         188559                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          51076                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          66860                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data         112125                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             418620                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        35995                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        10966                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst        27651                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst        28085                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total          102697                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       119057                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        33042                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data        40134                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data        73982                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         266215                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       383686                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data        19000                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu2.data        28887                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu3.data        66669                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         498242                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1348                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1360                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             35995                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            307616                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker          417                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker          408                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             10966                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             84118                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker          426                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker          363                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst             27651                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data            106994                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.dtb.walker         1018                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.itb.walker          932                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst             28085                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data            186107                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                793804                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1348                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1360                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            35995                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           307616                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker          417                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker          408                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            10966                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            84118                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker          426                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker          363                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst            27651                       # number of overall misses
-system.l2c.overall_misses::cpu2.data           106994                       # number of overall misses
-system.l2c.overall_misses::cpu3.dtb.walker         1018                       # number of overall misses
-system.l2c.overall_misses::cpu3.itb.walker          932                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst            28085                       # number of overall misses
-system.l2c.overall_misses::cpu3.data           186107                       # number of overall misses
-system.l2c.overall_misses::total               793804                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     35190000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker     35160000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     36174500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker     31569500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.dtb.walker     89352000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.itb.walker     82579500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      310025500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     68776500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data     92773000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3.data    156127500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    317677000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_misses::cpu0.data         185092                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          50106                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          67861                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data         111466                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             414525                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        36176                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst        10171                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst        24961                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst        28695                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total          100003                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       121334                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data        30649                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data        39810                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data        71534                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         263327                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       379740                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data        17897                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu2.data        30330                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu3.data        64698                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         492665                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1311                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1432                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             36176                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            306426                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker          325                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker          316                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             10171                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             80755                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker          518                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.itb.walker          438                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst             24961                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data            107671                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.dtb.walker         1014                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.itb.walker          938                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst             28695                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data            183000                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                784147                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1311                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1432                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            36176                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           306426                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker          325                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker          316                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            10171                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            80755                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker          518                       # number of overall misses
+system.l2c.overall_misses::cpu2.itb.walker          438                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst            24961                       # number of overall misses
+system.l2c.overall_misses::cpu2.data           107671                       # number of overall misses
+system.l2c.overall_misses::cpu3.dtb.walker         1014                       # number of overall misses
+system.l2c.overall_misses::cpu3.itb.walker          938                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst            28695                       # number of overall misses
+system.l2c.overall_misses::cpu3.data           183000                       # number of overall misses
+system.l2c.overall_misses::total               784147                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     27394000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker     26979000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     46265500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.itb.walker     38224500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.dtb.walker     88339000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.itb.walker     82935000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total      310137000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     67216500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data     90783500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data    160025000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    318025000                       # number of UpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu3.data        81000                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::total        81000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4115650000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   5398260500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data  10994713000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  20508623500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    887226500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst   2301476500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst   2388363000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   5577066000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   2751846000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   3344905000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data   6580498500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  12677249500                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data   1513300000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu2.data   2542083000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu3.data   7155981000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total  11211364000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker     35190000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker     35160000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    887226500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   6867496000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker     36174500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker     31569500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst   2301476500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   8743165500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.dtb.walker     89352000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.itb.walker     82579500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst   2388363000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data  17575211500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     39072964500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker     35190000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker     35160000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    887226500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   6867496000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker     36174500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker     31569500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst   2301476500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   8743165500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.dtb.walker     89352000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.itb.walker     82579500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst   2388363000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data  17575211500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    39072964500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       163882                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       111929                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        55799                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        42338                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker       157920                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        59723                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker       300172                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.itb.walker       113056                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1004819                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      7530303                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          7530303                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        17927                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5832                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         7274                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data        12683                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           43716                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu3.data            4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       822641                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       243522                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       344563                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data       583732                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1994458                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      5529192                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      1696190                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst      3915157                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst      4675368                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      15815907                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      2700010                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       791633                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data      1100361                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data      1942039                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      6534043                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       668357                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       105494                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu2.data       155209                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu3.data       296151                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1225211                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       163882                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       111929                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         5529192                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         3522651                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        55799                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        42338                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         1696190                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1035155                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       157920                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        59723                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst         3915157                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data         1444924                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker       300172                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker       113056                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst         4675368                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data         2525771                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25349227                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       163882                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       111929                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        5529192                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        3522651                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        55799                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        42338                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1696190                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1035155                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker       157920                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        59723                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        3915157                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data        1444924                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker       300172                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker       113056                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst        4675368                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data        2525771                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25349227                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008225                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012151                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.007473                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.009637                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002698                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.006078                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003391                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008244                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.006242                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784403                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.786180                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.788974                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.781203                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.784473                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.229212                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.209739                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.194043                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.192083                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.209892                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006510                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006465                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.007063                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.006007                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.006493                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.044095                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041739                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.036473                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.038095                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.040743                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.574073                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.180105                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data     0.186117                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data     0.225118                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.406658                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008225                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.012151                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006510                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.087325                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.007473                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.009637                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.006465                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.081261                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002698                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.006078                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.007063                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.074048                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003391                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.008244                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.006007                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.073683                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.031315                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008225                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.012151                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006510                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.087325                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.007473                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.009637                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.006465                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.081261                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002698                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.006078                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.007063                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.074048                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003391                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.008244                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.006007                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.073683                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.031315                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84388.489209                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86176.470588                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84916.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 86968.319559                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87772.102161                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88604.613734                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 49430.086097                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15000.327154                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 16165.359819                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15757.721034                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  9263.340526                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_miss_latency::cpu1.data   4038641500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   5517856500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data  10924461500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  20480959500                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    821304500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst   2076233000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst   2448035500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   5345573000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   2534482000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data   3329770500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data   6350368500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  12214621000                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data   1420979000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu2.data   2670318500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu3.data   6979114000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total  11070411500                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker     27394000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker     26979000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    821304500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   6573123500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker     46265500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.itb.walker     38224500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst   2076233000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   8847627000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.dtb.walker     88339000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.itb.walker     82935000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst   2448035500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data  17274830000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     38351290500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker     27394000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker     26979000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    821304500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   6573123500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker     46265500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.itb.walker     38224500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst   2076233000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   8847627000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.dtb.walker     88339000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.itb.walker     82935000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst   2448035500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data  17274830000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    38351290500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker       164200                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker       113387                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        58024                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker        43657                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker       155625                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker        59564                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker       296265                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker       110618                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1001340                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      7547308                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          7547308                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        17589                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5615                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data         7248                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data        13000                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           43452                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu3.data            3                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             3                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       817348                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       242823                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data       349010                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data       587649                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1996830                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      5516825                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      1724189                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst      3891179                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst      4655430                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      15787623                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      2692113                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       793400                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data      1083099                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data      1970586                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      6539198                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       666802                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       108292                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu2.data       153493                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu3.data       296025                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1224612                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       164200                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       113387                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         5516825                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         3509461                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        58024                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker        43657                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         1724189                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1036223                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker       155625                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        59564                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst         3891179                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data         1432109                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker       296265                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker       110618                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst         4655430                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data         2558235                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            25324991                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       164200                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       113387                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        5516825                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        3509461                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        58024                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker        43657                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        1724189                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1036223                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker       155625                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        59564                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst        3891179                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data        1432109                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker       296265                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker       110618                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst        4655430                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data        2558235                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           25324991                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007984                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012629                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.005601                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007238                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003329                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.007353                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003423                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008480                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006284                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.785093                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.791095                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.783113                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.781538                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.784475                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.666667                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.666667                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.226454                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.206348                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.194439                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.189681                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.207592                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006557                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005899                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006415                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.006164                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.006334                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045070                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.038630                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.036756                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.036301                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.040269                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.569494                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.165266                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data     0.197599                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu3.data     0.218556                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.402303                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007984                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012629                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006557                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.087314                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.005601                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.007238                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005899                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.077932                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003329                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.007353                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.006415                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.075184                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003423                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.itb.walker     0.008480                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.006164                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.071534                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.030963                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007984                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012629                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006557                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.087314                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.005601                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.007238                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005899                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.077932                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003329                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.007353                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.006415                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.075184                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003423                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.itb.walker     0.008480                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.006164                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.071534                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.030963                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84289.230769                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 85376.582278                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89315.637066                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 87270.547945                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87119.329389                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88416.844350                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 49290.686586                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15132.035119                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15994.274137                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15750.492126                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  9329.803151                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        40500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        40500                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80578.941186                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80739.762190                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98057.641026                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 48991.026468                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80907.030823                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83233.029547                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85040.519850                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 54306.026466                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83283.275831                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83343.424528                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88947.291233                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 47620.342580                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79647.368421                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88000.934676                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107335.958241                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 22501.844485                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84388.489209                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86176.470588                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 80907.030823                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 81641.218289                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84916.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 86968.319559                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 83233.029547                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 81716.409331                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87772.102161                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88604.613734                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 85040.519850                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 94436.058289                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 49222.433371                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84388.489209                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86176.470588                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 80907.030823                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 81641.218289                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84916.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 86968.319559                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 83233.029547                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 81716.409331                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87772.102161                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88604.613734                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 85040.519850                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 94436.058289                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 49222.433371                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80601.953858                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81311.158103                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98007.118763                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 49408.261263                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80749.631305                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83179.079364                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85312.266945                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 53454.126376                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82693.790988                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83641.559910                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88774.128387                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 46385.752316                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79397.608538                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88042.152984                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107872.175338                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 22470.464717                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84289.230769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 85376.582278                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80749.631305                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 81395.870225                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89315.637066                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker 87270.547945                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 83179.079364                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 82172.794903                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87119.329389                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88416.844350                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 85312.266945                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 94397.978142                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 48908.292068                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84289.230769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 85376.582278                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80749.631305                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 81395.870225                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89315.637066                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 87270.547945                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 83179.079364                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 82172.794903                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87119.329389                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88416.844350                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 85312.266945                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 94397.978142                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 48908.292068                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2807,342 +2811,342 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              991802                       # number of writebacks
-system.l2c.writebacks::total                   991802                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks              984548                       # number of writebacks
+system.l2c.writebacks::total                   984548                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.itb.walker            9                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                10                       # number of ReadReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data            3                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu3.data            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.dtb.walker            9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.itb.walker            9                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.data              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 27                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.dtb.walker            9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                 16                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.dtb.walker            1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.itb.walker            9                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.data             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                27                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          417                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          408                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          426                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          363                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1009                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.itb.walker          921                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            3544                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks          456                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total          456                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4585                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         5739                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data         9908                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        20232                       # number of UpgradeReq MSHR misses
+system.l2c.overall_mshr_hits::total                16                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          325                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          316                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          518                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          438                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1013                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.itb.walker          929                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            3539                       # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks          453                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total          453                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4442                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data         5676                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data        10160                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        20278                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        51076                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        66860                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data       112125                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        230061                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10966                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        27651                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        28084                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        66701                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        33042                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        40131                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data        73979                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       147152                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data        19000                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu2.data        28887                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu3.data        66669                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       114556                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker          417                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker          408                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        10966                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        84118                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker          426                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker          363                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst        27651                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data       106991                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker         1009                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.itb.walker          921                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst        28084                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data       186104                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           447458                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker          417                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker          408                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        10966                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        84118                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker          426                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker          363                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst        27651                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data       106991                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker         1009                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.itb.walker          921                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst        28084                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data       186104                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          447458                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6330                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         4869                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data         4820                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        16019                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5775                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4397                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data         4483                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        14655                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        12105                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data         9266                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data         9303                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        30674                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     31020000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     31080000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     31914500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     27939500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker     78750500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker     72708500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    273413000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     94704500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    119085000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    205591000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    419380500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        91500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        91500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3604890000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4729660500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   9873463000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  18208013500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    777566500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2024966500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   2107511500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   4910044500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   2421426000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   2943444000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data   5840517500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  11205387500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1323300000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   2253213000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   6489291000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  10065804000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     31020000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     31080000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    777566500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   6026316000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     31914500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     27939500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst   2024966500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   7673104500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker     78750500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.itb.walker     72708500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst   2107511500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data  15713980500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  34596858500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     31020000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     31080000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    777566500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   6026316000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     31914500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     27939500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst   2024966500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   7673104500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker     78750500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.itb.walker     72708500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst   2107511500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data  15713980500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  34596858500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1036307000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    760536500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data    777950000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   2574793500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    974195500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    694163000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data    758681500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2427040000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2010502500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1454699500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1536631500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5001833500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007473                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009637                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002698                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.006078                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003361                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008146                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.003527                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        50106                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        67861                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data       111466                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        229433                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10171                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        24961                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        28694                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        63826                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data        30649                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        39808                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data        71531                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       141988                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data        17897                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu2.data        30330                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu3.data        64698                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total       112925                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker          325                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker          316                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        10171                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        80755                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker          518                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker          438                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst        24961                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data       107669                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.dtb.walker         1013                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.itb.walker          929                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst        28694                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data       182997                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           438786                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker          325                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker          316                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        10171                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        80755                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker          518                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.itb.walker          438                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst        24961                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data       107669                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.dtb.walker         1013                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.itb.walker          929                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst        28694                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data       182997                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          438786                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5947                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         4621                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3.data         4770                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        15338                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5383                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4193                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3.data         4437                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        14013                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        11330                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data         8814                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3.data         9207                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        29351                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     24144000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     23819000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     41085500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     33844500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker     78151000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker     72937000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    273981000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     91747500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    117799500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    210807500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    420354500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        92000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        92000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3537581500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4839246500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   9809801500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  18186629500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    719594500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   1826623000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   2161084000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   4707301500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   2227992000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   2931602000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data   5634867500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  10794461500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1242009000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   2367018500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   6332134000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total   9941161500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     24144000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     23819000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    719594500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   5765573500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     41085500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     33844500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   1826623000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   7770848500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker     78151000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.itb.walker     72937000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst   2161084000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data  15444669000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  33962373500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     24144000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     23819000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    719594500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   5765573500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     41085500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     33844500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   1826623000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   7770848500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker     78151000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.itb.walker     72937000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst   2161084000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data  15444669000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  33962373500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    946766500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    728700000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data    770595000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   2446061500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    881146000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    669497000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data    751355000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2301998000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1827912500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1398197000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1521950000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4748059500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.005601                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007238                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003329                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.007353                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003419                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008398                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.003534                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.786180                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.788974                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.781203                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.462805                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.209739                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.194043                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.192083                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.115350                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006465                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.007063                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.006007                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.004217                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041739                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.036471                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.038093                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.022521                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.180105                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.186117                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.225118                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.093499                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.007473                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.009637                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006465                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.081261                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002698                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.006078                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.007063                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.074046                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003361                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008146                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.006007                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.073682                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.017652                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.007473                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.009637                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006465                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.081261                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002698                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.006078                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.007063                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.074046                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003361                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008146                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.006007                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.073682                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.017652                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77148.137698                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20655.288986                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20750.130685                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        20750                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20728.573547                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        45750                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        45750                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70578.941186                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70739.762190                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88057.641026                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 79144.285646                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70907.030823                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73233.029547                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75043.138442                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73612.756930                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73283.275831                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73345.892203                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78948.316414                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76148.387382                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69647.368421                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78000.934676                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97335.958241                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 87867.977234                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70907.030823                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71641.218289                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73233.029547                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71717.289305                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75043.138442                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84436.554292                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 77318.672367                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70907.030823                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71641.218289                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73233.029547                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71717.289305                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75043.138442                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84436.554292                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 77318.672367                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163713.586098                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 156199.733005                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161400.414938                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160733.722455                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168691.861472                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 157871.958153                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169235.221950                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165611.736609                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166088.599752                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156993.254910                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165175.910996                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 163064.272674                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.791095                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.783113                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.781538                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.466676                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.666667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.666667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.206348                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.194439                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.189681                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.114899                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005899                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006415                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.006164                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.004043                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.038630                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.036754                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.036299                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021713                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.165266                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.197599                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.218556                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.092213                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.005601                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007238                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005899                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.077932                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003329                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.007353                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006415                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.075182                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003419                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008398                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.006164                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.071533                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.017326                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.005601                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007238                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005899                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.077932                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003329                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.007353                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006415                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.075182                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003419                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008398                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.006164                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.071533                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.017326                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 77417.632099                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20654.547501                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20753.964059                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20748.769685                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20729.583785                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        46000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        46000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70601.953858                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71311.158103                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88007.118763                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 79267.714322                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70749.631305                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73179.079364                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75314.839339                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73752.099458                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72693.790988                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73643.538987                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78775.181390                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76023.759050                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69397.608538                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78042.152984                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97872.175338                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88033.309719                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70749.631305                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71395.870225                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73179.079364                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72173.499336                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75314.839339                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84398.481942                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 77400.768256                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74289.230769                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75376.582278                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70749.631305                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71395.870225                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 79315.637066                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77270.547945                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73179.079364                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72173.499336                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77148.075025                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78511.302476                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75314.839339                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84398.481942                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 77400.768256                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159200.689423                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157693.140013                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161550.314465                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159477.213457                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163690.507152                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159670.164560                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169338.517016                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 164275.886677                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161333.848191                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158633.651010                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165303.573368                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 161768.236176                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               76739                       # Transaction distribution
-system.membus.trans_dist::ReadResp             460749                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33648                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33648                       # Transaction distribution
-system.membus.trans_dist::Writeback           1098433                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           213962                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34949                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76737                       # Transaction distribution
+system.membus.trans_dist::ReadResp             455193                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33647                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33647                       # Transaction distribution
+system.membus.trans_dist::Writeback           1091179                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           208864                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34786                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34951                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            916210                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           916210                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        384010                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           34788                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            906494                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           906494                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        378456                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           62                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3942227                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4071627                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343658                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       343658                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4415285                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6756                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3898162                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4027556                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       345368                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       345368                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4372924                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155706                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13524                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    146305120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    146474546                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7302336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7302336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               153776882                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1554                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2866082                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13512                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    144864864                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    145034278                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7356288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7356288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               152390566                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              691                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2837421                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2866082    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2837421    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2866082                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            51617000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2837421                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            49386500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                2000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1694500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1639500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          3281296074                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          3223716711                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3058096264                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3001422636                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          103726218                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           89214499                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3186,64 +3190,64 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq            1507075                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23857599                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33648                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33648                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          8015609                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict        18152591                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           43716                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          43720                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1994458                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1994458                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      15815989                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6539025                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1270619                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1225211                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47531663                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29482635                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       826355                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1753245                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              79593898                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1012390548                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1027984926                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2989368                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6204744                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2049569586                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          999459                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         53440188                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.040190                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.196406                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            1500754                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          23827950                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33647                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33647                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          8025102                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict        18108882                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           43452                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             3                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          43455                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1996830                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1996830                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      15787707                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6541408                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1269700                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1224612                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47446864                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29502710                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       824705                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1741139                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              79515418                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1010580372                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1029542098                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2979800                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6154816                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2049257086                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          987636                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         53377948                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.039876                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.195669                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               51292404     95.98%     95.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                2147784      4.02%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               51249425     96.01%     96.01% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                2128523      3.99%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           53440188                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        20656393480                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           53377948                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        20681814986                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           738000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           436500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       15434172491                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       15410337923                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        7824329236                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        7854888294                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         294252739                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         293722728                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         716654510                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         713107905                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
index 5de46231b..11d96493e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -204,7 +204,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -587,7 +587,7 @@ opLat=3
 pipelined=false
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1261,7 +1261,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -1296,7 +1296,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1711,9 +1711,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index b9292423f..b59b70a33 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,159 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.321386                       # Number of seconds simulated
-sim_ticks                                51321386217000                       # Number of ticks simulated
-final_tick                               51321386217000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.241896                       # Number of seconds simulated
+sim_ticks                                51241895910000                       # Number of ticks simulated
+final_tick                               51241895910000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 134164                       # Simulator instruction rate (inst/s)
-host_op_rate                                   157647                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7630777532                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 687808                       # Number of bytes of host memory used
-host_seconds                                  6725.58                       # Real time elapsed on the host
-sim_insts                                   902332774                       # Number of instructions simulated
-sim_ops                                    1060266688                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  95627                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112378                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5423934154                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 730628                       # Number of bytes of host memory used
+host_seconds                                  9447.37                       # Real time elapsed on the host
+sim_insts                                   903425057                       # Number of instructions simulated
+sim_ops                                    1061671663                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       154240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       142464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4107136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         45245848                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       165376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       158016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3334400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         43223216                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        435264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             96965960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4107136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3334400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7441536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     82289920                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       165376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       148160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3796224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         45159832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       160832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       148224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3625536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         44632368                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        406656                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             98243208                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3796224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3625536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7421760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     83214784                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          82310500                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2410                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2226                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             64174                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            706974                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2584                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2469                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             52100                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            675368                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6801                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1515106                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1285780                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          83235364                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2584                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2315                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             59316                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            705630                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2513                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2316                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56649                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            697386                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6354                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1535063                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1300231                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1288353                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3005                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2776                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               80028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              881618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3222                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3079                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               64971                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              842207                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1889387                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          80028                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          64971                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             144999                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1603424                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1603825                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1603424                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3005                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2776                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              80028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             882019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3222                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              64971                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             842207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3493212                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1515106                       # Number of read requests accepted
-system.physmem.writeReqs                      1288353                       # Number of write requests accepted
-system.physmem.readBursts                     1515106                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1288353                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 96901440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     65344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  82309952                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  96965960                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               82310500                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1021                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         144011                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               91435                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               93225                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               89718                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               87919                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               92611                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              102433                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               93232                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               90056                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               87362                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              117909                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              95229                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              97284                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              90073                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             103730                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              91691                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              90178                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               77827                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               79309                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               76608                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               77829                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               80050                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               85847                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               79718                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               79449                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               76360                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               83802                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              81643                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              83145                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              78123                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              87627                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              79500                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              79256                       # Per bank write bursts
+system.physmem.num_writes::total              1302804                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2891                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               74084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              881307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               70753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              871013                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1917244                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          74084                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          70753                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             144838                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1623960                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1624362                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1623960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              74084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             881708                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              70753                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             871013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7936                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3541605                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1535063                       # Number of read requests accepted
+system.physmem.writeReqs                      1302804                       # Number of write requests accepted
+system.physmem.readBursts                     1535063                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1302804                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 98199040                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     44992                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  83234496                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  98243208                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               83235364                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      703                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2263                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         144188                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               94050                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               94624                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               91446                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               92243                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               98717                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              106707                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               93934                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               93123                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               90055                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              118648                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              94680                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              96202                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              91550                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              95334                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              93205                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              89842                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               79067                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               80858                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               78439                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               80901                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               84568                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               88799                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               79324                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               81423                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               78366                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               84879                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              80434                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              83122                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              79318                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              82355                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              80105                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              78581                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51321385112000                       # Total gap between requests
+system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51241894805000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1515091                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1535048                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1285780                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    688629                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    426852                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    228074                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    164413                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       987                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       875                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       956                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      461                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      156                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      128                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      104                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1300231                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    696212                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    434080                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    231480                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    166858                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       497                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       510                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       499                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       804                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       871                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      153                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       98                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                       85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       62                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -162,189 +162,183 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       745                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       743                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       734                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                       736                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                       737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      729                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                      723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    13812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    16283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    29465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    43941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    62844                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    76168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    76695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    80163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    82135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    85619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    84213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    87116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    83567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    96056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   103672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    81346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    84582                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    77173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      255                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       590002                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.746442                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.840046                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.017877                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         235290     39.88%     39.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       136180     23.08%     62.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        56828      9.63%     72.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27605      4.68%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        24232      4.11%     81.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13797      2.34%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        13359      2.26%     85.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9785      1.66%     87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        72926     12.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         590002                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         74241                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.393489                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      234.888851                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          74237     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    14109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    16691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    29697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    44633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    65149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    77035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    77508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    81035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    83877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    86632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    85119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    87954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    84437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    96180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   104378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    81922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    85007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    77822                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       92                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       599076                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.854983                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.463010                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.270126                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         239456     39.97%     39.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       137779     23.00%     62.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        58288      9.73%     72.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28412      4.74%     77.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        23965      4.00%     81.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        14114      2.36%     83.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        13744      2.29%     86.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        10019      1.67%     87.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        73299     12.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         599076                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         75110                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.428012                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      233.528819                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          75106     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::61440-63487            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           74241                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         74241                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.323218                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.863934                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.335765                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                39      0.05%      0.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                11      0.01%      0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               20      0.03%      0.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              65      0.09%      0.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           70112     94.44%     94.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1316      1.77%     96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             568      0.77%     97.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             346      0.47%     97.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             342      0.46%     98.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             528      0.71%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             134      0.18%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              37      0.05%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              41      0.06%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              27      0.04%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              42      0.06%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              26      0.04%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             396      0.53%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              32      0.04%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              46      0.06%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              38      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               9      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           75110                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         75110                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.315124                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.869848                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.130210                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                32      0.04%      0.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                20      0.03%      0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               14      0.02%      0.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              62      0.08%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           70906     94.40%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1379      1.84%     96.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             596      0.79%     97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             313      0.42%     97.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             370      0.49%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             506      0.67%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             145      0.19%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              36      0.05%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              45      0.06%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              34      0.05%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              32      0.04%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              33      0.04%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             412      0.55%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              33      0.04%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              44      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              12      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               8      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            24      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             4      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           74241                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    44116098728                       # Total ticks spent queuing
-system.physmem.totMemAccLat               72505192478                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   7570425000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29137.13                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::112-115             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            27      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           75110                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    44722536913                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73491786913                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7671800000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29147.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47887.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.60                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47897.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.92                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.13                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1245847                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    964327                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        10.66                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1262545                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    973277                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.28                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18306451.11                       # Average gap between requests
-system.physmem.pageHitRate                      78.93                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2222337600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1212585000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5776859400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4125407760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352063391040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1232605432755                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29711598339000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34309604352555                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.524518                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49427675587817                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713733840000                       # Time in different power states
+system.physmem.writeRowHitRate                  74.84                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18056482.14                       # Average gap between requests
+system.physmem.pageHitRate                      78.87                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2313095400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1262105625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5965736400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4233895920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3346871502000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1235329874865                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29661514581750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34257490791960                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.544567                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49344314821819                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1711079500000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    179976420183                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    186501218681                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2238077520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1221173250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6032956800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4208474880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352063391040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1237235987925                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29707536448500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34310536509915                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.542681                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49420862619804                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713733840000                       # Time in different power states
+system.physmem_1.actEnergy                 2215919160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1209082875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6002224800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4193596800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3346871502000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1231628029245                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29664761814750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34256882169630                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.532689                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49349717648088                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1711079500000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    186788845196                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    181098330662                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -374,15 +368,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              132571032                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         90050105                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5878539                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            90490581                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               64975080                       # Number of BTB hits
+system.cpu0.branchPred.lookups              131237057                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         89167205                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5638568                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            88557097                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               64192129                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.803142                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17318147                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            190057                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.486713                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17175820                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            188370                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -413,94 +407,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   913008                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               913008                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16692                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        92976                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       560771                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       352237                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2376.777567                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 13703.858808                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-32767       344408     97.78%     97.78% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-65535         5384      1.53%     99.31% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-98303          983      0.28%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-131071          725      0.21%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-163839          276      0.08%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::163840-196607          169      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-229375           94      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::229376-262143           47      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-294911           59      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::294912-327679           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-360447           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::360448-393215           25      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-425983           25      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::425984-458751            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-491519            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::491520-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       352237                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       421207                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22517.986406                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18384.767938                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 16267.103719                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       412281     97.88%     97.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         8071      1.92%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          392      0.09%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          363      0.09%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           55      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       421207                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 353008884868                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.117411                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.682149                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 352021835868     99.72%     99.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    541843500      0.15%     99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    193463500      0.05%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    118741500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     46634500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     24285000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     23543000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     31748500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      6046000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       436000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        56500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47        38500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        27500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55       185000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 353008884868                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        92977     84.78%     84.78% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        16692     15.22%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       109669                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       913008                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   905525                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               905525                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16897                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        92924                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       558822                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       346703                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2425.430412                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 13757.880539                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       344211     99.28%     99.28% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1816      0.52%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          412      0.12%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          106      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           81      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           35      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           36      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       346703                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       421563                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22489.281555                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18275.838186                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16656.658640                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       412599     97.87%     97.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         7935      1.88%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          523      0.12%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          370      0.09%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           86      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       421563                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 359417936788                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.126321                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.679023                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 358421610788     99.72%     99.72% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    547811500      0.15%     99.88% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    199809500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    118742000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     45429500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     23353000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     23408000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     31953500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      5493500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       315500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        10000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 359417936788                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        92925     84.61%     84.61% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        16897     15.39%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       109822                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       905525                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       913008                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       109669                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       905525                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       109822                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       109669                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total      1022677                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       109822                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total      1015347                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   104802286                       # DTB read hits
-system.cpu0.dtb.read_misses                    628192                       # DTB read misses
-system.cpu0.dtb.write_hits                   81730320                       # DTB write hits
-system.cpu0.dtb.write_misses                   284816                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1079                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   104324024                       # DTB read hits
+system.cpu0.dtb.read_misses                    622142                       # DTB read misses
+system.cpu0.dtb.write_hits                   81549080                       # DTB write hits
+system.cpu0.dtb.write_misses                   283383                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1078                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              22185                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    501                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   54383                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      188                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9307                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              22319                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    542                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   56138                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      214                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9448                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    56122                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               105430478                       # DTB read accesses
-system.cpu0.dtb.write_accesses               82015136                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    55690                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               104946166                       # DTB read accesses
+system.cpu0.dtb.write_accesses               81832463                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        186532606                       # DTB hits
-system.cpu0.dtb.misses                         913008                       # DTB misses
-system.cpu0.dtb.accesses                    187445614                       # DTB accesses
+system.cpu0.dtb.hits                        185873104                       # DTB hits
+system.cpu0.dtb.misses                         905525                       # DTB misses
+system.cpu0.dtb.accesses                    186778629                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -530,831 +514,828 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                   102934                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               102934                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2830                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69670                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        14211                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        88723                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1670.198257                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  9993.098637                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        87793     98.95%     98.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          509      0.57%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          243      0.27%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           94      0.11%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839           34      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           21      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        88723                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        86711                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 27827.271050                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23655.790569                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 18399.370737                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        84751     97.74%     97.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1686      1.94%     99.68% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          179      0.21%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           53      0.06%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        86711                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 499035191932                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.085193                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -42443239012     -8.51%     -8.51% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   541415505444    108.49%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       55393500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        6761000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         722500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          48000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6            500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 499035191932                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        69670     96.10%     96.10% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2830      3.90%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        72500                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                   104491                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               104491                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2977                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        70833                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        14071                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        90420                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1597.942933                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  9019.721733                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        89473     98.95%     98.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          526      0.58%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          276      0.31%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071           90      0.10%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839           22      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           16      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        90420                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        87881                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 27928.608004                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23671.030961                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18442.594011                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        85773     97.60%     97.60% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1788      2.03%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          210      0.24%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           67      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           26      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        87881                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 587048610976                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.928143                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.258729                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    42249088256      7.20%      7.20% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   544740674220     92.79%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       52941500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        5346000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         541000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5           5000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6          15000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 587048610976                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        70833     95.97%     95.97% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2977      4.03%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        73810                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102934                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102934                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       104491                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       104491                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72500                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72500                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       175434                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    95094277                       # ITB inst hits
-system.cpu0.itb.inst_misses                    102934                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        73810                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        73810                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       178301                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    93910274                       # ITB inst hits
+system.cpu0.itb.inst_misses                    104491                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1079                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1078                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              22185                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    501                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   40091                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              22319                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    542                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   41605                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   207907                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   209342                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                95197211                       # ITB inst accesses
-system.cpu0.itb.hits                         95094277                       # DTB hits
-system.cpu0.itb.misses                         102934                       # DTB misses
-system.cpu0.itb.accesses                     95197211                       # DTB accesses
-system.cpu0.numCycles                       675702202                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                94014765                       # ITB inst accesses
+system.cpu0.itb.hits                         93910274                       # DTB hits
+system.cpu0.itb.misses                         104491                       # DTB misses
+system.cpu0.itb.accesses                     94014765                       # DTB accesses
+system.cpu0.numCycles                       672837873                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         244757501                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     589419880                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  132571032                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          82293227                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    391738714                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13356245                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2509355                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               22606                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             4900                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5469917                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       167540                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         2725                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 94868898                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3621980                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  41300                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         651351111                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.059349                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.306953                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         242596168                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     583871358                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  131237057                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          81367949                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    391672300                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               12912795                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2559887                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               21371                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             5907                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      5496890                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       161597                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         2291                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 93683695                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3482115                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  41656                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         648972539                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.054070                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.303352                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               505677761     77.64%     77.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18279909      2.81%     80.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18243298      2.80%     83.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13516535      2.08%     85.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28852465      4.43%     89.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 8999693      1.38%     91.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9719421      1.49%     92.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8528805      1.31%     93.93% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                39533224      6.07%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               504751488     77.78%     77.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                18012631      2.78%     80.55% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                17993966      2.77%     83.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13374247      2.06%     85.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28570124      4.40%     89.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8915108      1.37%     91.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9700378      1.49%     92.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8355653      1.29%     93.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                39298944      6.06%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           651351111                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.196197                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.872307                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               198764731                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            327769223                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105831567                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13682981                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5300378                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19660361                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1397395                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             643175990                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4312729                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5300378                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               206434504                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               26397501                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     257870314                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                111703786                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             43642083                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             627780362                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                81911                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1880696                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1582827                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              24120192                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3699                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          601307944                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            969598831                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       742471294                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           750947                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            504947564                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                96360375                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15500464                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13524428                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 76866665                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           101145902                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           86060501                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13628383                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14576675                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 595266457                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15567772                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                595602490                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           860155                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       81220997                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     52302062                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        356361                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    651351111                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.914411                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.641831                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           648972539                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.195050                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.867774                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               196814484                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            328839067                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                104545498                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13685712                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5085585                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19454701                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1390261                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             638009836                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4286683                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5085585                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               204391005                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               27392255                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     259209600                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                110517948                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             42373779                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             623249202                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                71579                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1876177                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1615058                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              22749976                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3905                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          596805281                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            963507479                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       737465972                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           746816                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            504819765                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                91985511                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15562034                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13603964                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 76990444                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           100130044                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           85693466                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13752433                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14485683                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 591325254                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15668453                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                593122197                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           836144                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       77301127                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     49722084                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        361977                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    648972539                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.913940                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.642087                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          416907124     64.01%     64.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           99553383     15.28%     79.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43434757      6.67%     85.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           30928180      4.75%     90.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           22872426      3.51%     94.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           16003542      2.46%     96.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           10950121      1.68%     98.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6425711      0.99%     99.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4275867      0.66%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          415433099     64.01%     64.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           99398694     15.32%     79.33% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           43154141      6.65%     85.98% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           30671240      4.73%     90.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           22754813      3.51%     94.21% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           15949435      2.46%     96.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10913282      1.68%     98.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6427298      0.99%     99.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4270537      0.66%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      651351111                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      648972539                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                2977313     25.58%     25.58% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 21726      0.19%     25.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   2146      0.02%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               1      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4737742     40.71%     66.50% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3899084     33.50%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                2981405     25.56%     25.56% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 22602      0.19%     25.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2507      0.02%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               1      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4779561     40.98%     66.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3875984     33.24%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               69      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            404218599     67.87%     67.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1425375      0.24%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                67506      0.01%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 50      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         58410      0.01%     68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           106977397     17.96%     86.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82855084     13.91%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               47      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            402622584     67.88%     67.88% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1399505      0.24%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                65721      0.01%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                 48      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   5      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         57538      0.01%     68.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           106372763     17.93%     86.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           82603986     13.93%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             595602490                       # Type of FU issued
-system.cpu0.iq.rate                          0.881457                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11638012                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019540                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1854047614                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        692214073                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    573874162                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1006644                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            498985                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       447097                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             606702343                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 538090                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4757420                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             593122197                       # Type of FU issued
+system.cpu0.iq.rate                          0.881523                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11662060                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019662                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1846708499                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        684493895                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    571889273                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1006638                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            498386                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       446935                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             604246281                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 537929                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4762645                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16585910                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        22662                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       668240                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      9092320                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     15679208                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        19927                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       708487                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8639603                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3863731                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      7820378                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3917286                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      7883426                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5300378                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15293530                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              9669423                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          610970772                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1799898                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            101145902                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            86060501                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13228626                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                242900                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              9335617                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        668240                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2719159                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2323934                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5043093                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            588743474                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            104791307                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5960112                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5085585                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15009758                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles             10941422                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          607129936                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1704783                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            100130044                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            85693466                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13307217                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                240581                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents             10607814                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        708487                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2549086                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2233115                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4782201                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            586634430                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            104313037                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          5594967                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       136543                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   186525171                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               109265890                       # Number of branches executed
-system.cpu0.iew.exec_stores                  81733864                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.871306                       # Inst execution rate
-system.cpu0.iew.wb_sent                     575597633                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    574321259                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                283300170                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                492230600                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       136229                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   185865379                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               108795926                       # Number of branches executed
+system.cpu0.iew.exec_stores                  81552342                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.871881                       # Inst execution rate
+system.cpu0.iew.wb_sent                     573547999                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    572336208                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                282398495                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                490722197                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.849962                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575544                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.850630                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575475                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       81268346                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15211411                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4500525                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    637573218                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.830670                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.824266                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       77341674                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15306476                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4267486                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    635759269                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.833165                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.828636                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    442173264     69.35%     69.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     97173464     15.24%     84.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     33154077      5.20%     89.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15182673      2.38%     92.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10793922      1.69%     93.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6469162      1.01%     94.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6019139      0.94%     95.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3912878      0.61%     96.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22694639      3.56%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    440698390     69.32%     69.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     96997007     15.26%     84.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     32966862      5.19%     89.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     15106149      2.38%     92.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10791866      1.70%     93.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6453132      1.02%     94.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6019295      0.95%     95.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3918041      0.62%     96.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22808527      3.59%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    637573218                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           450633299                       # Number of instructions committed
-system.cpu0.commit.committedOps             529613227                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    635759269                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           450546917                       # Number of instructions committed
+system.cpu0.commit.committedOps             529692575                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     161528172                       # Number of memory references committed
-system.cpu0.commit.loads                     84559991                       # Number of loads committed
-system.cpu0.commit.membars                    3687184                       # Number of memory barriers committed
-system.cpu0.commit.branches                 100678778                       # Number of branches committed
-system.cpu0.commit.fp_insts                    428537                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                486019598                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13276351                       # Number of function calls committed.
+system.cpu0.commit.refs                     161504698                       # Number of memory references committed
+system.cpu0.commit.loads                     84450835                       # Number of loads committed
+system.cpu0.commit.membars                    3736231                       # Number of memory barriers committed
+system.cpu0.commit.branches                 100681556                       # Number of branches committed
+system.cpu0.commit.fp_insts                    429176                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                486199452                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13322938                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       366882155     69.27%     69.27% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1103700      0.21%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           50072      0.01%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        49128      0.01%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84559991     15.97%     85.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      76968181     14.53%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       366991615     69.28%     69.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1098704      0.21%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           48820      0.01%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        48738      0.01%     69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       84450835     15.94%     85.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      77053863     14.55%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        529613227                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22694639                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1221719500                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1235563732                       # The number of ROB writes
-system.cpu0.timesIdled                        4062222                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       24351091                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 46889510422                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  450633299                       # Number of Instructions Simulated
-system.cpu0.committedOps                    529613227                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.499450                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.499450                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.666911                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.666911                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               694532138                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              409756453                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   813886                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  470480                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                126655644                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               127915254                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1202729248                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15348526                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10661519                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.983500                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          305118964                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10662031                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.617340                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        529692575                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22808527                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1215947592                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1227300023                       # The number of ROB writes
+system.cpu0.timesIdled                        4042817                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       23865334                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 48376378387                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  450546917                       # Number of Instructions Simulated
+system.cpu0.committedOps                    529692575                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.493380                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.493380                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.669622                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.669622                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               692384326                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              408324633                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   809160                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  477572                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                126161613                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               127342866                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1198291262                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15447790                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10676503                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.983474                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          304546323                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10677015                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.523545                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1659069500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   285.071495                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   226.912005                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.556780                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.443188                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   293.453166                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   218.530308                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.573151                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.426817                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1346452186                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1346452186                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80589927                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     80681589                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      161271516                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67520868                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     67884168                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     135405036                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204627                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       201539                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       406166                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       174874                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       149966                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       324840                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1793684                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1773233                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3566917                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2041252                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2056052                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4097304                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    148110795                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    148565757                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       296676552                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    148315422                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    148767296                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      297082718                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6173656                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6486433                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12660089                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6585609                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6413253                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     12998862                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       647829                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       671589                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1319418                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       637368                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       603972                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1241340                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       307807                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       348230                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       656037                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            8                       # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses       1344556090                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1344556090                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79999086                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     80528903                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      160527989                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67561475                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     67996777                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     135558252                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       203785                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202222                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       406007                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       172640                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       153185                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       325825                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1797141                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1773094                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3570235                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2068264                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2042534                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4110798                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147560561                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    148525680                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       296086241                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147764346                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    148727902                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      296492248                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6141795                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      6528764                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total     12670559                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6608479                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      6465845                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total     13074324                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       649478                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       677361                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1326839                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       635249                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       605487                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1240736                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       328601                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       329591                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       658192                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            7                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            3                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     12759265                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12899686                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25658951                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13407094                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13571275                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     26978369                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  95102935500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  99484470500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 194587406000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227327993853                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 219936608514                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 447264602367                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  33983690404                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  32156071893                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  66139762297                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4002448500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4417133500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8419582000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       243500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     12750274                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     12994609                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      25744883                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     13399752                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data     13671970                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     27071722                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  94431381500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 100570450000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 195001831500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 229012929937                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 223645956318                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 452658886255                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  33967464475                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  32913724847                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  66881189322                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4162185500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4276509000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   8438694500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       161500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       108000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       351500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 322430929353                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 319421079014                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 641852008367                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 322430929353                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 319421079014                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 641852008367                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     86763583                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     87168022                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    173931605                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74106477                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     74297421                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    148403898                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       852456                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       873128                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1725584                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       812242                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       753938                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1566180                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2101491                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2121463                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4222954                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2041260                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2056055                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4097315                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    160870060                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    161465443                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    322335503                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    161722516                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    162338571                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    324061087                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071155                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074413                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.072788                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.088867                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.086319                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.087591                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759956                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.769176                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.764621                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.784702                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.801090                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792591                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.146471                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.164146                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.155350                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_latency::total       269500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 323444311437                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 324216406318                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 647660717755                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 323444311437                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 324216406318                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 647660717755                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     86140881                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     87057667                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    173198548                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     74169954                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     74462622                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    148632576                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853263                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       879583                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1732846                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       807889                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       758672                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1566561                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2125742                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2102685                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4228427                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2068271                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2042537                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4110808                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    160310835                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    161520289                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    321831124                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    161164098                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    162399872                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    323563970                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071299                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074994                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.073156                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.089099                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.086833                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.087964                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.761170                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.770093                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765699                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.786307                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.798088                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792013                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.154582                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.156748                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.155659                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.079314                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079891                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.079603                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.082902                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.083599                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.083251                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15404.637949                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15337.315671                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15370.145186                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34518.902330                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34294.079543                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 34407.981435                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53318.789779                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 53240.997750                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53280.940191                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13003.110715                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12684.528903                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12834.004789                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 30437.500000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.079535                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.080452                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.079995                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.083144                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.084187                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.083667                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15375.208958                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15404.209740                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15390.152202                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34654.408365                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34588.821155                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 34621.972521                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53471.102631                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 54359.094162                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53904.448103                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12666.381113                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12975.199566                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12821.022589                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23071.428571                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        36000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 31954.545455                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25270.337230                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24761.926687                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25014.740796                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24049.277894                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23536.556367                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 23791.357008                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     66975280                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        45752                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3575735                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1017                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.730493                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    44.987217                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        26950                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25367.636134                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24950.070165                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25156.871669                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24138.081917                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23713.949513                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23923.883296                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     67819583                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        50977                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3590540                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1007                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.888408                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    50.622642                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8160945                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8160945                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3346545                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3573146                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      6919691                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5483385                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5330407                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10813792                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3566                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3327                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         6893                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       188282                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       213819                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       402101                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8829930                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8903553                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17733483                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8829930                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8903553                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17733483                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2827111                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2913287                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5740398                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1102224                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1082846                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2185070                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       638719                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       656171                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1294890                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       633802                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       600645                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1234447                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       119525                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       134411                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253936                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            8                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      8163245                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8163245                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3314208                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3616670                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      6930878                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5502274                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5376459                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10878733                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3693                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3290                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6983                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       202459                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       202911                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       405370                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8816482                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      8993129                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17809611                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8816482                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      8993129                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17809611                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2827587                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2912094                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5739681                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1106205                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1089386                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2195591                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       640410                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       661534                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1301944                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       631556                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       602197                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1233753                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126142                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       126680                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       252822                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            7                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3929335                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3996133                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7925468                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4568054                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4652304                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9220358                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17396                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16284                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33680                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18911                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14786                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        36307                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        31070                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67377                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43970285000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  44965591500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  88935876500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39469232389                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  38108394120                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  77577626509                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10196891500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11887921500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22084813000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  33197271404                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  31430048393                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  64627319797                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1640365500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1815773000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3456138500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       235500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3933792                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      4001480                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7935272                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4574202                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4663014                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9237216                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17080                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16596                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33676                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18113                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        15582                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33695                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35193                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        32178                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67371                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43873755000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  45263684000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  89137439000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39703297752                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  38710304225                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  78413601977                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10229018500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12106764000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22335782500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  33180093475                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  32187853347                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  65367946822                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1698558000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1735409000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3433967000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       154500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       105000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       340500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83439517389                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83073985620                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 166513503009                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  93636408889                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  94961907120                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 188598316009                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3034885000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2806255000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5841140000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3049818991                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2643724500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5693543491                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6084703991                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5449979500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11534683491                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032584                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033422                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033004                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014874                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014574                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014724                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.749269                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.751518                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.750407                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.780312                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.796677                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.788190                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056876                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063358                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060132                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       259500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83577052752                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83973988225                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 167551040977                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  93806071252                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  96080752225                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 189886823477                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2986588500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2854625000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5841213500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2919463491                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2774139500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5693602991                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5906051991                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5628764500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11534816491                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032825                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033450                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033139                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014914                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014630                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014772                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750542                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.752100                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.751333                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.781736                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.793751                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787555                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059340                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060247                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059791                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024426                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024749                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024588                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028246                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028658                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028453                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15553.080512                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15434.659029                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15492.980887                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35808.721629                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35192.810538                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35503.497146                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15964.597108                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18117.108955                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17055.358370                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52377.984613                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 52327.162289                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52353.255990                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13724.036812                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13509.110117                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13610.273849                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 29437.500000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024539                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024774                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024657                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028382                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028713                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028548                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15516.323636                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15543.345785                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15530.033638                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35891.446660                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35534.057006                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35714.120698                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15972.608954                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18301.045751                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17155.716759                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52537.056848                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 53450.703585                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52983.009421                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13465.443706                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13699.155352                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13582.548196                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22071.428571                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        35000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30954.545455                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21235.022565                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20788.593778                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21009.926860                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20498.095883                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20411.801791                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20454.554586                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174458.783628                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172332.043724                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173430.522565                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161272.222040                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178799.168132                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168962.919281                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167590.381772                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175409.703894                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171196.157309                       # average overall mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        25950                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21245.925751                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20985.732335                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21114.719316                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20507.636360                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20604.860338                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20556.715733                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174858.811475                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172006.808870                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173453.305024                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161180.560426                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178034.879990                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168974.714082                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167818.941011                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174925.865498                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171213.378026                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16142168                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.947517                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          172883065                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16142680                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.709688                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      16340342500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   273.082606                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   238.864911                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.533364                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.466533                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         16087139                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.947221                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          170921783                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16087651                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.624409                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      16333976500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   275.838488                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   236.108732                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.538747                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.461150                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999897                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           76                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           65                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        206401666                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       206401666                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     86191123                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     86691942                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      172883065                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     86191123                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     86691942                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       172883065                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     86191123                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     86691942                       # number of overall hits
-system.cpu0.icache.overall_hits::total      172883065                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8665288                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8710490                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17375778                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8665288                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8710490                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17375778                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8665288                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8710490                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17375778                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 113689396380                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113502001896                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 227191398276                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 113689396380                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 113502001896                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 227191398276                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 113689396380                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 113502001896                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 227191398276                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     94856411                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     95402432                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    190258843                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     94856411                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     95402432                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    190258843                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     94856411                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     95402432                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    190258843                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.091352                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091303                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.091327                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.091352                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.091303                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.091327                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.091352                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091303                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.091327                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13120.094379                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13030.495632                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13075.178463                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13120.094379                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13030.495632                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13075.178463                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13120.094379                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13030.495632                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13075.178463                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        86637                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        204325556                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       204325556                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     85081339                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     85840444                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      170921783                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     85081339                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     85840444                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       170921783                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     85081339                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     85840444                       # number of overall hits
+system.cpu0.icache.overall_hits::total      170921783                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8589868                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      8726123                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     17315991                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      8589868                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      8726123                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      17315991                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      8589868                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      8726123                       # number of overall misses
+system.cpu0.icache.overall_misses::total     17315991                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 112329905402                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 114108527365                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 226438432767                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 112329905402                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 114108527365                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 226438432767                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 112329905402                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 114108527365                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 226438432767                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     93671207                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     94566567                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    188237774                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     93671207                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     94566567                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    188237774                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     93671207                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     94566567                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    188237774                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.091702                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.092275                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.091990                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.091702                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.092275                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.091990                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.091702                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.092275                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.091990                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13077.023466                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13076.658141                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13076.839366                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13077.023466                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13076.658141                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13076.839366                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13077.023466                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13076.658141                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13076.839366                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        85300                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             7314                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             7438                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.845365                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.468137                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       615328                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       617627                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1232955                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       615328                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       617627                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1232955                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       615328                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       617627                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1232955                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8049960                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8092863                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16142823                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8049960                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8092863                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16142823                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8049960                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8092863                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16142823                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       606680                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       621529                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total      1228209                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       606680                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst       621529                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total      1228209                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       606680                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst       621529                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total      1228209                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      7983188                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8104594                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     16087782                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      7983188                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      8104594                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     16087782                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      7983188                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      8104594                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     16087782                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        12465                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         8175                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        20640                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        12465                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         8175                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        20640                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 100646775925                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 100551252932                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 201198028857                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 100646775925                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 100551252932                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 201198028857                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 100646775925                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 100551252932                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 201198028857                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  99492670437                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 101031835906                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 200524506343                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  99492670437                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 101031835906                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 200524506343                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  99492670437                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 101031835906                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 200524506343                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    965827500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    632670500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1598498000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    965827500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    632670500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1598498000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084847                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.084847                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.084847                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12463.621069                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12463.621069                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12463.621069                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.085226                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085703                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085465                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.085226                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085703                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.085465                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.085226                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085703                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.085465                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12462.774325                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12465.995941                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12464.397289                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12462.774325                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12465.995941                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12464.397289                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12462.774325                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12465.995941                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12464.397289                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77446.608527                       # average ReadReq mshr uncacheable latency
@@ -1362,15 +1343,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77446.608527                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              132830364                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         90187101                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5886537                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            91288458                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               64898028                       # Number of BTB hits
+system.cpu1.branchPred.lookups              132090219                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89757318                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5756723                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            89315962                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               64542834                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.091165                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17334778                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            185732                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            72.263493                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17132912                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            188342                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1400,96 +1381,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   905180                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               905180                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17142                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92306                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       553484                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       351696                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2321.493563                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 13592.585679                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       349244     99.30%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1804      0.51%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          390      0.11%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          114      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           67      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       351696                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       414217                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22492.792425                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18361.243775                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16253.124731                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767       322417     77.84%     77.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535        82857     20.00%     97.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303         6808      1.64%     99.48% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071         1275      0.31%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839          173      0.04%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607          198      0.05%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375          298      0.07%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           83      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           62      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           12      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447           13      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       414217                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 326963093592                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.083701                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.672512                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 325992368092     99.70%     99.70% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    539476500      0.16%     99.87% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    187726500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    115407500      0.04%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     46500000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     23809500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     21473500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     29946500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      5666000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       571000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        55000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        32500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51        25000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::52-55         4000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::56-59        32000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 326963093592                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        92306     84.34%     84.34% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17142     15.66%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       109448                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       905180                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   899065                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               899065                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16912                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92517                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       553507                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       345558                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2400.667905                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 13912.564680                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       343096     99.29%     99.29% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1764      0.51%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          399      0.12%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          131      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           83      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           41      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           39      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       345558                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       421889                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 22499.157361                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18375.438889                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 16484.116423                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       412836     97.85%     97.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         8131      1.93%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          432      0.10%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          347      0.08%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           85      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           30      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           25      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       421889                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 324784285420                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.056472                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.661085                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 323808973920     99.70%     99.70% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    531761500      0.16%     99.86% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    194206000      0.06%     99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    116904000      0.04%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     46719500      0.01%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     26039000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     24606500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     29193500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      5603500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       253000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43        17000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47         6000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51         2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 324784285420                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        92517     84.55%     84.55% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        16912     15.45%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       109429                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       899065                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       905180                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       109448                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       899065                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       109429                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       109448                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total      1014628                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       109429                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total      1008494                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   105776812                       # DTB read hits
-system.cpu1.dtb.read_misses                    627964                       # DTB read misses
-system.cpu1.dtb.write_hits                   81868125                       # DTB write hits
-system.cpu1.dtb.write_misses                   277216                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1087                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   105725858                       # DTB read hits
+system.cpu1.dtb.read_misses                    617527                       # DTB read misses
+system.cpu1.dtb.write_hits                   81869169                       # DTB write hits
+system.cpu1.dtb.write_misses                   281538                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1084                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21316                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    568                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   55232                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      212                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8920                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              21345                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    529                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   55091                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      175                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8923                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    54701                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               106404776                       # DTB read accesses
-system.cpu1.dtb.write_accesses               82145341                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    57008                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               106343385                       # DTB read accesses
+system.cpu1.dtb.write_accesses               82150707                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        187644937                       # DTB hits
-system.cpu1.dtb.misses                         905180                       # DTB misses
-system.cpu1.dtb.accesses                    188550117                       # DTB accesses
+system.cpu1.dtb.hits                        187595027                       # DTB hits
+system.cpu1.dtb.misses                         899065                       # DTB misses
+system.cpu1.dtb.accesses                    188494092                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1519,217 +1491,223 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                   106266                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               106266                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3111                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        73302                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14293                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        91973                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1630.543747                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  9941.577304                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        90961     98.90%     98.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          588      0.64%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303          258      0.28%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071           90      0.10%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839           38      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-491519            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        91973                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        90706                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28271.216899                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24128.368541                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18525.575548                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        88461     97.52%     97.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1926      2.12%     99.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          212      0.23%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           62      0.07%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           21      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        90706                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 610372252128                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.878972                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.326581                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    73947141376     12.12%     12.12% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   536358552252     87.87%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       59179000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        6640000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         645500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          94000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 610372252128                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        73302     95.93%     95.93% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         3111      4.07%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        76413                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                   107064                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               107064                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3059                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        73056                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        14602                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        92462                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1594.287383                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  9428.868117                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        91539     99.00%     99.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          493      0.53%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          272      0.29%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071           87      0.09%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839           28      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           16      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        92462                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        90717                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28181.123714                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24098.190167                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18325.203286                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        49691     54.78%     54.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535        38968     42.96%     97.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          889      0.98%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          845      0.93%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839          113      0.12%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607          103      0.11%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           30      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           24      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           11      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679           18      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        90717                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 612488746252                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.881369                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.323767                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    72732513396     11.87%     11.87% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   539691898856     88.11%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       57837000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        5354000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         885500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5         253500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6           4000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 612488746252                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        73056     95.98%     95.98% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3059      4.02%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        76115                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       106266                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       106266                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       107064                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       107064                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        76413                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        76413                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       182679                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    95636263                       # ITB inst hits
-system.cpu1.itb.inst_misses                    106266                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        76115                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        76115                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       183179                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    94801988                       # ITB inst hits
+system.cpu1.itb.inst_misses                    107064                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1087                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1084                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21316                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    568                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   41371                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              21345                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    529                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   40979                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202868                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   204318                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                95742529                       # ITB inst accesses
-system.cpu1.itb.hits                         95636263                       # DTB hits
-system.cpu1.itb.misses                         106266                       # DTB misses
-system.cpu1.itb.accesses                     95742529                       # DTB accesses
-system.cpu1.numCycles                       670348620                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                94909052                       # ITB inst accesses
+system.cpu1.itb.hits                         94801988                       # DTB hits
+system.cpu1.itb.misses                         107064                       # DTB misses
+system.cpu1.itb.accesses                     94909052                       # DTB accesses
+system.cpu1.numCycles                       671476106                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         245802953                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     590871754                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  132830364                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          82232806                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    386445016                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13431293                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2639306                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               21635                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             4572                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5276880                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       167481                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         2239                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 95410634                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3652057                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  41964                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         647075459                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.068807                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.316374                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         245366519                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     588017734                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  132090219                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          81675746                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    387641424                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13138102                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2647355                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               22361                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             4505                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      5327205                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       166052                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         2673                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 94574767                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3547562                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  42774                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         647746875                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.062629                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.311059                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               501080801     77.44%     77.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18371493      2.84%     80.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18561867      2.87%     83.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13401625      2.07%     85.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28513625      4.41%     89.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9105805      1.41%     91.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9777924      1.51%     92.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8450851      1.31%     93.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                39811468      6.15%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               502555880     77.59%     77.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18134910      2.80%     80.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18417584      2.84%     83.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13370411      2.06%     85.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                28474947      4.40%     89.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 9035668      1.39%     91.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9746929      1.50%     92.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8410613      1.30%     93.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39599933      6.11%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           647075459                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.198151                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.881440                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               199983147                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            321798427                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                106352633                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13609650                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5329449                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19773591                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1406143                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             644884461                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4323616                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5329449                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               207655640                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               26665473                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     252746187                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                112130376                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             42545968                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             629384575                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                84102                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2156884                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1598140                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              23186474                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3948                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          602389573                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            968798649                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       744085505                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           803060                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            505488932                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                96900641                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15182115                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13209558                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 75938042                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           101507501                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           86179777                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13679637                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14662477                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 596915130                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15279603                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                597602438                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           863336                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       81541272                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     52071117                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        356106                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    647075459                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.923544                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.649381                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           647746875                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.196716                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.875709                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               199564404                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            323792643                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                105578746                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13636228                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5172543                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19679879                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1416500                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             642218643                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4358994                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5172543                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               207175837                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               26230498                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     253904637                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                111453983                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             43806880                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             627356682                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                88872                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2222363                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1667701                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              24272659                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3825                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          600705753                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            967034808                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       741797210                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           803110                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            507019119                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                93686634                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15251472                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13261267                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 76352353                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           101066741                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           86034098                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13578571                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14575923                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 595450227                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15308226                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                597111513                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           840860                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       78779365                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     50277835                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        362203                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    647746875                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.921828                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.648992                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          412751344     63.79%     63.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           98711881     15.26%     79.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           43578879      6.73%     85.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31028755      4.80%     90.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           23162473      3.58%     94.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16109238      2.49%     96.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10961200      1.69%     98.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6490260      1.00%     99.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4281429      0.66%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          413645402     63.86%     63.86% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           98786426     15.25%     79.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43350634      6.69%     85.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           30948406      4.78%     90.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           23128317      3.57%     94.15% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           16110243      2.49%     96.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           11031117      1.70%     98.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6443224      0.99%     99.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4303106      0.66%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      647075459                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      647746875                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3038725     25.54%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 25345      0.21%     25.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   3128      0.03%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               3      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4885830     41.07%     66.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3943683     33.15%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                3034292     25.34%     25.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 25435      0.21%     25.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   2765      0.02%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4931574     41.19%     66.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3978849     33.23%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               46      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            405061818     67.78%     67.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1472658      0.25%     68.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                66179      0.01%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                 56      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               52      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            404756244     67.79%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1480116      0.25%     68.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                67236      0.01%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                 53      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.04% # Type of FU issued
@@ -1742,111 +1720,111 @@ system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.04% # Ty
 system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               2      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             16      0.00%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             23      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         71237      0.01%     68.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           107954973     18.06%     86.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           82975408     13.88%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         71191      0.01%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           107813613     18.06%     86.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82922942     13.89%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             597602438                       # Type of FU issued
-system.cpu1.iq.rate                          0.891480                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11896714                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019907                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1853948472                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        693931681                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    575193406                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1091913                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            542260                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       485773                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             608916098                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 583008                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4685337                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             597111513                       # Type of FU issued
+system.cpu1.iq.rate                          0.889252                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11972916                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.020051                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1853695544                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        689699314                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    575118751                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1088133                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            538121                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       485191                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             608503665                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 580712                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4698016                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     16615869                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        21909                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       749717                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      9068365                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     15955461                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        21531                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       710912                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      8765717                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3952894                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      8300380                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3921205                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      8400525                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5329449                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               14829127                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles             10212979                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          612328593                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1790117                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            101507501                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            86179777                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12919930                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                237071                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              9891044                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        749717                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2710919                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2329182                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5040101                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            590723670                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            105766513                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5987554                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5172543                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               14653668                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              9919586                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          610892135                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1742457                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            101066741                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            86034098                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12972500                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                236911                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              9594506                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        710912                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2600980                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2287673                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4888653                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            590524927                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            105716307                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5700612                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       133860                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   187634979                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               109483047                       # Number of branches executed
-system.cpu1.iew.exec_stores                  81868466                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.881219                       # Inst execution rate
-system.cpu1.iew.wb_sent                     576950915                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    575679179                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                284156915                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                493402851                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       133682                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   187585376                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               109412564                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81869069                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.879443                       # Inst execution rate
+system.cpu1.iew.wb_sent                     576824246                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    575603942                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                284399442                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                494076723                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.858776                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575913                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.857222                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575618                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       81583045                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14923497                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4500070                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    633204147                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.838045                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.832186                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       78818099                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14946023                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4359945                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    634288153                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.838703                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.835068                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    438438352     69.24%     69.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     96042056     15.17%     84.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     33088291      5.23%     89.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15382536      2.43%     92.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10958189      1.73%     93.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6612249      1.04%     94.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      6082014      0.96%     95.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3902550      0.62%     96.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22697910      3.58%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    439406713     69.28%     69.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     96089140     15.15%     84.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     33004326      5.20%     89.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15342101      2.42%     92.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10933751      1.72%     93.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6607641      1.04%     94.81% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6115019      0.96%     95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3924026      0.62%     96.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22865436      3.60%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    633204147                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           451699475                       # Number of instructions committed
-system.cpu1.commit.committedOps             530653461                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    634288153                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           452878140                       # Number of instructions committed
+system.cpu1.commit.committedOps             531979088                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     162003044                       # Number of memory references committed
-system.cpu1.commit.loads                     84891632                       # Number of loads committed
-system.cpu1.commit.membars                    3738235                       # Number of memory barriers committed
-system.cpu1.commit.branches                 100868221                       # Number of branches committed
-system.cpu1.commit.fp_insts                    465542                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                487126697                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13297594                       # Number of function calls committed.
+system.cpu1.commit.refs                     162379661                       # Number of memory references committed
+system.cpu1.commit.loads                     85111280                       # Number of loads committed
+system.cpu1.commit.membars                    3699604                       # Number of memory barriers committed
+system.cpu1.commit.branches                 101084293                       # Number of branches committed
+system.cpu1.commit.fp_insts                    466365                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                488261253                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13274874                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       367411373     69.24%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1128741      0.21%     69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           49317      0.01%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       368350296     69.24%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1137362      0.21%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           50458      0.01%     69.46% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.46% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.46% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.46% # Class of committed instruction
@@ -1869,35 +1847,35 @@ system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.46% #
 system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.46% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.46% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        60944      0.01%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       84891632     16.00%     85.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      77111412     14.53%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        61269      0.01%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       85111280     16.00%     85.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      77268381     14.52%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        530653461                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22697910                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1218827033                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1238367651                       # The number of ROB writes
-system.cpu1.timesIdled                        4095381                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       23273161                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 54406850213                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  451699475                       # Number of Instructions Simulated
-system.cpu1.committedOps                    530653461                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.484059                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.484059                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.673828                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.673828                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               696515100                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              411090108                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   864151                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  531144                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                126615327                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               127765048                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1196239956                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15044847                       # number of misc regfile writes
+system.cpu1.commit.op_class_0::total        531979088                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22865436                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1218285123                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1235075441                       # The number of ROB writes
+system.cpu1.timesIdled                        4119845                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       23729231                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 52762738169                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  452878140                       # Number of Instructions Simulated
+system.cpu1.committedOps                    531979088                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.482686                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.482686                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.674452                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.674452                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               696400049                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              410875535                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   865968                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  525416                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                127021368                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               128126601                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1197743929                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15078416                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                40301                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40301                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
@@ -1972,7 +1950,7 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           569059287                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           568866585                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
@@ -1982,17 +1960,17 @@ system.iobus.respLayer3.occupancy           147720000                       # La
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115460                       # number of replacements
-system.iocache.tags.tagsinuse               10.424672                       # Cycle average of tags in use
+system.iocache.tags.replacements               115461                       # number of replacements
+system.iocache.tags.tagsinuse               10.416117                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115476                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115477                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13093329887000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544075                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.880598                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221505                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430037                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651542                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13093305735000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.549567                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.866551                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221848                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429159                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651007                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2012,18 +1990,18 @@ system.iocache.overall_misses::realview.ethernet           40
 system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
 system.iocache.overall_misses::total             8856                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1614263059                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1619332059                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1629394165                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1634463165                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12613364228                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12613364228                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12612717420                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12612717420                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1614263059                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1619683059                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1629394165                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1634814165                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1614263059                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1619683059                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1629394165                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1634814165                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
@@ -2051,28 +2029,28 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183106.063861                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182913.369366                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184822.387137                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 184622.519485                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118253.245969                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118253.245969                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118247.181992                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118247.181992                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183106.063861                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 182891.040989                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 184822.387137                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 184599.612127                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183106.063861                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 182891.040989                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31017                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 184822.387137                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 184599.612127                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31652                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3459                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3349                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.967042                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.451179                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106629                       # number of writebacks
-system.iocache.writebacks::total               106629                       # number of writebacks
+system.iocache.writebacks::writebacks          106630                       # number of writebacks
+system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
@@ -2087,18 +2065,18 @@ system.iocache.overall_mshr_misses::realview.ethernet           40
 system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1173463059                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1176682059                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1188594165                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1191813165                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7280164228                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7280164228                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7279517420                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7279517420                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1173463059                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1176883059                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1188594165                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1192014165                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1173463059                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1176883059                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1188594165                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1192014165                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2113,307 +2091,308 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133106.063861                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 132913.369366                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134822.387137                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 134622.519485                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68253.245969                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68253.245969                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68247.181992                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.181992                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 133106.063861                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 132891.040989                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 134822.387137                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 134599.612127                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 133106.063861                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 132891.040989                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 134822.387137                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 134599.612127                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1395026                       # number of replacements
-system.l2c.tags.tagsinuse                65295.492166                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   50144400                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1458293                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    34.385682                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              15281090500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35597.818988                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   166.792374                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   227.419292                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3927.975659                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9604.860217                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   170.331373                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   255.084245                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3398.092398                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11947.117619                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.543180                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002545                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003470                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.059936                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.146559                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002599                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003892                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.051851                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.182299                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996330                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          361                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62906                       # Occupied blocks per task id
+system.l2c.tags.replacements                  1414414                       # number of replacements
+system.l2c.tags.tagsinuse                65287.875921                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   50028752                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1477251                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    33.866115                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              15277469000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35504.413846                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   175.319867                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   252.399214                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3604.019001                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     8668.612883                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   168.198781                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   249.035174                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3764.497441                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    12901.379713                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.541754                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002675                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003851                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.054993                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.132273                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002567                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003800                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.057442                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.196859                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996214                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          266                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62571                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          360                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          264                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          593                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2785                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5017                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54411                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005508                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.959869                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                445809940                       # Number of tag accesses
-system.l2c.tags.data_accesses               445809940                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       538533                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       183659                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       537301                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       193067                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1452560                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         8160945                       # number of Writeback hits
-system.l2c.Writeback_hits::total              8160945                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            5106                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5035                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               10141                       # number of UpgradeReq hits
+system.l2c.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2814                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5105                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54035                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004059                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.954758                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                445125308                       # Number of tag accesses
+system.l2c.tags.data_accesses               445125308                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker       529471                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       186836                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker       532880                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker       194253                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1443440                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         8163245                       # number of Writeback hits
+system.l2c.Writeback_hits::total              8163245                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            5159                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            4935                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               10094                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data             2                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           801127                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           795359                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1596486                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       7998143                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       8048835                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          16046978                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3426730                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3533561                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6960291                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       362301                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       359177                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           721478                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        538533                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        183659                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7998143                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4227857                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        537301                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        193067                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             8048835                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4328920                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                26056315                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       538533                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       183659                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7998143                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4227857                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       537301                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       193067                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            8048835                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4328920                       # number of overall hits
-system.l2c.overall_hits::total               26056315                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2429                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2264                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2593                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2507                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 9793                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         18387                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         18174                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             36561                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_hits::cpu0.data           802127                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           795144                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1597271                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       7936245                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst       8056010                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          15992255                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      3437949                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data      3523138                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          6961087                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       361682                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       352463                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           714145                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker        529471                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker        186836                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             7936245                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             4240076                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker        532880                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker        194253                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             8056010                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data             4318282                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                25994053                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       529471                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker       186836                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            7936245                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            4240076                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker       532880                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker       194253                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            8056010                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            4318282                       # number of overall hits
+system.l2c.overall_hits::total               25994053                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker         2596                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker         2347                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker         2527                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker         2344                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 9814                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data         18684                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         17988                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             36672                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         284361                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         270457                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             554818                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        51722                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        43961                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           95683                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       151868                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       164132                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         316000                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       271501                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       241468                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         512969                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2429                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2264                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             51722                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            436229                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2593                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2507                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             43961                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            434589                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                976294                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2429                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2264                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            51722                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           436229                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2593                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2507                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            43961                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           434589                       # number of overall misses
-system.l2c.overall_misses::total               976294                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    212763500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    201130500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    229023500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    219290000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      862207500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    279221000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    285672000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    564893000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       160500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         286935                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         277647                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             564582                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        46865                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst        48510                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           95375                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       149491                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       170842                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         320333                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       269874                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       249734                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         519608                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         2596                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         2347                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             46865                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            436426                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         2527                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         2344                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             48510                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            448489                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                990104                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         2596                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         2347                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            46865                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           436426                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         2527                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         2344                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            48510                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           448489                       # number of overall misses
+system.l2c.overall_misses::total               990104                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    226666000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker    208137000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    222854000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker    211048000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total      868705000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data    286606000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    278244500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    564850500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data        81000                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       240000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  28552328500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  27263762000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  55816090500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   4410990000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3717651000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   8128641000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  13488162000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  15070468500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  28558630500                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data  27681533000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data  26039052000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total  53720585000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    212763500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    201130500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   4410990000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  42040490500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    229023500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    219290000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3717651000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  42334230500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     93365569500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    212763500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    201130500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   4410990000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  42040490500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    229023500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    219290000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3717651000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  42334230500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    93365569500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       540962                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       185923                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       539894                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       195574                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1462353                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      8160945                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          8160945                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        23493                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        23209                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46702                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data            8                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  28759533500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data  27874280000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  56633813500                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst   4006344499                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst   4103874000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   8110218499                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  13350704000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  15601640500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  28952344500                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu0.data  27675709000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data  26863663000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total  54539372000                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    226666000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    208137000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   4006344499                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  42110237500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    222854000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    211048000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   4103874000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  43475920500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     94565081499                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    226666000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    208137000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   4006344499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  42110237500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    222854000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    211048000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   4103874000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  43475920500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    94565081499                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker       532067                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker       189183                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker       535407                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker       196597                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1453254                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      8163245                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          8163245                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        23843                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        22923                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           46766                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            7                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            3                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            11                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1085488                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data      1065816                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2151304                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      8049865                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      8092796                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      16142661                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      3578598                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data      3697693                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      7276291                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       633802                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       600645                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1234447                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       540962                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       185923                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         8049865                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         4664086                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       539894                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       195574                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         8092796                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         4763509                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            27032609                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       540962                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       185923                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        8049865                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        4664086                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       539894                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       195574                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        8092796                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        4763509                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           27032609                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.006697                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.782659                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783058                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.782857                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data      1089062                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data      1072791                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          2161853                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      7983110                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      8104520                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      16087630                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      3587440                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      3693980                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      7281420                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       631556                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       602197                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1233753                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       532067                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       189183                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         7983110                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         4676502                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker       535407                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker       196597                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         8104520                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         4766771                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            26984157                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       532067                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       189183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        7983110                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        4676502                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker       535407                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       196597                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        8104520                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        4766771                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           26984157                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004879                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012406                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004720                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011923                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006753                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.783626                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784714                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.784159                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.142857                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.333333                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.272727                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.261966                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.253756                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.257898                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006425                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005432                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005927                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042438                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.044388                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043429                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.428369                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.402015                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.415546                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006425                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.093529                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005432                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.091233                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.036115                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006425                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.093529                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005432                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.091233                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.036115                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 88043.245175                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15185.783434                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15718.719049                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15450.698832                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        80250                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_miss_rate::total     0.200000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.263470                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.258808                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.261157                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005871                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005986                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005928                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041671                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.046249                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.043993                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.427316                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.414705                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.421160                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004879                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012406                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.005871                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.093323                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004720                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.011923                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005986                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.094087                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.036692                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004879                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012406                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.005871                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.093323                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004720                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.011923                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005986                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.094087                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.036692                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87313.559322                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88682.147422                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88189.157103                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 90037.542662                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 88516.914612                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15339.648897                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15468.340004                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15402.773233                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        80000                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 100408.735727                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100806.272346                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 100602.522809                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85282.665017                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84567.025318                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 84953.868503                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88815.036742                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91819.197353                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 90375.412975                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 101957.388739                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 107836.450379                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 104724.817679                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85282.665017                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 96372.525669                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84567.025318                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 97412.107762                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 95632.636788                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85282.665017                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 96372.525669                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84567.025318                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 97412.107762                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 95632.636788                       # average overall miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 100230.134002                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100394.673812                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 100311.050476                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85486.919855                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84598.515770                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 85035.056346                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89307.744279                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91322.043174                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 90382.022770                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 102550.482818                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 107569.105528                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 104962.533294                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87313.559322                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88682.147422                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 85486.919855                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 96488.837741                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88189.157103                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90037.542662                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 84598.515770                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 96938.655129                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 95510.250942                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87313.559322                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88682.147422                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 85486.919855                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 96488.837741                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88189.157103                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90037.542662                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 84598.515770                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 96938.655129                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 95510.250942                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2422,295 +2401,295 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1179151                       # number of writebacks
-system.l2c.writebacks::total                  1179151                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           19                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           38                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           38                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               104                       # number of ReadReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.l2c.writebacks::writebacks             1193601                       # number of writebacks
+system.l2c.writebacks::total                  1193601                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           12                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           32                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker           14                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           28                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                86                       # number of ReadReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu0.data           10                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu1.data           12                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker           19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.itb.walker           38                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.dtb.walker           12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.itb.walker           32                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu0.data             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.itb.walker           38                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.dtb.walker           14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.itb.walker           28                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.data             12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                127                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.dtb.walker           19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.itb.walker           38                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                110                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.dtb.walker           12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.itb.walker           32                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu0.data            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.dtb.walker            9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.itb.walker           38                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.dtb.walker           14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.itb.walker           28                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.data            12                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               127                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2410                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2226                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2584                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2469                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            9689                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks         1116                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         1116                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        18387                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        18174                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        36561                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.overall_mshr_hits::total               110                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2584                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2315                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2513                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2316                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            9728                       # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks         1098                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         1098                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        18684                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        17988                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        36672                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       284361                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       270457                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        554818                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        51721                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        43961                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        95682                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       151858                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       164120                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       315978                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       271501                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       241468                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       512969                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         2410                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2226                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        51721                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       436219                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2584                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2469                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        43961                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       434577                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           976167                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         2410                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         2226                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        51721                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       436219                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2584                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2469                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        43961                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       434577                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          976167                       # number of overall MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       286935                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data       277647                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        564582                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        46863                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        48510                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        95373                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       149481                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data       170830                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       320311                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu0.data       269874                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data       249734                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total       519608                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         2584                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         2315                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        46863                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       436416                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2513                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         2316                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        48510                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data       448477                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           989994                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         2584                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         2315                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        46863                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       436416                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2513                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         2316                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        48510                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data       448477                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          989994                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        12465                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17396                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17080                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         8175                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16284                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        54320                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18911                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14786                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16596                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        54316                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18113                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        15582                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        33695                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        12465                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        36307                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        35193                       # number of overall MSHR uncacheable misses
 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         8175                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31070                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        88017                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    757696500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    381648500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    377184000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    758832500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        32178                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        88011                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    199854500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    182923500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    196571500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    185980500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    765330000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    387591999                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    373200500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    760792499                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        71000                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        69500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       210000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  25708718500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  24559192000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  50267910500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   3893746000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   3278041000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   7171787000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  11968937500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13428627500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  25397565000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  24966523000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  23624372000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  48590895000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   3893746000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  37677656000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3278041000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  37987819500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  83594959000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   3893746000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  37677656000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3278041000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  37987819500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  83594959000                       # number of overall MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  25890183500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  25097810000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  50987993500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   3537569999                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   3618774000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   7156343999                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  11855172500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13892574000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  25747746500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  24976969000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  24366323000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  49343292000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    199854500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    182923500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   3537569999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  37745356000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    196571500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    185980500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3618774000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  38990384000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  84657413999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    199854500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    182923500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   3537569999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  37745356000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    196571500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    185980500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3618774000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  38990384000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  84657413999                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    772594499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2817435000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2773087000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    505958000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2602704500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6698691999                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2830764496                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2473673500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5304437996                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2647172500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6698811999                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2709591500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2594934500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5304526000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    772594499                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5648199496                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5482678500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    505958000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5076378000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12003129995                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.006626                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5242107000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12003337999                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004857                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.012237                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004694                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011780                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.006694                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.782659                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783058                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.782857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.783626                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784714                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.784159                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.142857                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.261966                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.253756                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.257898                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005927                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042435                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.044384                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043426                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.428369                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.402015                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.415546                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.093527                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.091230                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.036111                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.093527                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.091230                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.036111                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 78201.723604                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.431174                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.044239                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.244660                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        70250                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.263470                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.258808                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.261157                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005870                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005986                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005928                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041668                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.046246                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043990                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.427316                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.414705                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.421160                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004857                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012237                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005870                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.093321                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004694                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011780                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005986                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.094084                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.036688                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004857                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012237                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005870                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.093321                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004694                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011780                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005986                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.094084                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.036688                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 78672.902961                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20744.594252                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20747.192573                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20745.868755                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90408.735727                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90806.272346                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 90602.522809                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74954.401037                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78816.641204                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81822.005240                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80377.637051                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 91957.388739                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97836.450379                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94724.817679                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86373.257469                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87413.322610                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 85635.919878                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86373.257469                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87413.322610                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 85635.919878                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90230.134002                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90394.673812                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 90311.050476                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75487.484775                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74598.515770                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75035.324452                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79308.892100                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81323.971199                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80383.585016                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 92550.482818                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97569.105528                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94962.533294                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75487.484775                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86489.395439                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74598.515770                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86939.539820                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 85513.057654                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75487.484775                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86489.395439                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74598.515770                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86939.539820                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 85513.057654                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161958.783628                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162358.723653                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159832.013019                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123319.072147                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149688.778806                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167298.356553                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157415.734220                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159506.658231                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123330.363042                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149593.744824                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166534.109870                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157427.689568                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155567.782962                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155788.892678                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 163385.194722                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 136372.859732                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162909.658773                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 136384.520105                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54320                       # Transaction distribution
-system.membus.trans_dist::ReadResp             484522                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
-system.membus.trans_dist::Writeback           1285780                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           222453                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37353                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           37356                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1066998                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1066998                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        430202                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54316                       # Transaction distribution
+system.membus.trans_dist::ReadResp             488581                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33695                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33695                       # Transaction distribution
+system.membus.trans_dist::Writeback           1300231                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           226932                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            37530                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           37532                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1083335                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1083335                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        434265                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6864                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4492142                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4621788                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342195                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342195                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4963983                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6852                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4552687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4682321                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5023611                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    172016940                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    172188714                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7259520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7259520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               179448234                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2724                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3239737                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    174247596                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    174419346                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7230976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7230976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               181650322                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3166                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3279708                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3239737    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3279708    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3239737                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113920999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3279708                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           114259000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               51156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5444004                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5427500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8690318133                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8793071023                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8114396828                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8222412889                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228917368                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228888550                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2754,67 +2733,67 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.trans_dist::ReadReq            2074158                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25494018                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          9446739                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict        18863436                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           46705                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          46716                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2151304                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2151304                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16142823                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7285144                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1341111                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1234447                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48465856                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32213596                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       910891                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2571300                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              84161643                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1034451264                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1125904618                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3051976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8646848                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2172054706                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2184416                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         57389162                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.063529                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.243911                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2064834                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25434780                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33695                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33695                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          9463502                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict        18825810                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           46769                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          46779                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2161853                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2161853                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      16087782                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7290273                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1340417                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1233753                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48300519                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32258677                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       920526                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2543246                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              84022968                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1030929280                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1127055058                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3086240                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8539792                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2169610370                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2203584                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         57319196                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.063782                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.244364                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               53743303     93.65%     93.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                3645859      6.35%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               53663256     93.62%     93.62% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                3655940      6.38%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           57389162                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        36059386455                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           57319196                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        36016999461                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1120500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1117500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24257498228                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24175146802                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14835156686                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14858261870                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         529789657                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         535144651                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1493165292                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1478603615                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16399                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   19287                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
index edfc7ccb5..10ca60c72 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -208,7 +208,7 @@ sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -503,7 +503,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -538,7 +538,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -953,9 +953,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 8ea842e52..0c2ce6f33 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.832615                       # Nu
 sim_ticks                                51832614542500                       # Number of ticks simulated
 final_tick                               51832614542500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 636228                       # Simulator instruction rate (inst/s)
-host_op_rate                                   747615                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            37416431352                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 669888                       # Number of bytes of host memory used
-host_seconds                                  1385.29                       # Real time elapsed on the host
+host_inst_rate                                 536275                       # Simulator instruction rate (inst/s)
+host_op_rate                                   630162                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31538205227                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 713092                       # Number of bytes of host memory used
+host_seconds                                  1643.49                       # Real time elapsed on the host
 sim_insts                                   881360160                       # Number of instructions simulated
 sim_ops                                    1035663034                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -599,7 +599,7 @@ system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                 518072849                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16267                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   19145                       # number of quiesce instructions executed
 system.cpu0.dcache.tags.replacements         10037940                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.966034                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs          305864730                       # Total number of references to valid blocks.
@@ -2119,13 +2119,13 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
 system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 4b49caa69..15805fa4d 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -29,7 +29,7 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -202,7 +202,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -252,7 +252,7 @@ system=system
 port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -594,7 +594,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -660,7 +660,7 @@ system=system
 port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -695,7 +695,7 @@ sequential_access=false
 size=1024
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1202,7 +1202,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -1586,7 +1586,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1609,7 +1609,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index ce7843f5c..264f4c629 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.154115                       # Number of seconds simulated
-sim_ticks                                5154115247000                       # Number of ticks simulated
-final_tick                               5154115247000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.126140                       # Number of seconds simulated
+sim_ticks                                5126139641000                       # Number of ticks simulated
+final_tick                               5126139641000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128017                       # Simulator instruction rate (inst/s)
-host_op_rate                                   253040                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1617614851                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 806232                       # Number of bytes of host memory used
-host_seconds                                  3186.24                       # Real time elapsed on the host
-sim_insts                                   407894468                       # Number of instructions simulated
-sim_ops                                     806246903                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 128755                       # Simulator instruction rate (inst/s)
+host_op_rate                                   254500                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1618610313                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 809248                       # Number of bytes of host memory used
+host_seconds                                  3167.00                       # Real time elapsed on the host
+sim_insts                                   407767906                       # Number of instructions simulated
+sim_ops                                     806002026                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1047104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10813376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1038720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10766272                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11893632                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1047104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1047104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9584064                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9584064                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           70                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16361                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168959                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11837632                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1038720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1038720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9565696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9565696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           61                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16230                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168223                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                185838                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149751                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149751                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            869                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               203159                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2098008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2307599                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          203159                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             203159                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1859497                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1859497                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1859497                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              203159                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2098008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4167097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        185838                       # Number of read requests accepted
-system.physmem.writeReqs                       149751                       # Number of write requests accepted
-system.physmem.readBursts                      185838                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     149751                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11883456                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9582144                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11893632                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9584064                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                184963                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149464                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               202632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2100269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5531                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2309268                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          202632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             202632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1866062                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1866062                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1866062                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              202632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2100269                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5531                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4175331                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        184963                       # Number of read requests accepted
+system.physmem.writeReqs                       149464                       # Number of write requests accepted
+system.physmem.readBursts                      184963                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149464                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11826048                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9564672                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11837632                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9565696                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      181                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48492                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11738                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11323                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11916                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11912                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12271                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11705                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10605                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10992                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11596                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11415                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11752                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11610                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11474                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12022                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11655                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11693                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10141                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9357                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8826                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8882                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9347                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9205                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8767                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8936                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9149                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9192                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              10057                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9346                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9689                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9578                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9663                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9586                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48781                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12059                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11374                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11651                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11200                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11713                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11071                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11625                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11816                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11540                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11598                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11427                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11449                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11382                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12463                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11321                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11093                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10213                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9339                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9470                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9072                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9457                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9178                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9173                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8997                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8928                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9204                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9473                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8827                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9527                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9857                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9294                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9439                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5154115197500                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5126139591500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  185838                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  184963                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149751                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    171307                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11621                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1958                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       473                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149464                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170238                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11784                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1972                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       468                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        57                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -156,418 +156,418 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7770                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2963                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     9638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9886                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8512                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       94                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        72428                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.370685                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     175.530831                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     319.820481                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          27904     38.53%     38.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17658     24.38%     62.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7456     10.29%     73.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4108      5.67%     78.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2731      3.77%     82.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1986      2.74%     85.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1581      2.18%     87.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1174      1.62%     89.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7830     10.81%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          72428                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7352                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.252992                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      561.335686                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7351     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        71880                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      297.588425                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.048684                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     320.988013                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27629     38.44%     38.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17400     24.21%     62.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7428     10.33%     72.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4118      5.73%     78.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2845      3.96%     82.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1999      2.78%     85.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1307      1.82%     87.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1141      1.59%     88.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8013     11.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          71880                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7347                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.150402                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      560.379075                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7346     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7352                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7352                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.364663                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.601623                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.168660                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6294     85.61%     85.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              82      1.12%     86.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             194      2.64%     89.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              86      1.17%     90.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              99      1.35%     91.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             218      2.97%     94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              33      0.45%     95.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.15%     95.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              15      0.20%     95.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               6      0.08%     95.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.04%     95.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.04%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             253      3.44%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.07%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.04%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               7      0.10%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.05%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.04%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.04%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.20%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7347                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7347                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.341364                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.592949                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.054942                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6299     85.74%     85.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              77      1.05%     86.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             192      2.61%     89.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              82      1.12%     90.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             130      1.77%     92.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             203      2.76%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              23      0.31%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.10%     95.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               7      0.10%     95.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               8      0.11%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.05%     95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.08%     95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             243      3.31%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.10%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.12%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              11      0.15%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             7      0.10%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            16      0.22%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7352                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2003475850                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5484957100                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    928395000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10790.00                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7347                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1972823732                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5437486232                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    923910000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10676.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29540.00                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29426.49                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.86                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.16                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     152313                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110658                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.03                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.89                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15358415.20                       # Average gap between requests
-system.physmem.pageHitRate                      78.40                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  270738720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  147724500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 721203600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                476027280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           336641292000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           130240416060                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2978219081250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3446716483410                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.731853                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4954469478230                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    172107000000                       # Time in different power states
+system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.70                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     152120                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110229                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.32                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.75                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15328127.19                       # Average gap between requests
+system.physmem.pageHitRate                      78.49                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  270149040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  147402750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 721570200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                485345520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           334814035920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           129415070025                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2962157471250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3428011044705                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.732438                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4927750166228                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    171172820000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27531969270                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27209465022                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  276816960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  151041000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 727084800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                494164800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           336641292000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           130162900905                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2978287085250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3446740385715                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.736489                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4954592740478                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    172107000000                       # Time in different power states
+system.physmem_1.actEnergy                  273263760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  149102250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 719721600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                483077520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           334814035920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           129328302060                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2962233583500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3428001086610                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.730496                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4927884080230                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    171172820000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27415396022                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27082630770                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86789700                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86789700                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            894071                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             80040540                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78122239                       # Number of BTB hits
+system.cpu.branchPred.lookups                86515320                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86515320                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            846562                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79887008                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                77941063                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.603338                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1558682                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             180590                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.564128                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1538368                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             179519                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        449504376                       # number of cpu cycles simulated
+system.cpu.numCycles                        448780162                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27485279                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      428718572                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86789700                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79680921                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     418030666                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1875632                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     150798                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                59488                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        208856                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           90                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          672                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9123295                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                449746                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4755                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          446873665                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.892893                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.051645                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27109366                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      427484272                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86515320                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79479431                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     417767954                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1778202                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     144572                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                59542                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        198505                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          291                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8932158                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                424030                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4890                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          446169387                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.890848                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.050446                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                281625965     63.02%     63.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2138685      0.48%     63.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72155487     16.15%     79.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1568927      0.35%     80.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2122343      0.47%     80.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2325830      0.52%     80.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1507660      0.34%     81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1867139      0.42%     81.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81561629     18.25%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281281763     63.04%     63.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2130107      0.48%     63.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72126905     16.17%     79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1545484      0.35%     80.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2095217      0.47%     80.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2290541      0.51%     81.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1479828      0.33%     81.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1850907      0.41%     81.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81368635     18.24%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            446873665                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.193079                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.953758                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 22890187                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             264923803                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150702566                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7419293                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 937816                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              837865741                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 937816                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25728184                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               222903682                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       12889746                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154594835                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29819402                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834359795                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                448369                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12212745                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 141423                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               14773604                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           996662587                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1812180036                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1114009606                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               309                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964181963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 32480622                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             461875                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         465908                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38538990                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17255328                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10136845                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1286418                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1053742                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  828858399                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1188333                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 823669123                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            243637                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23799824                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     35821203                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         147900                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     446873665                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.843181                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.418517                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            446169387                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.192779                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.952547                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23013230                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             265986736                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 147854773                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8425547                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 889101                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              835878661                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 889101                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 26336765                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               222825660                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       12982234                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 152266315                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              30869312                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              832551989                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                449261                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12787861                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 146326                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               14734321                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           994655089                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1807638707                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1111268111                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               319                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             963888503                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 30766581                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             460676                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         463553                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  43190500                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17070475                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10019861                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1311535                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1113253                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  827301854                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1181846                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 822527972                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            224018                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        22481665                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33938360                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         142118                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     446169387                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.843533                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.419200                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           262902763     58.83%     58.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13828746      3.09%     61.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9781500      2.19%     64.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7055144      1.58%     65.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74339132     16.64%     82.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4387820      0.98%     83.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72808347     16.29%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1195469      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              574744      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262457891     58.82%     58.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13818111      3.10%     61.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9771246      2.19%     64.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7528828      1.69%     65.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            73243364     16.42%     82.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4832116      1.08%     83.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72756563     16.31%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1182673      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              578595      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       446873665                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       446169387                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1974081     71.95%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     2      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 609151     22.20%     94.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                160307      5.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2475977     76.35%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 605774     18.68%     95.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161247      4.97%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            285084      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795424559     96.57%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150449      0.02%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                127671      0.02%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  84      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18333357      2.23%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9347919      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            283294      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             794512938     96.59%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150315      0.02%     96.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                126079      0.02%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  84      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18183253      2.21%     98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9272009      1.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              823669123                       # Type of FU issued
-system.cpu.iq.rate                           1.832394                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2743541                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003331                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2097198642                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         853858757                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819128971                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 446                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                432                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          155                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826127364                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     216                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1863869                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              822527972                       # Type of FU issued
+system.cpu.iq.rate                           1.832808                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3242998                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003943                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2094691886                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         850977244                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    818130626                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                450                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          165                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              825487451                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     225                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1857982                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3260732                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        15309                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14369                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1707925                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3083761                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14419                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13953                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1600409                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2207612                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         70919                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2207227                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         67958                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 937816                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               204799790                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              10007204                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830046732                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            155850                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17255344                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10136845                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             698572                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 395239                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8760495                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14369                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         514805                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       529588                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1044393                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822053660                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17935902                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1483234                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 889101                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               204671978                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              10002497                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           828483700                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            158761                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17070475                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10019861                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             692471                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 393140                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8758574                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13953                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         479614                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       507057                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               986671                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             821011839                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17813350                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1389357                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27057833                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83242296                       # Number of branches executed
-system.cpu.iew.exec_stores                    9121931                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.828800                       # Inst execution rate
-system.cpu.iew.wb_sent                      821550761                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819129126                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640649566                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1049893259                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     26873346                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83150160                       # Number of branches executed
+system.cpu.iew.exec_stores                    9059996                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.829430                       # Inst execution rate
+system.cpu.iew.wb_sent                      820539763                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     818130791                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 639922411                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1048802840                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.822294                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610204                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.823010                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610146                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23669936                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1040433                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            905908                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    443311497                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.818692                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.674309                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        22357422                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1039727                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            857347                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    442798070                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.820247                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.674846                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    272449194     61.46%     61.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11181690      2.52%     63.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3605884      0.81%     64.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74618286     16.83%     81.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2464935      0.56%     82.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1628465      0.37%     82.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       954634      0.22%     82.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70998554     16.02%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5409855      1.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272013186     61.43%     61.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11121974      2.51%     63.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3639430      0.82%     64.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74586618     16.84%     81.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2447768      0.55%     82.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1626880      0.37%     82.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1002961      0.23%     82.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70975924     16.03%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5383329      1.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    443311497                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407894468                       # Number of instructions committed
-system.cpu.commit.committedOps              806246903                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    442798070                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407767906                       # Number of instructions committed
+system.cpu.commit.committedOps              806002026                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22423531                       # Number of memory references committed
-system.cpu.commit.loads                      13994611                       # Number of loads committed
-system.cpu.commit.membars                      468283                       # Number of memory barriers committed
-system.cpu.commit.branches                   82184111                       # Number of branches committed
+system.cpu.commit.refs                       22406164                       # Number of memory references committed
+system.cpu.commit.loads                      13986712                       # Number of loads committed
+system.cpu.commit.membars                      468149                       # Number of memory barriers committed
+system.cpu.commit.branches                   82157432                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735078702                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1156217                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171842      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783387641     97.16%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          145035      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121422      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 734850257                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155439                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       171613      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783160302     97.17%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144896      0.02%     97.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121618      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
@@ -594,230 +594,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13992027      1.74%     98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8428920      1.05%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13984129      1.73%     98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8419452      1.04%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806246903                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5409855                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1267740043                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1663415417                       # The number of ROB writes
-system.cpu.timesIdled                          288487                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2630711                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9858723524                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407894468                       # Number of Instructions Simulated
-system.cpu.committedOps                     806246903                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.102011                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.102011                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.907432                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.907432                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1091775121                       # number of integer regfile reads
-system.cpu.int_regfile_writes               655663425                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       155                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416039105                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321913343                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265322894                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 400562                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1662098                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.990156                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19068760                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1662610                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.469172                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total         806002026                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5383329                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1265696040                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1660107630                       # The number of ROB writes
+system.cpu.timesIdled                          283975                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2610775                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9803496536                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407767906                       # Number of Instructions Simulated
+system.cpu.committedOps                     806002026                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.100577                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.100577                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.908614                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.908614                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1090426394                       # number of integer regfile reads
+system.cpu.int_regfile_writes               654841654                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       165                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 415713185                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                321659378                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               264880270                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 399890                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1655948                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.995019                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18959511                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1656460                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.445801                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          40620500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.990156                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999981                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999981                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.995019                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          204                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88153475                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88153475                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10917190                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10917190                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8084600                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8084600                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        64210                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         64210                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19001790                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19001790                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19066000                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19066000                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1815691                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1815691                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       334621                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       334621                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406397                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406397                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2150312                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2150312                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2556709                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2556709                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  27046737500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  27046737500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  13846171242                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  13846171242                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  40892908742                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  40892908742                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  40892908742                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  40892908742                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12732881                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12732881                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8419221                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8419221                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       470607                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       470607                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21152102                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21152102                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21622709                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21622709                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142599                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.142599                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039745                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039745                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863559                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.863559                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101659                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101659                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118242                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118242                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14896.112554                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14896.112554                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.667932                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.667932                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19017.197849                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19017.197849                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15994.353969                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15994.353969                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       467851                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             51332                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          87653092                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         87653092                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10818266                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10818266                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8075018                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8075018                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        63136                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         63136                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      18893284                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18893284                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18956420                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18956420                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1801440                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1801440                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       334795                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       334795                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406500                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406500                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2136235                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2136235                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2542735                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2542735                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26875877500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26875877500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  13801276738                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  13801276738                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  40677154238                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  40677154238                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  40677154238                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  40677154238                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12619706                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12619706                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8409813                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8409813                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       469636                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       469636                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21029519                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21029519                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21499155                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21499155                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142748                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.142748                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039810                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039810                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865564                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.865564                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.101583                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.101583                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118271                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118271                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14919.107769                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14919.107769                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.067065                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.067065                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19041.516611                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19041.516611                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15997.402104                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15997.402104                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       467524                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             52009                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.114217                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           84                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.989290                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           95                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1563047                       # number of writebacks
-system.cpu.dcache.writebacks::total           1563047                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       843909                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       843909                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44439                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44439                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       888348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       888348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       888348                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       888348                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       971782                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       971782                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290182                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290182                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402906                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402906                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1261964                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1261964                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1664870                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1664870                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602920                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total       602920                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13934                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        13934                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616854                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       616854                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13356525500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  13356525500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12439701244                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12439701244                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6060856500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6060856500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25796226744                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25796226744                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31857083244                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31857083244                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97797423500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97797423500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2624129500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2624129500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100421553000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100421553000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076321                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076321                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034467                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.856141                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.856141                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059661                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059661                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076996                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076996                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.363962                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.363962                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42868.617778                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42868.617778                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15042.854909                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15042.854909                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20441.333306                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20441.333306                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19134.877344                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19134.877344                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.301831                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.301831                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188325.642314                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188325.642314                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162796.306744                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162796.306744                       # average overall mshr uncacheable latency
+system.cpu.dcache.writebacks::writebacks      1557810                       # number of writebacks
+system.cpu.dcache.writebacks::total           1557810                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       835579                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       835579                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44644                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44644                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       880223                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       880223                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       880223                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       880223                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       965861                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       965861                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290151                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290151                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403017                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       403017                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1256012                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1256012                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1659029                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1659029                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13873                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        13873                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616769                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       616769                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13275179500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  13275179500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12396951239                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12396951239                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6045548500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6045548500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25672130739                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25672130739                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31717679239                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31717679239                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793653500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793653500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2614977500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2614977500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076536                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076536                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034501                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034501                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858148                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858148                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059726                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059726                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077167                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077167                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        73546                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    14.805379                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       113695                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        73561                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.545588                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5097093086500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.805379                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.925336                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.925336                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements        71018                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.855051                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       110090                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        71033                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.549843                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.855051                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.990941                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.990941                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       451096                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       451096                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       113711                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       113711                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       113711                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       113711                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       113711                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       113711                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74558                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        74558                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74558                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        74558                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74558                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        74558                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    932190000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    932190000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    932190000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    932190000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    932190000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    932190000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       188269                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       188269                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       188269                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       188269                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       188269                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       188269                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.396018                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.396018                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.396018                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12502.883661                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12502.883661                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12502.883661                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       436469                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       436469                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       110104                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       110104                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       110104                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       110104                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       110104                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       110104                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        72087                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        72087                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        72087                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        72087                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        72087                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        72087                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    888705500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    888705500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    888705500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    888705500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    888705500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    888705500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       182191                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       182191                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       182191                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       182191                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       182191                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       182191                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395667                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395667                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395667                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395667                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395667                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395667                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -826,180 +827,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        13222                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        13222                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74558                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74558                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74558                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        74558                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74558                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        74558                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    857632000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    857632000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    857632000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.396018                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.396018                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.396018                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11502.883661                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11502.883661                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11502.883661                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        17880                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        17880                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        72087                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        72087                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        72087                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        72087                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        72087                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        72087                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    816618500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    816618500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    816618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    816618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    816618500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    816618500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395667                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395667                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395667                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395667                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395667                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395667                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            993321                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.961085                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8058871                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            993832                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.108887                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      147914027500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.961085                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994065                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994065                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          113                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10117194                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10117194                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8058871                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8058871                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8058871                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8058871                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8058871                       # number of overall hits
-system.cpu.icache.overall_hits::total         8058871                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1064420                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1064420                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1064420                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1064420                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1064420                       # number of overall misses
-system.cpu.icache.overall_misses::total       1064420                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14809433489                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14809433489                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14809433489                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14809433489                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14809433489                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14809433489                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9123291                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9123291                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9123291                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9123291                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9123291                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9123291                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116671                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116671                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116671                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116671                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116671                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116671                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13913.148465                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13913.148465                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13913.148465                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13913.148465                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13913.148465                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13913.148465                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         6712                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           16                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               348                       # number of cycles access was blocked
+system.cpu.icache.tags.replacements            972475                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.589862                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7892622                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            972987                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.111745                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147937650500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.589862                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995293                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995293                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          274                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          134                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses           9905522                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9905522                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7892622                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7892622                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7892622                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7892622                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7892622                       # number of overall hits
+system.cpu.icache.overall_hits::total         7892622                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1039533                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1039533                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1039533                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1039533                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1039533                       # number of overall misses
+system.cpu.icache.overall_misses::total       1039533                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14506630997                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14506630997                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14506630997                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14506630997                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14506630997                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14506630997                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8932155                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8932155                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8932155                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8932155                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8932155                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8932155                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116381                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.116381                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.116381                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.116381                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.116381                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.116381                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13954.949960                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13954.949960                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6454                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           21                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               314                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    19.287356                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           16                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    20.554140                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           21                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70517                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        70517                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        70517                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        70517                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        70517                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        70517                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       993903                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       993903                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       993903                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       993903                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       993903                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       993903                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13139309991                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13139309991                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13139309991                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13139309991                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13139309991                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13139309991                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108941                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108941                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108941                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13219.911793                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13219.911793                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13219.911793                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66166                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        66166                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        66166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        66166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        66166                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        66166                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       973367                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       973367                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       973367                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       973367                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       973367                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       973367                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12880264497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12880264497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12880264497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12880264497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12880264497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12880264497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108973                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108973                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108973                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108973                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108973                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108973                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        13951                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.067078                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        26495                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        13966                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.897107                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5104644726500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.067078                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.379192                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.379192                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        97508                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        97508                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26495                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26495                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.replacements        13962                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.017494                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        24005                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        13975                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.717710                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.017494                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376093                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.376093                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        92555                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        92555                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24014                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        24014                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26497                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26497                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26497                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26497                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14838                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        14838                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14838                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        14838                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14838                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        14838                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176788000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176788000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176788000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    176788000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176788000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    176788000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41333                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        41333                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24016                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        24016                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24016                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        24016                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14841                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14841                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14841                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        14841                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14841                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        14841                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    170100000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    170100000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    170100000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    170100000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    170100000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    170100000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        38855                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        38855                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41335                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        41335                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41335                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        41335                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358987                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358987                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358969                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.358969                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358969                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.358969                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11914.543739                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11914.543739                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11914.543739                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11914.543739                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11914.543739                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11914.543739                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        38857                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        38857                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        38857                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        38857                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.381959                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.381959                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.381939                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.381939                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.381939                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.381939                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1008,183 +1009,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1499                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1499                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14838                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14838                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14838                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        14838                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14838                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        14838                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    161950000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    161950000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    161950000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    161950000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    161950000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    161950000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358987                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358987                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358969                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358969                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358969                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358969                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10914.543739                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10914.543739                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10914.543739                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         2319                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         2319                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14841                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14841                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14841                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14841                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14841                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        14841                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    155259000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    155259000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    155259000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    155259000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    155259000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    155259000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.381959                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.381959                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.381939                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.381939                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.381939                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.381939                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112938                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64810.238427                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4946164                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176935                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            27.954695                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           112328                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64826.279220                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4884469                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176125                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.732968                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50458.579366                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    20.514879                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139418                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3172.056588                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11158.948175                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.769937                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000313                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.632944                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.140332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3105.306836                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.771202                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000208                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048402                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.170272                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.988926                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63997                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3372                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5567                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54302                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.976517                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43925036                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43925036                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      1577768                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1577768                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          309                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          309                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       153927                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       153927                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       977435                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       977435                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        69221                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12891                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1338249                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1420361                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        69221                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        12891                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       977435                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1492176                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2551723                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        69221                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        12891                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       977435                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1492176                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2551723                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1505                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1505                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       134154                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       134154                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16363                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           70                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35783                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        35858                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           70                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16363                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       169937                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        186375                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           70                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16363                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       169937                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       186375                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23274500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     23274500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10328890000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10328890000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1358981500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1358981500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      6541000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       429500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3085479000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3092449500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6541000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       429500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1358981500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  13414369000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14780321000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6541000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       429500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1358981500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  13414369000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14780321000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      1577768                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1577768                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1814                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1814                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       288081                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       288081                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       993798                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       993798                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        69291                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        12896                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1374032                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1456219                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69291                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        12896                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       993798                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1662113                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2738098                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69291                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        12896                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       993798                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1662113                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2738098                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.829658                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.829658                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.465682                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.465682                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016465                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016465                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000388                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026042                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024624                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000388                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016465                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102242                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.068067                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000388                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016465                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102242                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068067                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15464.784053                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15464.784053                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76992.784412                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76992.784412                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83052.099248                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83052.099248                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        85900                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86227.510270                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86241.550003                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        85900                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83052.099248                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78937.306178                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79304.203890                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        85900                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83052.099248                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78937.306178                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79304.203890                       # average overall miss latency
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047383                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.170375                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989171                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63797                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          708                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3407                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5556                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54082                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.973465                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43431157                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43431157                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1578009                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1578009                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          321                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          321                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       154224                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       154224                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       956701                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       956701                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        65553                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12091                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332425                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1410069                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        65553                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        12091                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       956701                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1486649                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2520994                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        65553                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        12091                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       956701                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1486649                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2520994                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1786                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1786                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133488                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133488                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16231                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        16231                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           61                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            6                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35709                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        35776                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           61                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        16231                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       169197                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        185495                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           61                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        16231                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       169197                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       185495                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23220500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     23220500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10274230500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10274230500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1348223000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1348223000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      5829000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       513000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3059963500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3066305500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5829000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       513000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1348223000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  13334194000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  14688759000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5829000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       513000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1348223000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  13334194000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  14688759000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      1578009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1578009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2107                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2107                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       287712                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       287712                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       972932                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       972932                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        65614                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        12097                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1368134                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1445845                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        65614                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        12097                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       972932                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1655846                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2706489                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        65614                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        12097                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       972932                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1655846                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2706489                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.847651                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.847651                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463964                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.463964                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016683                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016683                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000930                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000496                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026101                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024744                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000930                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000496                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016683                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102182                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.068537                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000930                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000496                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016683                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102182                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.068537                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13001.399776                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13001.399776                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76967.446512                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76967.446512                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83064.691023                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83064.691023                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 95557.377049                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        85500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85691.660366                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85708.449799                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 95557.377049                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        85500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83064.691023                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78808.690461                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79186.819052                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 95557.377049                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        85500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83064.691023                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78808.690461                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79186.819052                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1193,181 +1194,181 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       103084                       # number of writebacks
-system.cpu.l2cache.writebacks::total           103084                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           88                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total           88                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1505                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1505                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       134154                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       134154                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16361                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16361                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           70                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35779                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35854                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           70                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16361                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       169933                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       186369                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           70                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16361                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       169933                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       186369                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602920                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602920                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13934                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13934                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616854                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616854                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     32097000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     32097000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8987350000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8987350000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1195241000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1195241000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       379500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2728894000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2735114500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       379500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1195241000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11716244000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  12917705500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       379500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1195241000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11716244000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  12917705500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90260915500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90260915500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2463879500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2463879500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92724795000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92724795000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.writebacks::writebacks       102797                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102797                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            3                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            3                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            3                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          107                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          107                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1786                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1786                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133488                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133488                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16230                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16230                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           61                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            6                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35706                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35773                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           61                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16230                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       169194                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185491                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           61                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16230                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169194                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185491                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13873                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13873                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616769                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616769                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37836000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37836000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8939350500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8939350500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1185827000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1185827000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5219000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       453000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2703742500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2709414500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5219000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       453000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1185827000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11643093000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12834592000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5219000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       453000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1185827000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11643093000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12834592000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257448500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257448500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2455427500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2455427500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92712876000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92712876000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.829658                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.829658                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.465682                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.465682                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026039                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024621                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102239                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068065                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102239                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068065                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21326.910299                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21326.910299                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66992.784412                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66992.784412                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73054.275411                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76270.829257                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76284.779941                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68946.255289                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69312.522469                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68946.255289                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69312.522469                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.288562                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.288562                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176824.996412                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176824.996412                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150318.867998                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150318.867998                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.847651                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.847651                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463964                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463964                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016682                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016682                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000930                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026098                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024742                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000930                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016682                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102180                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.068536                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000930                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016682                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102180                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.068536                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        75500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75739.090935                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        75500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73063.894023                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68815.046633                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69192.532252                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        75500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         602920                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3061153                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1727529                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1124352                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       288090                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       288090                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       993903                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1464872                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq         1650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           12                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         602896                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3032324                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1727482                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1093519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2562                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2562                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287721                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287721                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       973367                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1456602                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq         1641                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2979851                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6223737                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        32716                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       177236                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9413540                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63603072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208211079                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       921280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5280832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          278016263                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      218468                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6317764                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.033210                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.179185                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917513                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6205490                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31703                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       168231                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           9322937                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62267648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207474745                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       922624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5343616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          276008633                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      220316                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6258702                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.033424                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.179742                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            6107951     96.68%     96.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4             209813      3.32%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            6049509     96.66%     96.66% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             209193      3.34%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6317764                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4638715490                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        6258702                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4609709481                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       577500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       573000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1492354491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1461362367                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3105124685                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3096027096                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      22263487                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      22269484                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     111892387                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     108175907                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               222126                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              222126                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57753                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57753                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1650                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1650                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               222102                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              222102                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57708                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57708                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1641                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1641                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
@@ -1383,15 +1384,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       464488                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       464350                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3300                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  563058                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3282                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3282                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  562902                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
@@ -1407,19 +1408,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       238530                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       238452                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3272994                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3933000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3272880                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3911656                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1449,25 +1450,25 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           242643106                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           242679087                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           453455000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           453362000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            50182000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1650000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1641000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                47580                       # number of replacements
-system.iocache.tags.tagsinuse                0.177808                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.091366                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4993210705000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.177808                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.011113                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.011113                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4993241946000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091366                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005710                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005710                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1481,14 +1482,14 @@ system.iocache.demand_misses::pc.south_bridge.ide          915
 system.iocache.demand_misses::total               915                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide          915                       # number of overall misses
 system.iocache.overall_misses::total              915                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142818702                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    142818702                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5513453404                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5513453404                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    142818702                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    142818702                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    142818702                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    142818702                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    143595677                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    143595677                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5513463410                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5513463410                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    143595677                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    143595677                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    143595677                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    143595677                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
@@ -1505,19 +1506,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 156086.013115                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.560873                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118010.560873                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 156086.013115                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 156086.013115                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           218                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 156935.166120                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 156935.166120                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 156935.166120                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   18                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.111111                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1531,14 +1532,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide          915
 system.iocache.demand_mshr_misses::total          915                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide          915                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          915                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     97068702                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3177453404                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3177453404                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     97068702                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     97068702                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97845677                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     97845677                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3177463410                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3177463410                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97845677                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     97845677                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97845677                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     97845677                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1547,81 +1548,81 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 106086.013115                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.560873                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.560873                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 106086.013115                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 106086.013115                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 106935.166120                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 106935.166120                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              602920                       # Transaction distribution
-system.membus.trans_dist::ReadResp             656038                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13934                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13934                       # Transaction distribution
-system.membus.trans_dist::Writeback            149751                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            10203                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2209                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1791                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133869                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133868                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         53130                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1650                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1650                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           12                       # Transaction distribution
+system.membus.trans_dist::ReadReq              602896                       # Transaction distribution
+system.membus.trans_dist::ReadResp             655806                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13873                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13873                       # Transaction distribution
+system.membus.trans_dist::Writeback            149464                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             9883                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2535                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2080                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133195                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133194                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         52918                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1641                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1641                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3300                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3300                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464488                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769220                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       488383                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           24                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1722115                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1867232                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238530                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538437                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18462656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20239623                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3282                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3282                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464350                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769188                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       486631                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1720185                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1865287                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238452                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538373                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18388288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20165113                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23261263                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1586                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1014957                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001626                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.040287                       # Request fanout histogram
+system.membus.pkt_size::total                23186717                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1616                       # Total snoops (count)
+system.membus.snoop_fanout::samples           1013692                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001619                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.040202                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1013307     99.84%     99.84% # Request fanout histogram
-system.membus.snoop_fanout::2                    1650      0.16%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 1012051     99.84%     99.84% # Request fanout histogram
+system.membus.snoop_fanout::2                    1641      0.16%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             1014957                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           355040500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1013692                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           354973500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           388549500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           388325000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3300000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3282000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1018755770                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1016908044                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               14000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                9500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1650000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1641000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2209187226                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2204699193                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           86115345                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           86072153                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index bea975397..d7ee3e6f6 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -29,7 +29,7 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -134,7 +134,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -184,7 +184,7 @@ system=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -1220,7 +1220,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -1255,7 +1255,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1639,7 +1639,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1662,7 +1662,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
index 6fe40cc4f..6cc193075 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -2,7 +2,7 @@
     "name": null, 
     "sim_quantum": 0, 
     "system": {
-        "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9", 
+        "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", 
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "bridge": {
@@ -111,7 +111,7 @@
             "clk_domain": "system.cpu_clk_domain", 
             "write_buffers": 8, 
             "response_latency": 20, 
-            "cxx_class": "BaseCache", 
+            "cxx_class": "Cache", 
             "size": 4194304, 
             "tags": {
                 "name": "tags", 
@@ -145,11 +145,11 @@
             "prefetch_on_access": false, 
             "path": "system.l2c", 
             "name": "l2c", 
-            "type": "BaseCache", 
+            "type": "Cache", 
             "sequential_access": false, 
             "assoc": 8
         }, 
-        "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", 
+        "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", 
         "intel_mp_table": {
             "oem_table_addr": 0, 
             "name": "intel_mp_table", 
@@ -638,7 +638,7 @@
             "clk_domain": "system.clk_domain", 
             "write_buffers": 8, 
             "response_latency": 50, 
-            "cxx_class": "BaseCache", 
+            "cxx_class": "Cache", 
             "size": 1024, 
             "tags": {
                 "name": "tags", 
@@ -672,7 +672,7 @@
             "prefetch_on_access": false, 
             "path": "system.iocache", 
             "name": "iocache", 
-            "type": "BaseCache", 
+            "type": "Cache", 
             "sequential_access": false, 
             "assoc": 8
         }, 
@@ -1183,7 +1183,7 @@
                                     "eventq_index": 0, 
                                     "cxx_class": "RawDiskImage", 
                                     "path": "system.pc.south_bridge.ide.disks0.image.child", 
-                                    "image_file": "/work/gem5/dist/disks/linux-x86.img", 
+                                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", 
                                     "type": "RawDiskImage"
                                 }, 
                                 "path": "system.pc.south_bridge.ide.disks0.image", 
@@ -1211,7 +1211,7 @@
                                     "eventq_index": 0, 
                                     "cxx_class": "RawDiskImage", 
                                     "path": "system.pc.south_bridge.ide.disks1.image.child", 
-                                    "image_file": "/work/gem5/dist/disks/linux-bigswap2.img", 
+                                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", 
                                     "type": "RawDiskImage"
                                 }, 
                                 "path": "system.pc.south_bridge.ide.disks1.image", 
@@ -1797,7 +1797,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 32768, 
                     "tags": {
                         "name": "tags", 
@@ -1831,7 +1831,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu0.icache", 
                     "name": "icache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 1
                 }, 
@@ -1906,7 +1906,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 32768, 
                     "tags": {
                         "name": "tags", 
@@ -1940,7 +1940,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu0.dcache", 
                     "name": "dcache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 4
                 }, 
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
index 69801740a..fb8fdc7fa 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
@@ -4,6 +4,7 @@ warn: Sockets disabled, not accepting gdb connections
 warn: Reading current count from inactive timer.
 warn: Don't know what interrupt to clear for console.
 warn: x86 cpuid: unknown family 0xbacc
+warn: x86 cpuid: unknown family 0xbacc
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -21,24 +22,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7107, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12359, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10565, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7170, Bank: 1
+Command: 0, Timestamp: 7191, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -52,7 +43,7 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7090, Bank: 1
+Command: 0, Timestamp: 6675, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -61,6 +52,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6767, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6921, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11289, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7232, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11338, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -77,26 +82,24 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to clear PCI interrupt 14
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: Unknown mouse command 0xe1.
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: instruction 'wbinvd' unimplemented
+warn: Tried to clear PCI interrupt 14
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: Unknown mouse command 0xe1.
+warn: instruction 'wbinvd' unimplemented
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10421, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9326, Bank: 7
+Command: 0, Timestamp: 7075, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 0
+Command: 0, Timestamp: 6474, Bank: 4
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6590, Bank: 6
+Command: 0, Timestamp: 6837, Bank: 6
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index ba1f8e728..494bbffd2 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,156 +1,152 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.141168                       # Number of seconds simulated
-sim_ticks                                5141168437500                       # Number of ticks simulated
-final_tick                               5141168437500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.137726                       # Number of seconds simulated
+sim_ticks                                5137726358500                       # Number of ticks simulated
+final_tick                               5137726358500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 195369                       # Simulator instruction rate (inst/s)
-host_op_rate                                   388397                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4114294038                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1021404                       # Number of bytes of host memory used
-host_seconds                                  1249.59                       # Real time elapsed on the host
-sim_insts                                   244131065                       # Number of instructions simulated
-sim_ops                                     485336254                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 193743                       # Simulator instruction rate (inst/s)
+host_op_rate                                   385165                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4079424438                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1056160                       # Number of bytes of host memory used
+host_seconds                                  1259.42                       # Real time elapsed on the host
+sim_insts                                   244004222                       # Number of instructions simulated
+sim_ops                                     485086710                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           377472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4958144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           201472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2034880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           383296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          3456256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           380096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4972288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           215232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2058496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         2112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           369024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          3382272                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11442624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       377472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       201472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       383296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          962240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9198208                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9198208                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11408192                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       380096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       215232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       369024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          964352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9193728                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9193728                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              5898                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             77471                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3148                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             31795                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           37                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             54004                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              5939                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             77692                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3363                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             32164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           33                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5766                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             52848                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                178791                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143722                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143722                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                178253                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143652                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143652                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               73421                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              964400                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               39188                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              395801                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           461                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               74554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              672271                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5515                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2225685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          73421                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          39188                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          74554                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             187164                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1789128                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1789128                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1789128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               73981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              967799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               41892                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              400663                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           411                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               71826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              658321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2220475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          73981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          41892                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          71826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             187700                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1789455                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1789455                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1789455                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              73421                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             964400                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              39188                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             395801                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          461                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              74554                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             672271                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5515                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4014813                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         95417                       # Number of read requests accepted
-system.physmem.writeReqs                        81462                       # Number of write requests accepted
-system.physmem.readBursts                       95417                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      81462                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6099840                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5213440                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6106688                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5213568                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu0.inst              73981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             967799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              41892                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             400663                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          411                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              71826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             658321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4009929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         94617                       # Number of read requests accepted
+system.physmem.writeReqs                        88760                       # Number of write requests accepted
+system.physmem.readBursts                       94617                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      88760                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6047936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5680640                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6055488                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5680640                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          21330                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6364                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5596                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5691                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5690                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                6222                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5617                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5512                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5018                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6455                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6386                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5929                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5798                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5744                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6558                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6049                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6681                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5937                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5551                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4927                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4762                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5737                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5264                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5028                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4496                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4483                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4823                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4660                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4592                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4759                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5475                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5045                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5921                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          28899                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                6147                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5269                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5685                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5978                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5788                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5231                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5218                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5097                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6282                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6366                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               6408                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               6175                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5716                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6642                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6153                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6344                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6191                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5213                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6082                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5966                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5232                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5147                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4857                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4466                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5491                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5559                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5838                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5586                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5717                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5929                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5787                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5699                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5140168291000                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5136593386000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   95417                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   94617                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  81462                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     89319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4643                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       844                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       184                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  88760                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     87985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      5016                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       993                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        47                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -165,989 +161,996 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        70                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        63                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        60                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4340                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4893                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        41433                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      273.048440                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.990010                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     298.466349                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16764     40.46%     40.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10136     24.46%     64.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4303     10.39%     75.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2529      6.10%     81.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1659      4.00%     85.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1139      2.75%     88.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          786      1.90%     90.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          657      1.59%     91.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3460      8.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          41433                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4254                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.404325                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      181.210886                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            4251     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4558                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4579                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6774                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5868                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4923                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        41697                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      281.270307                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     168.374177                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.197981                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16587     39.78%     39.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10275     24.64%     64.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4266     10.23%     74.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2445      5.86%     80.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1622      3.89%     84.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1132      2.71%     87.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          786      1.89%     89.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          680      1.63%     90.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3904      9.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          41697                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4370                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.624485                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      178.940609                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            4367     99.93%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-1535            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-6655            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4254                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4254                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.149036                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.343940                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       10.936401                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                69      1.62%      1.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.16%      1.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                1      0.02%      1.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               8      0.19%      2.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3652     85.85%     87.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              58      1.36%     89.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              99      2.33%     91.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              64      1.50%     93.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              41      0.96%     94.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              93      2.19%     96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              12      0.28%     96.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.19%     96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.26%     96.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.09%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.14%     97.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.05%     97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             101      2.37%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.05%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.07%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.02%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             6      0.14%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4254                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1082376548                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2869439048                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    476550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11356.38                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4370                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4370                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.311213                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.106663                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.785732                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                51      1.17%      1.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 5      0.11%      1.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.02%      1.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               8      0.18%      1.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3654     83.62%     85.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              60      1.37%     86.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             119      2.72%     89.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              59      1.35%     90.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              85      1.95%     92.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             116      2.65%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              13      0.30%     95.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               5      0.11%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.21%     95.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.07%     95.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.05%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               4      0.09%     95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             133      3.04%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.09%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.14%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.07%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.07%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.05%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.23%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.07%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4370                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1101479246                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2873335496                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    472495000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11655.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30106.38                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.19                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.01                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30405.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.18                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.18                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      76603                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     58733                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.10                       # Row buffer hit rate for writes
-system.physmem.avgGap                     29060364.94                       # Average gap between requests
-system.physmem.pageHitRate                      76.56                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  152447400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   82937250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 356538000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                270228960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           250406807040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            95253368040                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2241273741750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2587796068440                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.867367                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   3687953773966                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    128019840000                       # Time in different power states
+system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        11.15                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      75876                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     65681                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                     28011110.37                       # Average gap between requests
+system.physmem.pageHitRate                      77.24                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  153536040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   83535375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 346421400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                279618480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           250238982240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            94990329855                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2239672524000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2585764947390                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.869445                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   3685813216724                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    127934040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     18290517534                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     17956780776                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  160786080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   87503625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 386872200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                257631840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           250406807040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            95642577720                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2237948975250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2584891153755                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.974840                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3687413088990                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    128019840000                       # Time in different power states
+system.physmem_1.actEnergy                  161655480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   87978000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 390663000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                295410240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250238982240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            95244065640                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2234394426750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2580813181350                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.044329                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3685435461238                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    127934040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     18838516010                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     18309070012                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                       818622179                       # number of cpu cycles simulated
+system.cpu0.numCycles                       810473886                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   70465386                       # Number of instructions committed
-system.cpu0.committedOps                    143948929                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            131896754                       # Number of integer alu accesses
+system.cpu0.committedInsts                   70312072                       # Number of instructions committed
+system.cpu0.committedOps                    143658243                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            131612768                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     904463                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     13997547                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   131896754                       # number of integer instructions
+system.cpu0.num_func_calls                     897074                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     13988759                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   131612768                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          241558700                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         113520418                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          240911367                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         113282572                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            82096977                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           54912679                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13231012                       # number of memory refs
-system.cpu0.num_load_insts                    9870869                       # Number of load instructions
-system.cpu0.num_store_insts                   3360143                       # Number of store instructions
-system.cpu0.num_idle_cycles              776995348.800534                       # Number of idle cycles
-system.cpu0.num_busy_cycles              41626830.199466                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050850                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949150                       # Percentage of idle cycles
-system.cpu0.Branches                         15238298                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                84207      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                130532761     90.68%     90.74% # Class of executed instruction
-system.cpu0.op_class::IntMult                   57038      0.04%     90.78% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    45915      0.03%     90.81% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.81% # Class of executed instruction
-system.cpu0.op_class::MemRead                 9869228      6.86%     97.67% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3360143      2.33%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            82064957                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           54880945                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13139441                       # number of memory refs
+system.cpu0.num_load_insts                    9809284                       # Number of load instructions
+system.cpu0.num_store_insts                   3330157                       # Number of store instructions
+system.cpu0.num_idle_cycles              769348747.137634                       # Number of idle cycles
+system.cpu0.num_busy_cycles              41125138.862366                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050742                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949258                       # Percentage of idle cycles
+system.cpu0.Branches                         15218344                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                83498      0.06%      0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                130336285     90.73%     90.78% # Class of executed instruction
+system.cpu0.op_class::IntMult                   55624      0.04%     90.82% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    45353      0.03%     90.85% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.85% # Class of executed instruction
+system.cpu0.op_class::MemRead                 9807642      6.83%     97.68% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3330157      2.32%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 143949292                       # Class of executed instruction
+system.cpu0.op_class::total                 143658559                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          1638295                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999362                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19673231                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1638807                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            12.004605                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1637472                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999430                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19610556                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1637984                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.972373                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   232.517984                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   254.861534                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data    24.619844                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.454137                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.497776                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.048086                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   233.382237                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   253.425972                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    25.191221                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.455825                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.494973                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.049202                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          251                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88575778                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88575778                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4693238                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2575592                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4254114                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11522944                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3236162                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1812970                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      3039112                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8088244                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19748                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10138                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        30323                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        60209                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7929400                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4388562                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7293226                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19611188                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7949148                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4398700                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7323549                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19671397                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       340869                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       165985                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       824524                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1331378                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       120523                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        67710                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       137190                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       325423                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       143877                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        63954                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       198209                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406040                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       461392                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       233695                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       961714                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1656801                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       605269                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       297649                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1159923                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2062841                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2308605500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12073522500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14382128000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2733996493                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4762162878                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7496159371                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5042601993                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  16835685378                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  21878287371                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5042601993                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  16835685378                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  21878287371                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5034107                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2741577                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      5078638                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     12854322                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3356685                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1880680                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3176302                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8413667                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       163625                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        74092                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       228532                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       466249                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8390792                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4622257                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      8254940                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21267989                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8554417                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4696349                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      8483472                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21734238                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067712                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060544                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.162351                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.103574                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.035905                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036003                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.043192                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038678                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.879309                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.863170                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867314                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.870865                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.054988                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050559                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116502                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.077901                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070755                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.063379                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.136727                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.094912                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13908.518842                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.021307                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.437775                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40378.031207                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.172010                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.124656                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21577.705954                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.916913                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13205.138922                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16941.437710                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.485339                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10605.900974                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       198021                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88313667                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88313667                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4629522                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2541915                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4295165                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11466602                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3206369                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1799760                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      3076031                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       8082160                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        19345                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data         9882                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        30831                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        60058                       # number of SoftPFReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7835891                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      4341675                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      7371196                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        19548762                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7855236                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      4351557                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      7402027                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       19608820                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       342984                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       163194                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       822092                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1328270                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       120211                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        69264                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       136170                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       325645                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       144505                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        65147                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       196531                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       406183                       # number of SoftPFReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       463195                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       232458                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       958262                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1653915                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       607700                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       297605                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1154793                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2060098                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2262546000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12291465500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  14554011500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2775957490                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4654158371                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   7430115861                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   5038503490                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  16945623871                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  21984127361                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   5038503490                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  16945623871                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  21984127361                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4972506                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      2705109                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      5117257                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     12794872                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3326580                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1869024                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3212201                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      8407805                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       163850                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        75029                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       227362                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       466241                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8299086                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      4574133                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      8329458                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21202677                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8462936                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      4649162                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      8556820                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21668918                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068976                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060328                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.160651                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.103813                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036137                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.037059                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042391                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.038731                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.881935                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.868291                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.864397                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871187                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055813                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050820                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115045                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.078005                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.071807                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.064013                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.134956                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.095072                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13864.149417                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14951.447648                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10957.118282                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40077.926340                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34179.028942                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 22816.612756                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21674.898218                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17683.706409                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13292.174846                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16930.170830                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14674.165734                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10671.398817                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       195153                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            23048                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            22760                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.591678                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.574385                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1547778                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1547778                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           51                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       385318                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       385369                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1567                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        32007                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        33574                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1618                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       417325                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       418943                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1618                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       417325                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       418943                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       165934                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       439206                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       605140                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        66143                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       105183                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       171326                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        63954                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       194797                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       258751                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       232077                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       544389                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       776466                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       296031                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       739186                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1035217                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       186036                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       204987                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total       391023                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3332                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4183                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       189368                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       209170                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total       398538                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2142200000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5924733500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8066933500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2581607993                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4076164379                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6657772372                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    949074500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2819608000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3768682500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4723807993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10000897879                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  14724705872                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5672882493                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12820505879                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  18493388372                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30610037000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33210281500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63820318500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    591963000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    837812500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1429775500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31202000000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34048094000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65250094000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060525                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086481                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.047077                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.035170                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.033115                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.020363                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.863170                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.852384                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.554963                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050209                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065947                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.036509                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.063034                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087132                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.047631                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12909.952150                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.646089                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.689592                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39030.706091                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.072065                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.256890                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14839.955280                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14474.596631                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14564.900232                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20354.485766                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.866933                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.748409                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19163.136607                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.086440                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.262635                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164538.245286                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162011.647080                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163213.720165                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177659.963986                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200289.863734                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190256.220892                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164769.126780                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162777.138213                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163723.644922                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks      1547245                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1547245                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           49                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       383157                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       383206                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1554                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        32300                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        33854                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1603                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       415457                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       417060                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1603                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       415457                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       417060                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       163145                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       438935                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       602080                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        67710                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       103870                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       171580                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        65147                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       193119                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       258266                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       230855                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       542805                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       773660                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       296002                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       735924                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1031926                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       186313                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       204652                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total       390965                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3641                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         3691                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         7332                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       189954                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       208343                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total       398297                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2099080000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5941231000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8040311000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2625649990                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3973863872                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6599513862                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    969909500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2805652000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3775561500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4724729990                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9915094872                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  14639824862                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5694639490                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12720746872                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  18415386362                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30666876000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33145024000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63811900000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    650679500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    751025500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1401705000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31317555500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33896049500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65213605000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060310                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.085775                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.047056                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036227                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032336                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.020407                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.868291                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.849390                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.553932                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050470                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065167                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.036489                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.063668                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086004                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.047622                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12866.345889                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13535.559935                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13354.223691                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38777.876089                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38258.052104                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38463.188379                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14888.014797                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14528.099255                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14618.887116                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20466.223344                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18266.402984                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18922.814753                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19238.516936                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17285.408374                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17845.646260                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164598.691449                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161957.977445                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163216.400445                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178709.008514                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 203474.803576                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 191176.350245                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164869.155164                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162693.488622                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163731.097648                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           878679                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.838296                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          128369666                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           879191                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           146.008849                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     149037485500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   260.884696                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   143.250304                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   106.703296                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.509540                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.279786                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.208405                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997731                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           865313                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.808042                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          127930489                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           865825                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           147.755596                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     149027837500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   256.241174                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   140.482462                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   114.084406                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.500471                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.274380                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.222821                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997672                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        130155694                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       130155694                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     85680859                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39485533                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3203274                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      128369666                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     85680859                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39485533                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3203274                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       128369666                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     85680859                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39485533                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3203274                       # number of overall hits
-system.cpu0.icache.overall_hits::total      128369666                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       290083                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       179832                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       436911                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       906826                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       290083                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       179832                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       436911                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        906826                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       290083                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       179832                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       436911                       # number of overall misses
-system.cpu0.icache.overall_misses::total       906826                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2559612500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6034803488                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8594415988                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2559612500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   6034803488                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8594415988                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2559612500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   6034803488                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8594415988                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     85970942                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39665365                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3640185                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    129276492                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     85970942                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     39665365                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3640185                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    129276492                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     85970942                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     39665365                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3640185                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    129276492                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003374                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004534                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.120024                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.007015                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003374                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004534                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.120024                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.007015                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003374                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004534                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.120024                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.007015                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.353908                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.432024                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9477.469755                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14233.353908                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.432024                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9477.469755                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14233.353908                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.432024                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9477.469755                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         5682                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        129687214                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       129687214                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     85494784                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     39252405                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3183300                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      127930489                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     85494784                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     39252405                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3183300                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       127930489                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     85494784                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     39252405                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3183300                       # number of overall hits
+system.cpu0.icache.overall_hits::total      127930489                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       295547                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       174112                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       421231                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       890890                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       295547                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       174112                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       421231                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        890890                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       295547                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       174112                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       421231                       # number of overall misses
+system.cpu0.icache.overall_misses::total       890890                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2498575500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5836919481                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8335494981                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2498575500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5836919481                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8335494981                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2498575500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5836919481                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8335494981                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     85790331                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     39426517                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3604531                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    128821379                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     85790331                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     39426517                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3604531                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    128821379                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     85790331                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     39426517                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3604531                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    128821379                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003445                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004416                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.116862                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006916                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003445                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004416                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.116862                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006916                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003445                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004416                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.116862                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006916                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14350.392276                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13856.813675                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9356.368329                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14350.392276                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13856.813675                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9356.368329                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14350.392276                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13856.813675                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9356.368329                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4826                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              315                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              303                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.038095                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.927393                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        27624                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        27624                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        27624                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        27624                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        27624                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        27624                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       179832                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       409287                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       589119                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       179832                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       409287                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       589119                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       179832                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       409287                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       589119                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2379780500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5367751488                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7747531988                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2379780500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5367751488                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7747531988                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2379780500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5367751488                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7747531988                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.112436                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004557                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.112436                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004557                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.112436                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004557                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.883903                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.047561                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.883903                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.047561                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.883903                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.047561                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        25055                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        25055                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        25055                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        25055                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        25055                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        25055                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       174112                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       396176                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       570288                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       174112                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       396176                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       570288                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       174112                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       396176                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       570288                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2324463500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5197379983                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   7521843483                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2324463500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5197379983                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   7521843483                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2324463500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5197379983                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   7521843483                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004416                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.109911                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004427                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004416                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.109911                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004427                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004416                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.109911                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004427                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13350.392276                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13118.866320                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13189.552442                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13350.392276                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13118.866320                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13189.552442                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13350.392276                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13118.866320                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13189.552442                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2607160707                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606018119                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35907928                       # Number of instructions committed
-system.cpu1.committedOps                     69695660                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64757843                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35722790                       # Number of instructions committed
+system.cpu1.committedOps                     69377917                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             64437935                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     501298                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6590213                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64757843                       # number of integer instructions
+system.cpu1.num_func_calls                     498036                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6548156                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    64437935                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          119979371                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55719008                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          119381439                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55453390                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36729292                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27266794                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4880817                       # number of memory refs
-system.cpu1.num_load_insts                    2999293                       # Number of load instructions
-system.cpu1.num_store_insts                   1881524                       # Number of store instructions
-system.cpu1.num_idle_cycles              2477690884.667310                       # Number of idle cycles
-system.cpu1.num_busy_cycles              129469822.332690                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.049659                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.950341                       # Percentage of idle cycles
-system.cpu1.Branches                          7272679                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                37847      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64724112     92.87%     92.92% # Class of executed instruction
-system.cpu1.op_class::IntMult                   30276      0.04%     92.96% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    24690      0.04%     93.00% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.00% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2997578      4.30%     97.30% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1881524      2.70%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36402445                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27104510                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4834095                       # number of memory refs
+system.cpu1.num_load_insts                    2964009                       # Number of load instructions
+system.cpu1.num_store_insts                   1870086                       # Number of store instructions
+system.cpu1.num_idle_cycles              2478102522.985643                       # Number of idle cycles
+system.cpu1.num_busy_cycles              127915596.014357                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.049085                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.950915                       # Percentage of idle cycles
+system.cpu1.Branches                          7225753                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                35671      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64456455     92.91%     92.96% # Class of executed instruction
+system.cpu1.op_class::IntMult                   31131      0.04%     93.00% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    22623      0.03%     93.03% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.03% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2962280      4.27%     97.30% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1870086      2.70%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69696027                       # Class of executed instruction
+system.cpu1.op_class::total                  69378246                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29601973                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29601973                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           343203                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26791839                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               26086008                       # Number of BTB hits
+system.cpu2.branchPred.lookups               29560975                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29560975                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           321330                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26625449                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               26036610                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.365500                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 612615                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             69103                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       155854675                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.788435                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 603794                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             66654                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       155113045                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          11239570                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     145909603                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29601973                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26698623                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    143043279                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 717621                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                    104333                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                8734                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             9529                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        59780                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles           15                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          573                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3640195                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               178301                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3755                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         154823972                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.854554                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.033337                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          11047280                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     145686023                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29560975                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26640404                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    142542790                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 677515                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                    104928                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                5475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             8867                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        68985                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles           22                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          511                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3604542                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               166149                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   3283                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         154116964                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.860489                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.036370                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                98922650     63.89%     63.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  904691      0.58%     64.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23796776     15.37%     79.85% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  606779      0.39%     80.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  848220      0.55%     80.79% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  866864      0.56%     81.35% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  584872      0.38%     81.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  770506      0.50%     82.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27522614     17.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                98277439     63.77%     63.77% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  921613      0.60%     64.37% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23771065     15.42%     79.79% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  603849      0.39%     80.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  843324      0.55%     80.73% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  864608      0.56%     81.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  573617      0.37%     81.66% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  772001      0.50%     82.16% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27489448     17.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           154823972                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.189933                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.936190                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10345115                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             94152716                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 23674012                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              5064791                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                359462                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             284127567                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                359462                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12498058                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76923279                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4647064                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 26307426                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             12860875                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             282811276                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               202798                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5895071                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 49763                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               4757971                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          337796416                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            617680837                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       379222279                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              178                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            324911571                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                12884845                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            166150                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        167782                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 24657180                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6871363                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3845087                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           401055                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          322271                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 280748481                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             429304                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                278478009                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           108269                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        9486120                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     14384377                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         66849                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    154823972                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.798675                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.397594                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           154116964                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.190577                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.939225                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10113688                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             93745988                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 23732554                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              5061206                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                339409                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             283817902                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                339409                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                12262766                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               76655623                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4610961                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 26368994                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             12755160                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             282570010                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               203292                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5910187                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 59652                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4622392                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          337562699                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            617313701                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       378956511                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups              176                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            325317107                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                12245592                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            169706                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        171154                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 24674635                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6903065                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3842483                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           404867                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          342392                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 280633357                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             431682                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                278499537                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           103065                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        9014489                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     13791367                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         66778                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    154116964                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.807066                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.400549                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           91620637     59.18%     59.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5352321      3.46%     62.63% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3836914      2.48%     65.11% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3858930      2.49%     67.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           22596079     14.59%     82.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2789392      1.80%     84.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           24067258     15.54%     99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             479282      0.31%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             223159      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           90926640     59.00%     59.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5330208      3.46%     62.46% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3853102      2.50%     64.96% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3864237      2.51%     67.46% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           22585971     14.66%     82.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2780196      1.80%     83.92% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           24046184     15.60%     99.53% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             494962      0.32%     99.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             235464      0.15%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      154823972                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      154116964                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1768977     86.18%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                219653     10.70%     96.88% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                63974      3.12%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1774419     86.10%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                221659     10.76%     96.86% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                64684      3.14%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            83002      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            267565718     96.08%     96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               58655      0.02%     96.13% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                54123      0.02%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                 92      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             7168633      2.57%     98.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3547786      1.27%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            87958      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            267524922     96.06%     96.09% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               58980      0.02%     96.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                56493      0.02%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                 63      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             7208859      2.59%     98.72% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3562262      1.28%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             278478009                       # Type of FU issued
-system.cpu2.iq.rate                          1.786780                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    2052604                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007371                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         713940607                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        290668150                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    276821518                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                256                       # Number of floating instruction queue reads
+system.cpu2.iq.FU_type_0::total             278499537                       # Type of FU issued
+system.cpu2.iq.rate                          1.795462                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2060762                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007400                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         713279610                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        290083917                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    276907807                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                255                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes               236                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             280447483                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                    128                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          731517                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.fp_inst_queue_wakeup_accesses          101                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             280472218                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                    123                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          745560                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1286395                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6167                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5109                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       663777                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1225052                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         5875                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5188                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       625672                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       750358                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        29268                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       750058                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        26954                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                359462                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               70735218                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              3134704                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          281177785                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            44449                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6871363                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3845087                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            251829                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                166997                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              2638299                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5109                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        196795                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       202269                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              399064                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            277848009                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              7014778                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           573017                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                339409                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               70544458                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              3078967                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          281065039                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            38553                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6903084                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3842483                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            256263                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                170697                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              2578390                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5188                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        180466                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       193564                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              374030                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            277914745                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              7063605                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           530025                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    10469775                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                28224309                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3454997                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.782738                       # Inst execution rate
-system.cpu2.iew.wb_sent                     277647788                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    276821632                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                215782455                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                353891684                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                    10537501                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                28240197                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3473896                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.791692                       # Inst execution rate
+system.cpu2.iew.wb_sent                     277728046                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    276907908                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                215869899                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                354183211                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.776152                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609742                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.785201                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609487                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        9482298                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         362455                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           346445                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    153408349                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.771036                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.652208                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        9010167                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         364904                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           325088                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    152771285                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.780770                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.657176                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     95336110     62.15%     62.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4415580      2.88%     65.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1307869      0.85%     65.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24753928     16.14%     82.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       995070      0.65%     82.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       727248      0.47%     83.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       439603      0.29%     83.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23319103     15.20%     98.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2113838      1.38%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     94646882     61.95%     61.95% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4418156      2.89%     64.85% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1318603      0.86%     65.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24750822     16.20%     81.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       992364      0.65%     82.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       731797      0.48%     83.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       443039      0.29%     83.33% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23300929     15.25%     98.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2168693      1.42%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    153408349                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           137757751                       # Number of instructions committed
-system.cpu2.commit.committedOps             271691665                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    152771285                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           137969360                       # Number of instructions committed
+system.cpu2.commit.committedOps             272050550                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8766278                       # Number of memory references committed
-system.cpu2.commit.loads                      5584968                       # Number of loads committed
-system.cpu2.commit.membars                     161958                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27804222                       # Number of branches committed
+system.cpu2.commit.refs                       8894843                       # Number of memory references committed
+system.cpu2.commit.loads                      5678032                       # Number of loads committed
+system.cpu2.commit.membars                     160530                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27847068                       # Number of branches committed
 system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                248326046                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              453891                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        49969      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       262767573     96.72%     96.73% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          56460      0.02%     96.75% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           51419      0.02%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5584918      2.06%     98.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3181310      1.17%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                248702825                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              458806                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        52824      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       262991815     96.67%     96.69% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          56918      0.02%     96.71% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           54179      0.02%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5677987      2.09%     98.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3216811      1.18%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        271691665                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2113838                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   432438048                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  563770768                       # The number of ROB writes
-system.cpu2.timesIdled                         121162                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1030703                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4911308393                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  137757751                       # Number of Instructions Simulated
-system.cpu2.committedOps                    271691665                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.131368                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.131368                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.883886                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.883886                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               370162227                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              221868711                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    73082                       # number of floating regfile reads
+system.cpu2.commit.op_class_0::total        272050550                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2168693                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   431630642                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  563473683                       # The number of ROB writes
+system.cpu2.timesIdled                         116646                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                         996081                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4908046353                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  137969360                       # Number of Instructions Simulated
+system.cpu2.committedOps                    272050550                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.124257                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.124257                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.889476                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.889476                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               370420908                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              221942656                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73069                       # number of floating regfile reads
 system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                141178662                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               108439379                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               90543264                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                143975                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3552152                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3552152                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57748                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57748                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1661                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1661                       # Transaction distribution
+system.cpu2.cc_regfile_reads                141352578                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               108476747                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               90603281                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                149391                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3552124                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3552124                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57703                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57703                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1656                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1656                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
@@ -1163,15 +1166,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7124542                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3322                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3322                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7223122                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7124404                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95250                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95250                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3312                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3312                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7222966                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
@@ -1187,25 +1190,25 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3568515                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6644                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6644                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6602975                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2788160                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total      3568437                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027784                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027784                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6602845                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2765072                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              5737000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              5295000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
@@ -1213,62 +1216,62 @@ system.iobus.reqLayer8.occupancy                18000                       # La
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy            140109000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              441000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              421000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            11321000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy            11369000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy                4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           105499646                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           144756051                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           300163000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           299839000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            23378000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            30990000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1173000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1161000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47574                       # number of replacements
-system.iocache.tags.tagsinuse                0.102984                       # Cycle average of tags in use
+system.iocache.tags.replacements                47570                       # number of replacements
+system.iocache.tags.tagsinuse                0.092294                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47586                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000591236509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.102984                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006437                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006437                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000591335509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092294                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005768                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005768                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
-system.iocache.tags.data_accesses              428661                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428625                       # Number of tag accesses
+system.iocache.tags.data_accesses              428625                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          905                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              905                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
-system.iocache.overall_misses::total              909                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126015772                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    126015772                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   2387409874                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2387409874                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    126015772                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    126015772                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    126015772                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    126015772                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          905                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               905                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          905                       # number of overall misses
+system.iocache.overall_misses::total              905                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128938756                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    128938756                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3283387295                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   3283387295                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    128938756                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    128938756                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    128938756                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    128938756                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          905                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            905                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          905                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             905                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          905                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            905                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1277,337 +1280,323 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138631.212321                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 138631.212321                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 51100.382577                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 51100.382577                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138631.212321                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 138631.212321                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138631.212321                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 138631.212321                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           218                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142473.763536                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 142473.763536                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70277.981485                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 70277.981485                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142473.763536                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 142473.763536                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142473.763536                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 142473.763536                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   18                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.111111                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          757                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          757                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        20232                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        20232                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          757                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          757                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          757                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          757                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88165772                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     88165772                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1375809874                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1375809874                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     88165772                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     88165772                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     88165772                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     88165772                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.832783                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.832783                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.433048                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.433048                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.832783                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.832783                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.832783                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.832783                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 116467.334214                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68001.674278                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68001.674278                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 116467.334214                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 116467.334214                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          771                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          771                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        27816                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        27816                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          771                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          771                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          771                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          771                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90388756                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     90388756                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1892587295                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1892587295                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     90388756                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     90388756                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     90388756                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     90388756                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.851934                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.851934                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.595377                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.595377                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.851934                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.851934                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.851934                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.851934                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 117235.740597                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68039.520240                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.520240                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 117235.740597                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 117235.740597                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   105183                       # number of replacements
-system.l2c.tags.tagsinuse                64828.721241                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4684115                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169423                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    27.647456                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   105297                       # number of replacements
+system.l2c.tags.tagsinuse                64829.932138                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4653506                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   169379                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    27.473925                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50898.132312                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.126487                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1607.202570                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5199.796885                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      251.414397                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1573.306131                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.399418                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.004770                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1229.783276                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     4062.554995                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.776644                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51173.407982                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134359                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1534.003878                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4961.516829                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      244.491161                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1538.007484                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     8.330522                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1242.728330                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     4127.311591                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.780844                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.024524                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.079343                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003836                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.024007                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000098                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.018765                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.061990                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.989208                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64240                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3044                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6984                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54074                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.980225                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 41790330                       # Number of tag accesses
-system.l2c.tags.data_accesses                41790330                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        18694                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10376                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        14927                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         8452                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        63394                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        13067                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 128910                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.023407                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.075707                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.003731                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.023468                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000127                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.018963                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.062978                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.989226                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64082                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3909                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7185                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52613                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.977814                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 41530530                       # Number of tag accesses
+system.l2c.tags.data_accesses                41530530                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        18603                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        10268                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        13451                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         7422                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        62068                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        13128                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 124940                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1547778                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1547778                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              86                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              61                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data             104                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 251                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            57261                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            38255                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            63793                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               159309                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        284171                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        176684                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        403287                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            864142                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       469690                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       225324                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       620313                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          1315327                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         18694                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         10378                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              284171                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              526951                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         14927                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          8452                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              176684                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              263579                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         63394                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         13067                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              403287                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              684106                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2467690                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        18694                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        10378                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             284171                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             526951                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        14927                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         8452                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             176684                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             263579                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        63394                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        13067                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             403287                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             684106                       # number of overall hits
-system.l2c.overall_hits::total                2467690                       # number of overall hits
+system.l2c.Writeback_hits::writebacks         1547245                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1547245                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              73                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              62                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data             120                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 255                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            56139                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            39496                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            63875                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               159510                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        289595                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        170749                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst        390398                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total            850742                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       472949                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       223727                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data       618198                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          1314874                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         18603                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         10270                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              289595                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              529088                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         13451                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          7422                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              170749                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              263223                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         62068                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker         13128                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              390398                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              682073                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2450068                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        18603                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker        10270                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             289595                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             529088                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        13451                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         7422                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             170749                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             263223                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        62068                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker        13128                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             390398                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             682073                       # number of overall hits
+system.l2c.overall_hits::total                2450068                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           37                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                   43                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           482                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           340                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           597                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1419                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          62694                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          27499                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          40743                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130936                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         5899                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         3148                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         5990                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           15037                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data        15056                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         4564                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data        13637                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total          33257                       # number of ReadSharedReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker           33                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                   38                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data           455                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           314                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data           620                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1389                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63544                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          27850                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          39321                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             130715                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst         5939                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         3363                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst         5766                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           15068                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data        14540                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         4565                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data        13791                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total          32896                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5899                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             77750                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3148                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             32063                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           37                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              5990                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             54380                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                179273                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              5939                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             78084                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              3363                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             32415                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker           33                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              5766                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             53112                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                178717                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5899                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            77750                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3148                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            32063                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           37                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             5990                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            54380                       # number of overall misses
-system.l2c.overall_misses::total               179273                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3871500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker        83000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total        3954500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      6342500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data      7566000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     13908500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   2068321500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   3225771000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   5294092500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    254232000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    507311500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total    761543500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    380479000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   1184076000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   1564555000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    254232000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2448800500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      3871500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker        83000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    507311500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   4409847000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      7624145500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    254232000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2448800500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      3871500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker        83000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    507311500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   4409847000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     7624145500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        18694                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        10381                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        14927                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         8452                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        63431                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        13068                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             128953                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_misses::cpu0.inst             5939                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            78084                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             3363                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            32415                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker           33                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             5766                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            53112                       # number of overall misses
+system.l2c.overall_misses::total               178717                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3062000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total        3062000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      5922500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data      7897000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     13819500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   2097810500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   3123724500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   5221535000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst    269851500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst    492403500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total    762255000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    377324500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data   1213247000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total   1590571500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    269851500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2475135000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker      3062000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    492403500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   4336971500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      7577423500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    269851500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   2475135000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker      3062000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    492403500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   4336971500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     7577423500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        18603                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker        10273                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        13451                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         7422                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        62101                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker        13128                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             124978                       # number of ReadReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1547778                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1547778                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data          568                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          401                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          701                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1670                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       119955                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        65754                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       104536                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           290245                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       290070                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       179832                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst       409277                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total        879179                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       484746                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       229888                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data       633950                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1348584                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        18694                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        10383                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          290070                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          604701                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        14927                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         8452                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          179832                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          295642                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        63431                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        13068                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          409277                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          738486                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2646963                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        18694                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        10383                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         290070                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         604701                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        14927                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         8452                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         179832                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         295642                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        63431                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        13068                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         409277                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         738486                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2646963                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.000333                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.848592                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.847880                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.851641                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.849701                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.522646                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.418210                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.389751                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.451122                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.020336                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.017505                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014636                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.017103                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.031060                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019853                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.021511                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.024661                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.020336                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.128576                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.017505                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.108452                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.014636                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.073637                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.067728                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.020336                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.128576                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.017505                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.108452                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.014636                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.073637                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.067728                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        83000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 91965.116279                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18654.411765                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12673.366834                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  9801.620860                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75214.425979                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79173.624917                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 40432.673214                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80759.847522                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84693.071786                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 50644.643213                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83365.249781                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86828.188018                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 47044.381634                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 80759.847522                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 76374.653027                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 84693.071786                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 81093.177639                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 42528.130282                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 80759.847522                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 76374.653027                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 84693.071786                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 81093.177639                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 42528.130282                       # average overall miss latency
+system.l2c.Writeback_accesses::writebacks      1547245                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1547245                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data          528                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          376                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          740                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1644                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       119683                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        67346                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data       103196                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           290225                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       295534                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       174112                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst       396164                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total        865810                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       487489                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       228292                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data       631989                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      1347770                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        18603                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker        10275                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          295534                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          607172                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        13451                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7422                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          174112                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          295638                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        62101                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        13128                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          396164                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          735185                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2628785                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        18603                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker        10275                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         295534                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         607172                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        13451                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7422                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         174112                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         295638                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        62101                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        13128                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         396164                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         735185                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2628785                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000487                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000531                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.000304                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.861742                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.835106                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.837838                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.844891                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.530936                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.413536                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.381032                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.450392                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.020096                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.019315                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014555                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.017403                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029826                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019996                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.021822                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.024408                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000487                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.020096                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.128603                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.019315                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.109644                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000531                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.014555                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.072243                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.067985                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000487                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.020096                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.128603                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.019315                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.109644                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000531                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.014555                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.072243                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.067985                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 92787.878788                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 80578.947368                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18861.464968                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12737.096774                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  9949.244060                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75325.332136                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79441.634241                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 39945.951115                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80241.302409                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85397.762747                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 50587.669233                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82655.969332                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 87973.823508                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 48351.516902                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80241.302409                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 76357.704766                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 92787.878788                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 85397.762747                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 81657.092559                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 42399.007929                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80241.302409                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 76357.704766                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 92787.878788                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 85397.762747                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 81657.092559                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 42399.007929                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1616,228 +1605,206 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               97055                       # number of writebacks
-system.l2c.writebacks::total                    97055                       # number of writebacks
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           37                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total              38                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks           56                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total           56                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          340                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          597                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          937                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        27499                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        40743                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         68242                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         3148                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5989                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total         9137                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4564                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        13637                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total        18201                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         3148                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        32063                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           37                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         5989                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        54380                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            95618                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         3148                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        32063                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           37                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         5989                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        54380                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           95618                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data       186036                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data       204987                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total       391023                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3332                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4183                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total         7515                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data       189368                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data       209170                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       398538                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        73000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total      3574500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7682000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     12454500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     20136500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1793331500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2818341000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4611672500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    222752000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    447349500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    670101500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    334839000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1048075000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1382914000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    222752000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   2128170500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        73000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    447349500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3866416000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6668262500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    222752000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   2128170500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        73000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    447349500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3866416000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6668262500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28284583500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30647941500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  58932525000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    553645000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    789702500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1343347500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28838228500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31437644000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  60275872500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000583                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000077                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.000295                       # mshr miss rate for ReadReq accesses
+system.l2c.writebacks::writebacks               96985                       # number of writebacks
+system.l2c.writebacks::total                    96985                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           33                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total              33                       # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks           60                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total           60                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          314                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          620                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          934                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        27850                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        39321                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         67171                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         3363                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5766                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         9129                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4565                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        13791                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total        18356                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         3363                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        32415                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           33                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         5766                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        53112                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            94689                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         3363                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        32415                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           33                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         5766                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        53112                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           94689                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data       186313                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data       204652                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total       390965                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3641                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         3691                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total         7332                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data       189954                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data       208343                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       398297                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2732000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total      2732000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7099500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     13006500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     20106000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1819310500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2730514500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4549825000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    236221500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    434743500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    670965000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    331674500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1075337000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   1407011500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    236221500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2150985000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2732000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    434743500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3805851500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6630533500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    236221500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2150985000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2732000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    434743500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3805851500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6630533500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28337960500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30586872000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  58924832500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    608808000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    708573000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1317381000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28946768500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31295445000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60242213500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000531                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.000264                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.847880                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.851641                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.561078                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.418210                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.389751                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.235119                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017505                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014633                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010393                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019853                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.021511                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.013496                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017505                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.108452                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000583                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000077                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014633                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.073637                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.036124                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017505                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.108452                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000583                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000077                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014633                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.073637                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.036124                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 94065.789474                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22594.117647                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20861.809045                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21490.394877                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65214.425979                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69173.624917                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.214296                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74695.191184                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73339.334574                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73365.249781                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.246755                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.110983                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66374.653027                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74695.191184                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71099.963222                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69738.569098                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66374.653027                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74695.191184                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71099.963222                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69738.569098                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152038.226472                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149511.634884                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150713.704820                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166159.963986                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188788.548888                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178755.489022                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152286.703667                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150297.098054                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 151242.472487                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.835106                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.837838                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.568127                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.413536                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.381032                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.231445                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019315                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014555                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010544                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019996                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.021822                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.013620                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.019315                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.109644                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000531                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014555                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.072243                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.036020                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.019315                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.109644                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000531                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014555                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.072243                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.036020                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 82787.878788                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22609.872611                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20978.225806                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21526.766595                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65325.332136                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69441.634241                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 67734.960027                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70241.302409                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75397.762747                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73498.192573                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72655.969332                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77973.823508                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76651.312922                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70241.302409                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66357.704766                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75397.762747                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71657.092559                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 70024.327007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70241.302409                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66357.704766                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75397.762747                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71657.092559                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 70024.327007                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152098.675347                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149457.967672                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150716.387656                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167209.008514                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191973.178001                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 179675.531915                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152388.307169                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150211.166202                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 151249.478404                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5067102                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5116344                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13938                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13938                       # Transaction distribution
-system.membus.trans_dist::Writeback            143722                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8694                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1684                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1684                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130671                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130671                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         49245                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1661                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1661                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            3                       # Transaction distribution
+system.membus.trans_dist::ReadReq             5066901                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5115808                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13888                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13888                       # Transaction distribution
+system.membus.trans_dist::Writeback            143652                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8856                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1645                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1645                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130459                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130459                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         48907                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1656                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1656                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3322                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3322                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7124542                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3037538                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       466123                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            6                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10628209                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142133                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       142133                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10773664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6644                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6644                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3568515                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6075073                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17638016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27281604                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3024768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3024768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                30313016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              794                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5463823                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.000304                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.017433                       # Request fanout histogram
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3312                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3312                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7124404                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3037174                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       465190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total     10626768                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142086                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       142086                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10772166                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3568437                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6074345                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17606208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27248990                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3023616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3023616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                30279230                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              694                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5463095                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.000303                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.017408                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5462162     99.97%     99.97% # Request fanout histogram
-system.membus.snoop_fanout::2                    1661      0.03%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5461439     99.97%     99.97% # Request fanout histogram
+system.membus.snoop_fanout::2                    1656      0.03%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             5463823                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           233077000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5463095                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           232635000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           304111500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           304127000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2346000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2322000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           540335137                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           583726731                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                4500                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1173000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1161000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1355052899                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1349926167                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           39163714                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           52433855                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -1847,54 +1814,53 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            5228129                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7456139                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13940                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13940                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1629241                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          974526                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1670                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1670                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           290245                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          290245                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        879202                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1349341                       # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq            1173                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            3                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        20232                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2636646                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15081470                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73733                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       221081                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              18012930                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56268288                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213600772                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       270696                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       799584                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              270939340                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          164260                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         10415384                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.028580                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.166622                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            5228525                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7442369                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13890                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13890                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          1636010                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          961008                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1644                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1644                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           290225                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          290225                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        865835                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1348541                       # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq            1161                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        27816                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2596558                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15078411                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        72306                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       219403                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17966678                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55412672                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213513438                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       261576                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       779088                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              269966774                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          176011                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         10394757                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.029410                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.168953                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               10117715     97.14%     97.14% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 297669      2.86%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               10089048     97.06%     97.06% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 305709      2.94%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           10415384                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2866108499                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           10394757                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2840392499                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           340500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           358500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         884325204                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         856033294                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1946611318                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1941516813                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          27584988                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          27469982                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          99698688                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         100352159                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
index 096700e63..898984ead 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -46,7 +46,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

 ACPI: Unable to load the System Description Tables

 Using local APIC timer interrupts.

-result 7812519

+result 7812539

 Detected 7.812 MHz APIC timer.

 NET: Registered protocol family 16

 PCI: Using configuration type 1

diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
index f3e5c9bf3..feb4be957 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
@@ -3,6 +3,7 @@
     "sim_quantum": 0, 
     "system": {
         "kernel": "", 
+        "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "rom": {
             "range": "1099243192320:1099251580927", 
@@ -57,9 +58,9 @@
                 "role": "SLAVE"
             }, 
             "name": "iobus", 
+            "forward_latency": 1, 
             "clk_domain": "system.clk_domain", 
-            "header_cycles": 1, 
-            "width": 8, 
+            "width": 16, 
             "eventq_index": 0, 
             "master": {
                 "peer": [
@@ -81,10 +82,12 @@
                 ], 
                 "role": "MASTER"
             }, 
+            "response_latency": 2, 
             "cxx_class": "NoncoherentXBar", 
             "path": "system.iobus", 
             "type": "NoncoherentXBar", 
-            "use_default_range": false
+            "use_default_range": false, 
+            "frontend_latency": 2
         }, 
         "t1000": {
             "htod": {
@@ -484,11 +487,11 @@
         "work_end_ckpt_count": 0, 
         "nvram_addr": 133429198848, 
         "memories": [
-            "system.nvram", 
-            "system.physmem1", 
             "system.hypervisor_desc", 
+            "system.nvram", 
             "system.partition_desc", 
             "system.physmem0", 
+            "system.physmem1", 
             "system.rom"
         ], 
         "work_begin_ckpt_count": 0, 
@@ -582,10 +585,10 @@
                 "ret_data16": 65535
             }, 
             "snoop_filter": null, 
+            "forward_latency": 4, 
             "clk_domain": "system.clk_domain", 
-            "header_cycles": 1, 
             "system": "system", 
-            "width": 8, 
+            "width": 16, 
             "eventq_index": 0, 
             "master": {
                 "peer": [
@@ -601,10 +604,13 @@
                 ], 
                 "role": "MASTER"
             }, 
+            "response_latency": 2, 
             "cxx_class": "CoherentXBar", 
             "path": "system.membus", 
+            "snoop_response_latency": 4, 
             "type": "CoherentXBar", 
-            "use_default_range": false
+            "use_default_range": false, 
+            "frontend_latency": 3
         }, 
         "nvram": {
             "range": "133429198848:133429207039", 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
index 3938653f4..8b738959d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
index be80117c3..d0ca2b5a8 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 02:29:01
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x45a0240
 info: Entering event queue @ 0.  Starting simulation...
 
 MCF SPEC version 1.6.I
@@ -24,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 61589191500 because target called exit()
+Exiting @ tick 61240850500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index 1f83c039b..8f24165d3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061280                       # Number of seconds simulated
-sim_ticks                                 61279840500                       # Number of ticks simulated
-final_tick                                61279840500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061241                       # Number of seconds simulated
+sim_ticks                                 61240850500                       # Number of ticks simulated
+final_tick                                61240850500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 263178                       # Simulator instruction rate (inst/s)
-host_op_rate                                   264489                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              178002192                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447788                       # Number of bytes of host memory used
-host_seconds                                   344.26                       # Real time elapsed on the host
+host_inst_rate                                 182783                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183693                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              123547949                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 442472                       # Number of bytes of host memory used
+host_seconds                                   495.69                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           49536                       # Nu
 system.physmem.num_reads::cpu.inst                774                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14800                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               808357                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15456959                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16265316                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          808357                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             808357                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              808357                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15456959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16265316                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               808872                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15466800                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16275672                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          808872                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             808872                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              808872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15466800                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16275672                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                         15574                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61279747000                       # Total gap between requests
+system.physmem.totGap                     61240757000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1531                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      650.032658                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     444.829113                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     399.661041                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            243     15.87%     15.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          186     12.15%     28.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           73      4.77%     32.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           65      4.25%     37.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           75      4.90%     41.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          100      6.53%     48.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           43      2.81%     51.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           51      3.33%     54.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          695     45.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1531                       # Bytes accessed per row activation
-system.physmem.totQLat                       71795500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 363808000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1544                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      644.601036                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     438.502120                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     402.393837                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            247     16.00%     16.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          189     12.24%     28.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           92      5.96%     34.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           68      4.40%     38.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           69      4.47%     43.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           87      5.63%     48.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           40      2.59%     51.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           47      3.04%     54.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          705     45.66%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1544                       # Bytes accessed per row activation
+system.physmem.totQLat                       73458500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 365471000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4609.96                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        4716.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23359.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          16.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23466.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          16.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       16.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       16.28                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
@@ -216,48 +216,48 @@ system.physmem.busUtilRead                       0.13                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14039                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14026                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.14                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.06                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3934746.82                       # Average gap between requests
-system.physmem.pageHitRate                      90.14                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6259680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3415500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  63772800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      3932243.29                       # Average gap between requests
+system.physmem.pageHitRate                      90.06                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6305040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3440250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  63780600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4002367200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2491685460                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34581139500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41148640140                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.507037                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57518843500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2046200000                       # Time in different power states
+system.physmem_0.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2494978920                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34554891750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41123220960                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.518851                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57475186750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2044900000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1713017750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1719043250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5314680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2899875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                    5367600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2928750                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                  57517200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4002367200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2548940535                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34530915750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41147955240                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.495861                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57435989500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2046200000                       # Time in different power states
+system.physmem_1.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2555622360                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34501695750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41122956060                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.514525                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57387265750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2044900000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1796249000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1807269750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20766613                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17069686                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            765538                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8958713                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8857097                       # Number of BTB hits
+system.cpu.branchPred.lookups                20752188                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17062075                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            757746                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8939036                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8856390                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.865730                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   62715                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             99.075448                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   61984                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,67 +377,67 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        122559681                       # number of cpu cycles simulated
+system.cpu.numCycles                        122481701                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602850                       # Number of instructions committed
 system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2197712                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2176622                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.352713                       # CPI: cycles per instruction
-system.cpu.ipc                               0.739255                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109336366                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13223315                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            946108                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3616.962336                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26267632                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            950204                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.644203                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20520732500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3616.962336                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.883047                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.883047                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.351853                       # CPI: cycles per instruction
+system.cpu.ipc                               0.739726                       # IPC: instructions per cycle
+system.cpu.tickCycles                       109255125                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13226576                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            946097                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3616.871508                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26263183                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            950193                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.639841                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20511562500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3616.871508                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.883025                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.883025                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          254                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2248                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2246                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         1594                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55463928                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55463928                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21598652                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21598652                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4660698                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4660698                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          55455001                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55455001                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21594211                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21594211                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4660690                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4660690                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           508                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26259350                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26259350                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26259858                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26259858                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       914943                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        914943                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        74283                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        74283                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      26254901                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26254901                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26255409                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26255409                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       914926                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        914926                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        74291                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        74291                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       989226                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         989226                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       989230                       # number of overall misses
-system.cpu.dcache.overall_misses::total        989230                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11918923000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11918923000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2541568000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2541568000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14460491000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14460491000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14460491000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14460491000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22513595                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22513595                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       989217                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         989217                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       989221                       # number of overall misses
+system.cpu.dcache.overall_misses::total        989221                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11918942500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11918942500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2542548000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2542548000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14461490500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14461490500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14461490500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14461490500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22509137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22509137                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          512                       # number of SoftPFReq accesses(hits+misses)
@@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27248576                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27248576                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27249088                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27249088                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040640                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040640                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015688                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015688                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     27244118                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27244118                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27244630                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27244630                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040647                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040647                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015690                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015690                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036304                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036304                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036303                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036303                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.956871                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.956871                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34214.665536                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34214.665536                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14617.985172                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14617.985172                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.926064                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14617.926064                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036309                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036309                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036309                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036309                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14619.128563                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14619.069450                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       943289                       # number of writebacks
-system.cpu.dcache.writebacks::total            943289                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11509                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11509                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27516                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27516                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39025                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39025                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39025                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39025                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903434                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903434                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46767                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46767                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       943278                       # number of writebacks
+system.cpu.dcache.writebacks::total            943278                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11501                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11501                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27526                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27526                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        39027                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39027                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39027                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39027                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903425                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903425                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46765                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46765                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       950201                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       950201                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       950204                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       950204                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865211000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865211000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1480610000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1480610000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       950190                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       950190                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       950193                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       950193                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865257500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865257500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1481584500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1481584500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       156500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       156500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12345821000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12345821000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12345977500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12345977500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040128                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040128                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009877                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009877                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12346842000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12346842000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12346998500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12346998500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040136                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040136                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005859                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005859                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034872                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034872                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034871                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034871                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.568626                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.568626                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31659.289670                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31659.289670                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034877                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034877                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034876                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034876                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.852039                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.852039                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.975719                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.975719                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           690.428077                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27792848                       # Total number of references to valid blocks.
+system.cpu.icache.tags.replacements                 5                       # number of replacements
+system.cpu.icache.tags.tagsinuse           689.439690                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27770466                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34654.423940                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34626.516209                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   690.428077                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.337123                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.337123                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   689.439690                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.336640                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.336640                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          797                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          741                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.389648                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55588102                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55588102                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27792848                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27792848                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27792848                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27792848                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27792848                       # number of overall hits
-system.cpu.icache.overall_hits::total        27792848                       # number of overall hits
+system.cpu.icache.tags.age_task_id_blocks_1024::4          740                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.389160                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          55543338                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55543338                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27770466                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27770466                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27770466                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27770466                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27770466                       # number of overall hits
+system.cpu.icache.overall_hits::total        27770466                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           802                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     59599500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     59599500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     59599500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     59599500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     59599500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     59599500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27793650                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27793650                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27793650                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27793650                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27793650                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27793650                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     60107000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     60107000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     60107000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     60107000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     60107000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     60107000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27771268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27771268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27771268                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27771268                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27771268                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27771268                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74313.591022                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74313.591022                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74313.591022                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74313.591022                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74313.591022                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74313.591022                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 74946.384040                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 74946.384040                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          802
 system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     58797500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     58797500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     58797500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     58797500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     58797500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     58797500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     59305000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     59305000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     59305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     59305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     59305000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     59305000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73313.591022                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73313.591022                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73313.591022                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73313.591022                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73313.591022                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73313.591022                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10246.423743                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1834010                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10245.543243                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1833992                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           117.889696                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           117.888539                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9356.530979                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.454442                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   215.438322                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.285539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020583                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  9355.642515                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.444420                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   215.456307                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.285512                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020582                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006575                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.312696                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.312669                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        15557                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
@@ -632,22 +632,22 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1095                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13876                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15238060                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15238060                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       943289                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       943289                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        32223                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32223                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses         15237898                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15237898                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       943278                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       943278                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32221                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32221                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           26                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total           26                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903175                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       903175                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903166                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       903166                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           26                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       935398                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          935424                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       935387                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          935413                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           26                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       935398                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         935424                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       935387                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         935413                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14544                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          776                       # number of ReadCleanReq misses
@@ -660,34 +660,34 @@ system.cpu.l2cache.demand_misses::total         15582                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          776                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14806                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1066648000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1066648000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57320500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     57320500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     21756000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     21756000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     57320500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1088404000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1145724500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     57320500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1088404000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1145724500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       943289                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       943289                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        46767                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46767                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1067640500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1067640500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57828000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     57828000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     21914500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     21914500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     57828000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1089555000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1147383000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     57828000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1089555000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1147383000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       943278                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       943278                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46765                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46765                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          802                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total          802                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       903437                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       903437                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       903428                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       903428                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       950204                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       951006                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       950193                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       950995                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       950204                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       951006                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.310989                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.310989                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_accesses::cpu.data       950193                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       950995                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311002                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.311002                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.967581                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.967581                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000290                       # miss rate for ReadSharedReq accesses
@@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.016385                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967581                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015582                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016385                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73339.383938                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73339.383938                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73866.623711                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73866.623711                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83038.167939                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83038.167939                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73866.623711                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73511.009050                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73528.719035                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73866.623711                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73511.009050                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73528.719035                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -740,73 +740,73 @@ system.cpu.l2cache.demand_mshr_misses::total        15574
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14800                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    921208000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    921208000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     49433000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     49433000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18805000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18805000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     49433000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    940013000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    989446000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     49433000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    940013000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    989446000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.310989                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.310989                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    922200500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    922200500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     49941000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     49941000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18963500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18963500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     49941000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    941164000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    991105000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     49941000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    941164000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    991105000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311002                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311002                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965087                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000283                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000283                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016376                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016376                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63339.383938                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63339.383938                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63866.925065                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63866.925065                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73457.031250                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73457.031250                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63866.925065                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63514.391892                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63531.912161                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63866.925065                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63514.391892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63531.912161                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        904239                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       943289                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         2672                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46767                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46767                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        904230                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       943278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2674                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        46765                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46765                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          802                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       903437                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1607                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2846366                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2847973                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       903428                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1608                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2846334                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2847942                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121183552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          121234880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121182144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          121233472                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1897118                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      1897097                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1897118    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1897097    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1897118                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1891848000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1897097                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1891826500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1203998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1425308994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1425292494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
@@ -827,9 +827,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21740500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            21739500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82134000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82130500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index a092bf499..86dba512f 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -688,9 +688,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index eaa0003ec..976e948eb 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,13 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 11:34:28
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 02:12:41
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x299b730
 info: Entering event queue @ 0.  Starting simulation...
 
 MCF SPEC version 1.6.I
@@ -25,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 58202727500 because target called exit()
+Exiting @ tick 58182114500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 263d31358..a3f3e3177 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -118,7 +118,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -166,7 +166,7 @@ eventq_index=0
 size=64
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 009ef705f..e66d5ccc4 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,13 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 19:43:22
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+gem5 compiled Sep 14 2015 22:05:26
+gem5 started Sep 14 2015 22:06:13
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 361488530000 because target called exit()
+Exiting @ tick 361488535500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index 399eedece..d4aa178ac 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -156,7 +156,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -513,7 +513,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -579,7 +579,7 @@ system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -642,9 +642,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index d8c79ae54..efb33d70a 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 08:10:29
-gem5 started Apr 22 2015 09:28:24
-gem5 executing on phenom
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled Sep 14 2015 22:13:36
+gem5 started Sep 14 2015 22:43:54
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -17,12 +19,12 @@ All Rights Reserved.
 nodes                      : 500
 active arcs                : 1905
 simplex iterations         : 1502
+info: Increasing stack size by one page.
 flow value                 : 4990014995
 new implicit arcs          : 23867
 active arcs                : 25772
 simplex iterations         : 2663
-info: Increasing stack size by one page.
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 62113055500 because target called exit()
+Exiting @ tick 61602395500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 6f4514f73..40c2eacfb 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,75 +1,75 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.062104                       # Number of seconds simulated
-sim_ticks                                 62103992500                       # Number of ticks simulated
-final_tick                                62103992500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061602                       # Number of seconds simulated
+sim_ticks                                 61602395500                       # Number of ticks simulated
+final_tick                                61602395500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 108853                       # Simulator instruction rate (inst/s)
-host_op_rate                                   191673                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42789284                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455804                       # Number of bytes of host memory used
-host_seconds                                  1451.39                       # Real time elapsed on the host
+host_inst_rate                                  83209                       # Simulator instruction rate (inst/s)
+host_op_rate                                   146518                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               32444685                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451056                       # Number of bytes of host memory used
+host_seconds                                  1898.69                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             64832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1883648                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1948480                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        64832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           64832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst             63872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1883136                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1947008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        63872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           63872                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks        11776                       # Number of bytes written to this memory
 system.physmem.bytes_written::total             11776                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1013                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29432                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30445                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                998                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30422                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks             184                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  184                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1043926                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             30330546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                31374472                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1043926                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1043926                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            189617                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 189617                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            189617                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1043926                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            30330546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               31564090                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30446                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst              1036843                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             30569201                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                31606044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1036843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1036843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            191161                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 191161                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            191161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1036843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            30569201                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               31797205                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30422                       # Number of read requests accepted
 system.physmem.writeReqs                          184                       # Number of write requests accepted
-system.physmem.readBursts                       30446                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       30422                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                        184                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1943488                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                  1941952                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      5056                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     10368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1948544                       # Total read bytes from the system interface side
+system.physmem.bytesWritten                     10304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1947008                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                  11776                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                       79                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1927                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2069                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2026                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1929                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1928                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2065                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2023                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1928                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                2026                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1901                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1959                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1865                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1952                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1864                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1937                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               1796                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1932                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               1804                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1819                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  25                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  94                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   8                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                  82                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  28                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   6                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                  13                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     62103972000                       # Total gap between requests
+system.physmem.totGap                     61602210500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30446                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30422                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                    184                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29885                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        75                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        21                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     29859                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,8 +144,8 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                       10                       # What write queue length does an incoming req see
@@ -153,7 +153,7 @@ system.physmem.wrQLenPdf::20                       10                       # Wh
 system.physmem.wrQLenPdf::21                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                        9                       # What write queue length does an incoming req see
@@ -193,324 +193,326 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2720                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      718.117647                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     516.851204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     389.329010                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            349     12.83%     12.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          252      9.26%     22.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          126      4.63%     26.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          106      3.90%     30.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          106      3.90%     34.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          118      4.34%     38.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           88      3.24%     42.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           74      2.72%     44.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1501     55.18%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2720                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples         2722                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      716.414401                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     516.531797                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     387.717070                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            355     13.04%     13.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          240      8.82%     21.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          126      4.63%     26.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          120      4.41%     30.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           92      3.38%     34.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          131      4.81%     39.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          110      4.04%     43.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           67      2.46%     45.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1481     54.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2722                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples             9                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3367.333333                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       25.147360                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    10062.626521                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3364.888889                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       25.331779                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    10055.293027                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023              8     88.89%     88.89% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::29696-30719            1     11.11%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total               9                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples             9                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  9    100.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.888889                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.873018                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.781736                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  1     11.11%     11.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  7     77.78%     88.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1     11.11%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total               9                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      131808750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 701190000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151835000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4340.53                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                      132992250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 701923500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    151715000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4382.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23090.53                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          31.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23132.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          31.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       31.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       31.61                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.19                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.25                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.24                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.25                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        13.82                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27697                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       108                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.21                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2027553.77                       # Average gap between requests
-system.physmem.pageHitRate                      91.01                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   10848600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    5919375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 122421000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   997920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4056274560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2874471525                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34740567750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41811500730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              673.256335                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57777967000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2073760000                       # Time in different power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        15.66                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27667                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       105                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   91.18                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  57.38                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2012749.48                       # Average gap between requests
+system.physmem.pageHitRate                      90.98                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   10924200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    5960625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 122031000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   991440                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2832651765                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34473588000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41469365190                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              673.233667                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57335439750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2056860000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2251676750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2206407250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    9714600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    5300625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 114371400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    9608760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    5242875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 114207600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4056274560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3081237030                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34559194500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41826144555                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              673.492132                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57475856750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2073760000                       # Time in different power states
+system.physmem_1.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3020113080                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34309140000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41481582315                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              673.432156                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57061058750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2056860000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2554341750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2480990750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37407153                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          37407153                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            797525                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             21397569                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21291133                       # Number of BTB hits
+system.cpu.branchPred.lookups                36908902                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          36908902                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            741640                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             21094595                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21013332                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.502579                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5522199                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               5378                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.614769                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5443329                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               4414                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        124207986                       # number of cpu cycles simulated
+system.cpu.numCycles                        123204792                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           28243826                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      201531916                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37407153                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           26813332                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      95053081                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1666271                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                          3                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  874                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         14570                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           27815548                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      199030226                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36908902                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           26456661                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      94542157                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1553197                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  368                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5286                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                  27854872                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                208775                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          124145503                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.860655                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.369153                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  27443892                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                182896                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          123139971                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.847273                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.366420                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 63227150     50.93%     50.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3664165      2.95%     53.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3505505      2.82%     56.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5966108      4.81%     61.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7642313      6.16%     67.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5450974      4.39%     72.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3347715      2.70%     74.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2079081      1.67%     76.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 29262492     23.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 62945586     51.12%     51.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3649644      2.96%     54.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3480667      2.83%     56.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5913875      4.80%     61.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7544210      6.13%     67.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5413973      4.40%     72.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3251113      2.64%     74.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2020097      1.64%     76.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 28920806     23.49%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            124145503                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.301165                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.622536                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13298609                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63688691                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  36532978                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9792090                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 833135                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              335053232                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 833135                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18606460                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8830273                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          16174                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  40807487                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              55051974                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              328692220                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2265                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 765831                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               48323645                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4961410                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           330669691                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             873156420                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        537756143                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               567                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            123139971                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.299574                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.615442                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12941533                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63708539                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  35887594                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9825707                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 776598                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              331225454                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 776598                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18253440                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8529181                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          16791                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  40202739                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              55361222                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              325142962                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1786                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 778279                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               48626761                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4947640                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           327068193                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             863737847                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        532004044                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               425                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 51456944                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            481                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  66169497                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            106330183                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            36531613                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          49817317                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8395275                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  325507363                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2500                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 308019505                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             50533                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        47317399                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     68952386                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2055                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     124145503                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.481117                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.143684                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 47855446                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                492                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            490                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  66412230                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            105336194                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            36169393                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          49402360                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8500454                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  322302016                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1714                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 306103022                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             45906                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        44111266                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     63884636                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1269                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     123139971                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.485814                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.139103                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30872061     24.87%     24.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19525697     15.73%     40.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            16787256     13.52%     54.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17357634     13.98%     68.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            14846406     11.96%     80.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12689504     10.22%     90.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6302474      5.08%     95.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3917362      3.16%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1847109      1.49%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            30260082     24.57%     24.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19566754     15.89%     40.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            16687046     13.55%     54.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17331207     14.07%     68.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            14759369     11.99%     80.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12567445     10.21%     90.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6273255      5.09%     95.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3904180      3.17%     98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1790633      1.45%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       124145503                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       123139971                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  329941      8.31%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3456308     87.04%     95.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                184474      4.65%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  338797      8.53%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3433517     86.49%     95.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                197609      4.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             33338      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             175410718     56.95%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11212      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   340      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  38      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             98529790     31.99%     88.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34034069     11.05%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             33341      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             174121945     56.88%     56.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11182      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   343      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             98066351     32.04%     88.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            33869829     11.06%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              308019505                       # Type of FU issued
-system.cpu.iq.rate                           2.479869                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3970723                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012891                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          744205245                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         372866875                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    306008038                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 524                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                864                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          168                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              311956642                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     248                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         58273942                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              306103022                       # Type of FU issued
+system.cpu.iq.rate                           2.484506                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3969923                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012969                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          739361487                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         366454631                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    304282654                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 357                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                618                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          133                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              310039424                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     180                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         58196276                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     15550798                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        67136                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41716                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      5091861                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     14556809                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        63678                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        41328                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4729641                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3678                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        142532                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3641                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        141546                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 833135                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5706209                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3030570                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           325509863                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            125935                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             106330183                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             36531613                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                471                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2800                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3033928                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41716                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         402612                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       445047                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               847659                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             306958421                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              98183223                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1061084                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 776598                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5329301                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3100547                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           322303730                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             76830                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             105336194                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             36169393                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                475                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2588                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3102570                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          41328                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         371679                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       414777                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               786456                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             305156723                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              97750585                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            946299                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    132003276                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31537655                       # Number of branches executed
-system.cpu.iew.exec_stores                   33820053                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.471326                       # Inst execution rate
-system.cpu.iew.wb_sent                      306335531                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     306008206                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 231609196                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 336109097                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    131430383                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31401847                       # Number of branches executed
+system.cpu.iew.exec_stores                   33679798                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.476825                       # Inst execution rate
+system.cpu.iew.wb_sent                      304565841                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     304282787                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 230213925                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 333861001                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.463676                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.689089                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.469732                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.689550                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        47420049                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        44209684                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            798401                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    117693042                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.363712                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.086908                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            742009                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    117119203                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.375293                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.092758                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     53351319     45.33%     45.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     15952359     13.55%     58.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     10962553      9.31%     68.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8763534      7.45%     75.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1923790      1.63%     77.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1729278      1.47%     78.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       853123      0.72%     79.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       692579      0.59%     80.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23464507     19.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     52926109     45.19%     45.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     15815586     13.50%     58.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     10978620      9.37%     68.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8749339      7.47%     75.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1860123      1.59%     77.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1720770      1.47%     78.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       865930      0.74%     79.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       690109      0.59%     79.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23512617     20.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    117693042                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    117119203                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -556,330 +558,334 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23464507                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    419841048                       # The number of ROB reads
-system.cpu.rob.rob_writes                   657686557                       # The number of ROB writes
-system.cpu.timesIdled                             566                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           62483                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              23512617                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    416008734                       # The number of ROB reads
+system.cpu.rob.rob_writes                   650833809                       # The number of ROB writes
+system.cpu.timesIdled                             568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           64821                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.786183                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.786183                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.271968                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.271968                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                493729388                       # number of integer regfile reads
-system.cpu.int_regfile_writes               240917610                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       146                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       96                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107705980                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 64576396                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               196329384                       # number of misc regfile reads
+system.cpu.cpi                               0.779834                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.779834                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.282325                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.282325                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                491477122                       # number of integer regfile reads
+system.cpu.int_regfile_writes               239432261                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       110                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       84                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107533023                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 64416979                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               195275944                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2072430                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.090496                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            68424035                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076526                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             32.951206                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       19739908500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.090496                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993186                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993186                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2072313                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.012942                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            68071048                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2076409                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             32.783063                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       19455459500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.012942                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993167                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993167                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          595                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3373                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          630                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3339                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         144493228                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        144493228                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     37078222                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        37078222                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345813                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345813                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68424035                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68424035                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68424035                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68424035                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2690377                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2690377                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93939                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93939                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2784316                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2784316                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2784316                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2784316                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32316565000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32316565000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2955969494                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2955969494                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35272534494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35272534494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35272534494                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35272534494                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     39768599                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     39768599                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         143788667                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        143788667                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     36725223                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        36725223                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31345824                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31345824                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68071047                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68071047                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68071047                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68071047                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2691154                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2691154                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93928                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93928                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2785082                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2785082                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2785082                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2785082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32304422000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32304422000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2956618494                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2956618494                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35261040494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35261040494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35261040494                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35261040494                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     39416377                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     39416377                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     71208351                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     71208351                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     71208351                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     71208351                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.067651                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.067651                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     70856129                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     70856129                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     70856129                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     70856129                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068275                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.068275                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002988                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.002988                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.039101                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.039101                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039101                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039101                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12668.294293                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12668.294293                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       221313                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.039306                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.039306                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039306                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039306                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12660.683059                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12660.683059                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       221512                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             43094                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             43222                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.135587                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.124983                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066711                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066711                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       695911                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       695911                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11877                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        11877                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       707788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       707788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       707788                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       707788                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994466                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994466                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82062                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82062                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076528                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076528                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076528                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076528                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24203306500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24203306500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2798613994                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2798613994                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27001920494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  27001920494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27001920494                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27001920494                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050152                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050152                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks      2066601                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066601                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       696788                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       696788                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11884                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        11884                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       708672                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       708672                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       708672                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       708672                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994366                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994366                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82044                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82044                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076410                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076410                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076410                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076410                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24196094000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24196094000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2799396995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2799396995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26995490995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26995490995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26995490995                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26995490995                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050597                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050597                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002610                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002610                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029161                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029161                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029161                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029161                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029305                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029305                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                64                       # number of replacements
-system.cpu.icache.tags.tagsinuse           833.320748                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27853507                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1032                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          26989.832364                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                53                       # number of replacements
+system.cpu.icache.tags.tagsinuse           825.040012                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27442569                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1013                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          27090.393880                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   833.320748                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.406895                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.406895                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          968                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          876                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.472656                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55710776                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55710776                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27853507                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27853507                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27853507                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27853507                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27853507                       # number of overall hits
-system.cpu.icache.overall_hits::total        27853507                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1365                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1365                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1365                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1365                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1365                       # number of overall misses
-system.cpu.icache.overall_misses::total          1365                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     98783500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     98783500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     98783500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     98783500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     98783500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     98783500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27854872                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27854872                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27854872                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27854872                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27854872                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27854872                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000049                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000049                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000049                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000049                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000049                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72368.864469                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72368.864469                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72368.864469                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72368.864469                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72368.864469                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72368.864469                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          217                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   825.040012                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.402852                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.402852                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          960                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          870                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.468750                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          54888798                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         54888798                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27442569                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27442569                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27442569                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27442569                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27442569                       # number of overall hits
+system.cpu.icache.overall_hits::total        27442569                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1323                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1323                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1323                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1323                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1323                       # number of overall misses
+system.cpu.icache.overall_misses::total          1323                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     97269000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     97269000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     97269000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     97269000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     97269000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     97269000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27443892                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27443892                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27443892                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27443892                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27443892                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27443892                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000048                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000048                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73521.541950                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73521.541950                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    72.333333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          333                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          333                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          333                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          333                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          333                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          333                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1032                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1032                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1032                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1032                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1032                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1032                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     78148000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     78148000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     78148000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     78148000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     78148000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     78148000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          309                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          309                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          309                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          309                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          309                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          309                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1014                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1014                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1014                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1014                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1014                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1014                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     77416000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     77416000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     77416000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     77416000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     77416000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     77416000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.806202                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.806202                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.806202                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.806202                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.806202                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.806202                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              495                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20681.782708                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4035350                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30428                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.619627                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements              487                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20712.335895                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4035103                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30405                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           132.711824                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19745.210929                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   683.118816                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   253.452964                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.602576                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020847                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007735                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.631158                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29933                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          776                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1394                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27641                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913483                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33312880                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33312880                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2066711                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2066711                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53096                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53096                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           19                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           19                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1993999                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1993999                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           19                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2047095                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2047114                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           19                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2047095                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2047114                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        28996                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        28996                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1013                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1013                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          437                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          437                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1013                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29433                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30446                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1013                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29433                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30446                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2117372000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2117372000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     76394500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     76394500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     33330500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     33330500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     76394500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   2150702500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   2227097000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     76394500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   2150702500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   2227097000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2066711                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2066711                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82092                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82092                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1032                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1032                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1994436                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1994436                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1032                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076528                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077560                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1032                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076528                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077560                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.353213                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.353213                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.981589                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.981589                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000219                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000219                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.981589                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014174                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014655                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.981589                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014174                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014655                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73022.899710                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73022.899710                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75414.116486                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75414.116486                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76271.167048                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76271.167048                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75414.116486                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.127646                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73149.083623                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75414.116486                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.127646                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73149.083623                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.841934                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   245.917530                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.603991                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020595                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.007505                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.632090                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29918                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          780                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1385                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27629                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913025                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33310467                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33310467                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2066601                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2066601                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        53071                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        53071                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           16                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           16                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1993914                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1993914                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2046985                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2047001                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2046985                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2047001                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data        28998                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        28998                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          998                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          998                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          426                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          426                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          998                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29424                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30422                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          998                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29424                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30422                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2118154500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2118154500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75720000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     75720000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     32849000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     32849000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     75720000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   2151003500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2226723500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     75720000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   2151003500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2226723500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2066601                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2066601                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82069                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82069                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1014                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         1014                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1994340                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1994340                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1014                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076409                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077423                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1014                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2076409                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077423                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.353337                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.353337                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.984221                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.984221                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000214                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000214                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.984221                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014171                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014644                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984221                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014171                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014644                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -890,116 +896,118 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks          184                       # number of writebacks
 system.cpu.l2cache.writebacks::total              184                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            7                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            7                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28996                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        28996                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1013                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1013                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          437                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          437                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1013                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29433                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1013                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29433                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1827412000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1827412000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     66264500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     66264500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     28980500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     28980500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66264500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856392500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1922657000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66264500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856392500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1922657000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            6                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            6                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28998                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        28998                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          998                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          998                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          426                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          426                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          998                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29424                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30422                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          998                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29424                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30422                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1828174500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1828174500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65740000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65740000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     28589000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     28589000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65740000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856763500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1922503500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65740000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856763500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1922503500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353213                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353213                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.981589                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.981589                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000219                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000219                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.981589                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014174                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014655                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.981589                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014174                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014655                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63022.899710                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63022.899710                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65414.116486                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65414.116486                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66316.933638                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66316.933638                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65414.116486                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63071.807155                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63149.740524                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65414.116486                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63071.807155                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63149.740524                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353337                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353337                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.984221                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000214                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000214                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014171                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014644                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014171                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014644                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       1995466                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066895                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6085                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82092                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82092                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1032                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1994436                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2128                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6225475                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6227603                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        66048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265167168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265233216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         495                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4150549                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.000119                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.010920                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1995354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2066785                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         6027                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        82069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        82069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1014                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1994340                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2081                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6225092                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6227173                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        64896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265152640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          265217536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         487                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4150277                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.000117                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010832                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            4150054     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                495      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            4149790     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                487      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4150549                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4141738000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4150277                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4141496000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1548000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1521000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3114789000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          5.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               1448                       # Transaction distribution
+system.cpu.toL2Bus.respLayer1.occupancy    3114614000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          5.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp               1424                       # Transaction distribution
 system.membus.trans_dist::Writeback               184                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               34                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28996                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            28996                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          1450                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61108                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61108                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61108                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1960192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1960192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1960192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::CleanEvict               30                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1424                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1958784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1958784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1958784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             30664                       # Request fanout histogram
+system.membus.snoop_fanout::samples             30636                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30664    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30636    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30664                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            42854000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               30636                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            42746500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          160427250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          160323750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index fecf9a5e9..f0cb43f99 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -134,7 +134,7 @@ system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -200,7 +200,7 @@ system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 42e3e20b3..dc48bfe97 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,13 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 20:18:36
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
+gem5 compiled Sep 14 2015 22:13:36
+gem5 started Sep 14 2015 23:02:52
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 365989065000 because target called exit()
+Exiting @ tick 365988859500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
index 9aa92cf18..9e17532ff 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
index 354ea5068..f0a9a7c93 100644..100755
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
@@ -1,10 +1,6 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
 warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
index 6e5c2e80e..f3df2a37b 100644..100755
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
@@ -3,10 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  7 2014 10:41:53
-gem5 started May  7 2014 16:13:15
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:15:04
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -68,4 +69,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 409513954500 because target called exit()
+Exiting @ tick 412080064500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index 721b096f0..0819be4e4 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.412968                       # Number of seconds simulated
-sim_ticks                                412968287500                       # Number of ticks simulated
-final_tick                               412968287500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.412080                       # Number of seconds simulated
+sim_ticks                                412080064500                       # Number of ticks simulated
+final_tick                               412080064500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 309752                       # Simulator instruction rate (inst/s)
-host_op_rate                                   309752                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              209049423                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299216                       # Number of bytes of host memory used
-host_seconds                                  1975.46                       # Real time elapsed on the host
+host_inst_rate                                 229857                       # Simulator instruction rate (inst/s)
+host_op_rate                                   229857                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              154795079                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293864                       # Number of bytes of host memory used
+host_seconds                                  2662.10                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            171008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24125568                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24296576                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       171008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          171008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            170880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24123968                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24294848                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       170880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          170880                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks     18781376                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          18781376                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2672                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             376962                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                379634                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2670                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             376937                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                379607                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          293459                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               293459                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               414095                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58419905                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                58833999                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          414095                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             414095                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45478979                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45478979                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45478979                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              414095                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58419905                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104312978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        379634                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               414677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58541944                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                58956621                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          414677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             414677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45577007                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45577007                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45577007                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              414677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58541944                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104533628                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        379607                       # Number of read requests accepted
 system.physmem.writeReqs                       293459                       # Number of write requests accepted
-system.physmem.readBursts                      379634                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      379607                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                     293459                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24275200                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21376                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                 24271744                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     23104                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                  18779968                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24296576                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                  24294848                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys               18781376                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      334                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      361                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23720                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23189                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               23443                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24493                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25427                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23582                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23638                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23957                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23144                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23961                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24713                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22767                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23721                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24378                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22727                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23711                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23184                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               23442                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24496                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25435                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23571                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23637                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23952                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23149                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23951                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24706                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22760                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23713                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24379                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22720                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              22440                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               17784                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               17460                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17942                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18842                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               19508                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18590                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18730                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18662                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18408                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18932                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19251                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18034                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               17781                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               17456                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17945                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18847                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               19513                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18587                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18727                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18653                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18413                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18933                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19255                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18037                       # Per bank write bursts
 system.physmem.perBankWrBursts::12              18264                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18730                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17177                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17123                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18729                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17175                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17122                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    412968199500                       # Total gap between requests
+system.physmem.totGap                    412079976500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  379634                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  379607                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 293459                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    377911                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1373                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    377839                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    17007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17487                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    17014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17467                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17498                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
@@ -193,125 +193,129 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       142181                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.814019                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.682339                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.904056                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50781     35.72%     35.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38739     27.25%     62.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13305      9.36%     72.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8117      5.71%     78.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5703      4.01%     82.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3753      2.64%     84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3029      2.13%     86.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2502      1.76%     88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16252     11.43%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         142181                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17324                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.893847                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      236.830288                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17315     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            4      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       142258                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.629870                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.695929                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.359961                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50814     35.72%     35.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38804     27.28%     63.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13098      9.21%     72.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8314      5.84%     78.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5760      4.05%     82.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3818      2.68%     84.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2956      2.08%     86.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2613      1.84%     88.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16081     11.30%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         142258                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17331                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.881888                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      237.076982                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17323     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            3      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17324                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17324                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.938178                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.866265                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.087562                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           17274     99.71%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              36      0.21%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39               4      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47               3      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               2      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::328-335             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17324                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4037980750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11149855750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1896500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10645.88                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17331                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17331                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.931337                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.860812                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.636907                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17131     98.85%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             149      0.86%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              30      0.17%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               5      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               5      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17331                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4068932250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11179794750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1896230000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10729.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29395.88                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          58.78                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.48                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       58.83                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.48                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29479.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          58.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       58.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.81                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314187                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    216366                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        20.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314133                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    216290                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                       613538.10                       # Average gap between requests
-system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  547268400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  298608750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1493302200                       # Energy for read commands per rank (pJ)
+system.physmem.writeRowHitRate                  73.70                       # Row buffer hit rate for writes
+system.physmem.avgGap                       612243.04                       # Average gap between requests
+system.physmem.pageHitRate                      78.85                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  548364600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  299206875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1493138400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                955858320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26973005280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62129952405                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           193280474250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             285678469605                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.770048                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   320991140250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13789880000                       # Time in different power states
+system.physmem_0.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            62103866355                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           192770777250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             285086241240                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.822973                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   320142846250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13760240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     78186381000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     78176682500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  527582160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  287867250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1465152000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                945535680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26973005280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59078125665                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           195957550500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             285234818535                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              690.695650                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   325462585000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13789880000                       # Time in different power states
+system.physmem_1.actEnergy                  527105880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  287607375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1464957000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                945613440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            59197387905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           195320319750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             284658020790                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              690.783804                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   324404039000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13760240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     73715009750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     73915489750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               124207922                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87898525                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6402854                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71417252                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67405039                       # Number of BTB hits
+system.cpu.branchPred.lookups               123917174                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87658941                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6214604                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71577859                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67272092                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.382012                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15056477                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1126637                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.984499                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15041850                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1126019                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149440392                       # DTB read hits
-system.cpu.dtb.read_misses                     563754                       # DTB read misses
+system.cpu.dtb.read_hits                    149344667                       # DTB read hits
+system.cpu.dtb.read_misses                     549014                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                150004146                       # DTB read accesses
-system.cpu.dtb.write_hits                    57327101                       # DTB write hits
-system.cpu.dtb.write_misses                     66835                       # DTB write misses
+system.cpu.dtb.read_accesses                149893681                       # DTB read accesses
+system.cpu.dtb.write_hits                    57319597                       # DTB write hits
+system.cpu.dtb.write_misses                     63704                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57393936                       # DTB write accesses
-system.cpu.dtb.data_hits                    206767493                       # DTB hits
-system.cpu.dtb.data_misses                     630589                       # DTB misses
+system.cpu.dtb.write_accesses                57383301                       # DTB write accesses
+system.cpu.dtb.data_hits                    206664264                       # DTB hits
+system.cpu.dtb.data_misses                     612718                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207398082                       # DTB accesses
-system.cpu.itb.fetch_hits                   226564860                       # ITB hits
+system.cpu.dtb.data_accesses                207276982                       # DTB accesses
+system.cpu.itb.fetch_hits                   226051197                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               226564908                       # ITB accesses
+system.cpu.itb.fetch_accesses               226051245                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -325,82 +329,82 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        825936575                       # number of cpu cycles simulated
+system.cpu.numCycles                        824160129                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13262650                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12834592                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.349787                       # CPI: cycles per instruction
-system.cpu.ipc                               0.740858                       # IPC: instructions per cycle
-system.cpu.tickCycles                       740975160                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        84961415                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           2535462                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.659006                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202664910                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539558                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.803222                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1636438500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.659006                       # Average occupied blocks per requestor
+system.cpu.cpi                               1.346883                       # CPI: cycles per instruction
+system.cpu.ipc                               0.742455                       # IPC: instructions per cycle
+system.cpu.tickCycles                       739333640                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        84826489                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           2535265                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.660702                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202570424                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539361                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.772204                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1635033500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.660702                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          830                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3144                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414773666                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414773666                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146998717                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146998717                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     55666193                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666193                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     202664910                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202664910                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    202664910                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202664910                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1908303                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908303                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1543841                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543841                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3452144                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3452144                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3452144                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3452144                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37694000500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37694000500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  47697864000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  47697864000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  85391864500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  85391864500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  85391864500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  85391864500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    148907020                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148907020                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         414584973                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414584973                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146904267                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146904267                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     55666157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666157                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     202570424                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202570424                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    202570424                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202570424                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1908505                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908505                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1543877                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543877                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3452382                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3452382                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3452382                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3452382                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37715152000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37715152000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  47725761500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  47725761500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  85440913500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  85440913500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  85440913500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  85440913500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    148812772                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148812772                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    206117054                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206117054                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    206117054                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206117054                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012815                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012815                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026985                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.026985                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016748                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016748                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.016748                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.016748                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19752.628644                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19752.628644                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30895.580568                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30895.580568                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.892970                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24735.892970                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.892970                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24735.892970                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    206022806                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206022806                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    206022806                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206022806                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012825                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026986                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.026986                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016757                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016757                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016757                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.016757                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19761.620745                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19761.620745                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30912.929916                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30912.929916                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24748.395021                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24748.395021                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24748.395021                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24748.395021                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -409,103 +413,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2339794                       # number of writebacks
-system.cpu.dcache.writebacks::total           2339794                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143529                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143529                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769057                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769057                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       912586                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       912586                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       912586                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       912586                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764774                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764774                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774784                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       774784                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2539558                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539558                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2539558                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539558                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33188844000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33188844000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23330038500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23330038500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56518882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  56518882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56518882500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  56518882500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011852                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011852                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks      2339622                       # number of writebacks
+system.cpu.dcache.writebacks::total           2339622                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143967                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143967                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769054                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769054                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       913021                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       913021                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       913021                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       913021                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764538                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764538                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774823                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       774823                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2539361                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539361                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2539361                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539361                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33198964500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33198964500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23344010000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23344010000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56542974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  56542974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56542974500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  56542974500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011857                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.013543                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012321                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012321                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012321                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012321                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18806.285677                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18806.285677                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30111.667897                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30111.667897                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22255.401334                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22255.401334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22255.401334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22255.401334                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012326                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012326                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012326                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012326                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18814.536440                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18814.536440                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.184114                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.184114                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22266.615302                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22266.615302                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22266.615302                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22266.615302                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3160                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1117.196292                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           226559871                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4989                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45411.880337                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3153                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1116.819230                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           226046216                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4981                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45381.693636                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1117.196292                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545506                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545506                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           76                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1589                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         453134709                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        453134709                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    226559871                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       226559871                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     226559871                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        226559871                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    226559871                       # number of overall hits
-system.cpu.icache.overall_hits::total       226559871                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4989                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4989                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4989                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4989                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4989                       # number of overall misses
-system.cpu.icache.overall_misses::total          4989                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    243357500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    243357500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    243357500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    243357500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    243357500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    243357500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    226564860                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    226564860                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    226564860                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    226564860                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    226564860                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    226564860                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst  1116.819230                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545322                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545322                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1828                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         452107375                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        452107375                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    226046216                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       226046216                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     226046216                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        226046216                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    226046216                       # number of overall hits
+system.cpu.icache.overall_hits::total       226046216                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4981                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4981                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4981                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4981                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4981                       # number of overall misses
+system.cpu.icache.overall_misses::total          4981                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    245472000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    245472000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    245472000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    245472000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    245472000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    245472000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    226051197                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    226051197                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    226051197                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    226051197                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    226051197                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    226051197                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48778.813389                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48778.813389                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48778.813389                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48778.813389                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48778.813389                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48778.813389                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49281.670347                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49281.670347                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49281.670347                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49281.670347                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49281.670347                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49281.670347                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -514,129 +518,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4989                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4989                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4989                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4989                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4989                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4989                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    238368500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    238368500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    238368500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    238368500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    238368500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    238368500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4981                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4981                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4981                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4981                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4981                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4981                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    240491000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    240491000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    240491000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    240491000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    240491000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    240491000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47778.813389                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47778.813389                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47778.813389                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47778.813389                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47778.813389                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47778.813389                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48281.670347                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48281.670347                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48281.670347                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48281.670347                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48281.670347                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48281.670347                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           346924                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29501.974540                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3909137                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           379348                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.304884                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189597329500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21308.033203                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   178.119717                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8015.821620                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.650270                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005436                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.244623                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.900329                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32424                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13174                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18827                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989502                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41822837                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41822837                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2339794                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2339794                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       571874                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571874                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2317                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         2317                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590722                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1590722                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2317                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2162596                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164913                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2317                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2162596                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164913                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206263                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206263                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2672                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2672                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       170699                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       170699                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2672                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       376962                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        379634                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2672                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       376962                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       379634                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16205579000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16205579000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    206542500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    206542500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  13758959500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  13758959500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    206542500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  29964538500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30171081000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    206542500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  29964538500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30171081000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2339794                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2339794                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       778137                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       778137                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4989                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4989                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761421                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1761421                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4989                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2539558                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2544547                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4989                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2539558                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544547                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265073                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.265073                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.535578                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.535578                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.096910                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.096910                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.535578                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.148436                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.149195                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.535578                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.148436                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.149195                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78567.552106                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78567.552106                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77298.839820                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77298.839820                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80603.632710                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80603.632710                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77298.839820                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79489.546692                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79474.127712                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77298.839820                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79489.546692                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79474.127712                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           346897                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29502.927026                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3908665                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           379320                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.304400                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     189124044500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21307.222747                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   177.805871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8017.898409                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.650245                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005426                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.244687                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.900358                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32423                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           78                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13170                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18832                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989471                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         41819560                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41819560                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2339622                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2339622                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       571899                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       571899                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2311                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         2311                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590525                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1590525                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2311                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2162424                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164735                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2311                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2162424                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2164735                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206261                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206261                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2670                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2670                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       170676                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       170676                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2670                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       376937                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        379607                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2670                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       376937                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       379607                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16219478500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16219478500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    208738500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    208738500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  13771177000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  13771177000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    208738500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  29990655500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30199394000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    208738500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  29990655500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30199394000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2339622                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2339622                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       778160                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       778160                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4981                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4981                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761201                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1761201                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4981                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2539361                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2544342                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4981                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2539361                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544342                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265062                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.265062                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.536037                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.536037                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.096909                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.096909                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.536037                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.148438                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.149197                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.536037                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.148438                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.149197                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78635.701853                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78635.701853                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78179.213483                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78179.213483                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80686.077714                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80686.077714                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78179.213483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79564.106203                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79554.365436                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78179.213483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79564.106203                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79554.365436                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -647,114 +651,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       293459                       # number of writebacks
 system.cpu.l2cache.writebacks::total           293459                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          739                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          739                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206263                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206263                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2672                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2672                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       170699                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       170699                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2672                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       376962                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       379634                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2672                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       376962                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       379634                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14142949000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14142949000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    179822500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    179822500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12051969500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12051969500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    179822500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26194918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26374741000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    179822500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26194918500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26374741000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          738                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          738                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206261                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206261                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2670                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2670                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       170676                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       170676                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2670                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       376937                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       379607                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2670                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       376937                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       379607                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14156868500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14156868500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    182038500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    182038500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12064417000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12064417000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    182038500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26221285500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26403324000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    182038500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26221285500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26403324000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265073                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265073                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.535578                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.535578                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.096910                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.096910                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.535578                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148436                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.149195                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.535578                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148436                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.149195                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68567.552106                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68567.552106                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67298.839820                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67298.839820                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70603.632710                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70603.632710                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67298.839820                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69489.546692                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.127712                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67298.839820                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69489.546692                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69474.127712                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265062                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265062                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.536037                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.536037                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.096909                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.096909                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.536037                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148438                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149197                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.536037                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148438                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149197                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68635.701853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68635.701853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68179.213483                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68179.213483                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70686.077714                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70686.077714                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68179.213483                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69564.106203                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69554.365436                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       1766410                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2633253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       252293                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       778137                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       778137                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4989                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761421                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13138                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7614578                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7627716                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       319296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312278528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312597824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      346924                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5430093                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1766182                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2633081                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       252234                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       778160                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       778160                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4981                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761201                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13115                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7613987                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7627102                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       318784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312254912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312573696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      346897                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5429657                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        1.063889                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.244555                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.244556                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5083169     93.61%     93.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             346924      6.39%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5082760     93.61%     93.61% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             346897      6.39%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5430093                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4881378500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5429657                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4881002000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7483500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7471500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3809337000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3809041500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             173371                       # Transaction distribution
+system.membus.trans_dist::ReadResp             173346                       # Transaction distribution
 system.membus.trans_dist::Writeback            293459                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            51814                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206263                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206263                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        173371                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104541                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1104541                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43077952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43077952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::CleanEvict            51785                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206261                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206261                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        173346                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104458                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1104458                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43076224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43076224                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            724907                       # Request fanout histogram
+system.membus.snoop_fanout::samples            724851                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  724907    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  724851    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              724907                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2020096000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              724851                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2020156500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2009057000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2008875000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
index 482664dec..a401ada34 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -759,9 +759,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
index 83790a04a..984c172ad 100755
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 03:04:52
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x3275620
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: *************************************************
@@ -68,4 +70,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 366358475500 because target called exit()
+Exiting @ tick 363605295500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 9049068c3..0b95ee278 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.365934                       # Number of seconds simulated
-sim_ticks                                365934171500                       # Number of ticks simulated
-final_tick                               365934171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.363605                       # Number of seconds simulated
+sim_ticks                                363605295500                       # Number of ticks simulated
+final_tick                               363605295500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 236242                       # Simulator instruction rate (inst/s)
-host_op_rate                                   255881                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              170651382                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317968                       # Number of bytes of host memory used
-host_seconds                                  2144.34                       # Real time elapsed on the host
+host_inst_rate                                 163495                       # Simulator instruction rate (inst/s)
+host_op_rate                                   177087                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              117350463                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312624                       # Number of bytes of host memory used
+host_seconds                                  3098.46                       # Real time elapsed on the host
 sim_insts                                   506582156                       # Number of instructions simulated
 sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            218560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8996480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9215040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       218560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          218560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6186432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6186432                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3415                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140570                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                143985                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96663                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96663                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               597266                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24584968                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25182234                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          597266                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             597266                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          16905860                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               16905860                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          16905860                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              597266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24584968                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42088095                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        143985                       # Number of read requests accepted
-system.physmem.writeReqs                        96663                       # Number of write requests accepted
-system.physmem.readBursts                      143985                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      96663                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9208192                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6848                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6184704                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9215040                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6186432                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      107                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            219264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9004480                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9223744                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6189056                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6189056                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3426                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140695                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                144121                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96704                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96704                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               603028                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24764436                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25367463                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          603028                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             603028                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          17021358                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               17021358                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          17021358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              603028                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24764436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42388822                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        144121                       # Number of read requests accepted
+system.physmem.writeReqs                        96704                       # Number of write requests accepted
+system.physmem.readBursts                      144121                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      96704                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9217792                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5952                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6187328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9223744                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6189056                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       93                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9335                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8992                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8932                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8655                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9327                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8969                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9002                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8675                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                9455                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8940                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8097                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8569                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8673                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8766                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9474                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9347                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9510                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8717                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9061                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6192                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6097                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6005                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5812                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6185                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6187                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6017                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5496                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5731                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9352                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8946                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8102                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8582                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8671                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8765                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9475                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9349                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9515                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8723                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9120                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6189                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6094                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6010                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5821                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6183                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6186                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6015                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5498                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5738                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                5829                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6464                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6463                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6313                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6284                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6001                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6058                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6285                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6005                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6083                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    365934145500                       # Total gap between requests
+system.physmem.totGap                    363605269500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  143985                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  144121                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  96663                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143524                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       334                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  96704                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143663                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       343                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5660                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2949                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
@@ -193,107 +193,122 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65249                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.897316                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.545884                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.443874                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24707     37.87%     37.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18339     28.11%     65.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7015     10.75%     76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7835     12.01%     88.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2110      3.23%     91.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1145      1.75%     93.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          725      1.11%     94.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          601      0.92%     95.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2772      4.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65249                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5581                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.778176                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      381.924168                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5576     99.91%     99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            4      0.07%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65251                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      236.074482                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     156.620272                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.651300                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24697     37.85%     37.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18374     28.16%     66.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6917     10.60%     76.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7938     12.17%     88.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2038      3.12%     91.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1147      1.76%     93.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          769      1.18%     94.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          621      0.95%     95.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2750      4.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65251                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5585                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.786571                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      381.841879                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5581     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5581                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5581                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.315176                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.217549                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.442698                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2634     47.20%     47.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2799     50.15%     97.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              58      1.04%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              24      0.43%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              19      0.34%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              10      0.18%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               9      0.16%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               9      0.16%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               3      0.05%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               4      0.07%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               3      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               4      0.07%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::74-75               2      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-93               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5581                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1559327000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4257039500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    719390000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10837.84                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5585                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5585                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.310116                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.217866                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.213646                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2534     45.37%     45.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 92      1.65%     47.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               2660     47.63%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                156      2.79%     97.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 36      0.64%     98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 18      0.32%     98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 16      0.29%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  9      0.16%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  7      0.13%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 10      0.18%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  4      0.07%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  4      0.07%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  4      0.07%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  6      0.11%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.04%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  4      0.07%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  3      0.05%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  4      0.07%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  2      0.04%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  2      0.04%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.02%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  2      0.04%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::61                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5585                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1541292750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4241817750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    720140000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10701.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29587.84                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.16                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          16.90                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.18                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       16.91                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29451.34                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.35                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          17.02                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       17.02                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110804                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64456                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.01                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.68                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1520619.93                       # Average gap between requests
-system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  248300640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135481500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 559572000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                310819680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23900794320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47511748935                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           177881418000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             250548135075                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.687479                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   295615195000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12219220000                       # Time in different power states
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        19.51                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110876                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64571                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.77                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1509831.91                       # Average gap between requests
+system.physmem.pageHitRate                      72.88                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  248028480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135333000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 560164800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                310884480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47382783300                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           176597692500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             248983621440                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              684.768610                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   293478926000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12141480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     58096250000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     57982170250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  244785240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133563375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 562356600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                315174240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23900794320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            46698412230                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           178594871250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             250449957255                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.419183                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   296806540250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12219220000                       # Time in different power states
+system.physmem_1.actEnergy                  245080080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  133724250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 563004000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                315375120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            46983341835                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           176948079750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             248937339915                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              684.641324                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   294063578500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12141480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     56906569250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     57397836750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               132492243                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98438822                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6555205                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68897926                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64816869                       # Number of BTB hits
+system.cpu.branchPred.lookups               131896308                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98031712                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6139352                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             68410049                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                64397752                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.076662                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                10008233                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              17907                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.134930                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9981293                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              18014                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -412,98 +427,98 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        731868343                       # number of cpu cycles simulated
+system.cpu.numCycles                        727210591                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506582156                       # Number of instructions committed
 system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13915585                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      13199856                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.444718                       # CPI: cycles per instruction
-system.cpu.ipc                               0.692177                       # IPC: instructions per cycle
-system.cpu.tickCycles                       695013398                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        36854945                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1139741                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.950270                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171285752                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1143837                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.746644                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        4896340500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.950270                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993884                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993884                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.435524                       # CPI: cycles per instruction
+system.cpu.ipc                               0.696610                       # IPC: instructions per cycle
+system.cpu.tickCycles                       690727435                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        36483156                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1139971                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.789837                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           171168979                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1144067                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.614471                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.789837                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993845                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          549                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3503                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346825855                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346825855                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114767186                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114767186                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53538711                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53538711                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2773                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2773                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         346593001                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346593001                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114650515                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114650515                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53538628                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53538628                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2754                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2754                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168305897                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168305897                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168308670                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168308670                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       854648                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        854648                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       700595                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       700595                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           14                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           14                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1555243                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1555243                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1555257                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1555257                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14022869000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14022869000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21909880500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21909880500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35932749500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35932749500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35932749500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35932749500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115621834                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115621834                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     168189143                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168189143                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168191897                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168191897                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       854793                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        854793                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       700678                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       700678                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           17                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           17                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1555471                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1555471                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1555488                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1555488                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14024452000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14024452000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21892214000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21892214000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35916666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35916666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35916666000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35916666000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115505308                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115505308                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2787                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2787                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2771                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2771                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169861140                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169861140                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169863927                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169863927                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007392                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007392                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012917                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012917                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005023                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005023                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009156                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009156                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009156                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009156                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23104.266986                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23104.059008                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    169744614                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169744614                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169747385                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169747385                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007400                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007400                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.006135                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.006135                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009164                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009164                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009164                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009164                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23090.540422                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23090.288064                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -512,111 +527,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1068492                       # number of writebacks
-system.cpu.dcache.writebacks::total           1068492                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66944                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        66944                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344474                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344474                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      1068574                       # number of writebacks
+system.cpu.dcache.writebacks::total           1068574                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66907                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        66907                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344511                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344511                       # number of WriteReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data       411418                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total       411418                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data       411418                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total       411418                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787704                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       787704                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356121                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356121                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1143825                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1143825                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1143837                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1143837                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12336256500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12336256500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11129164500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11129164500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1374500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1374500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23465421000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23465421000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23466795500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23466795500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006813                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006813                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006566                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004306                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004306                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006734                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006734                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006734                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006734                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31251.076179                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 114541.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20514.869845                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20514.869845                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20515.856280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787886                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       787886                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356167                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356167                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           14                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           14                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1144053                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1144053                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1144067                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1144067                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12337562000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12337562000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11120015500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11120015500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1028000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1028000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23457577500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23457577500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23458605500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23458605500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006821                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006821                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006567                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006567                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005052                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005052                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006740                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006740                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006740                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006740                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             17695                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1189.845505                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           200793682                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19567                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10261.853222                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             17719                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1188.326281                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           199317838                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             19591                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          10173.949160                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1189.845505                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.580979                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.580979                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1188.326281                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.580237                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.580237                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          298                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1411                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          303                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1407                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         401646065                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        401646065                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    200793682                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       200793682                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     200793682                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        200793682                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    200793682                       # number of overall hits
-system.cpu.icache.overall_hits::total       200793682                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19567                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19567                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19567                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19567                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19567                       # number of overall misses
-system.cpu.icache.overall_misses::total         19567                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    488802000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    488802000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    488802000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    488802000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    488802000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    488802000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    200813249                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    200813249                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    200813249                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    200813249                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    200813249                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    200813249                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000097                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000097                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000097                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000097                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000097                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000097                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24980.937292                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24980.937292                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24980.937292                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24980.937292                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24980.937292                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24980.937292                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         398694449                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        398694449                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    199317838                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       199317838                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     199317838                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        199317838                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    199317838                       # number of overall hits
+system.cpu.icache.overall_hits::total       199317838                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19591                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19591                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19591                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19591                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19591                       # number of overall misses
+system.cpu.icache.overall_misses::total         19591                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    490899000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    490899000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    490899000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    490899000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    490899000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    490899000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    199337429                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    199337429                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    199337429                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    199337429                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    199337429                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    199337429                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000098                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000098                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000098                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000098                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000098                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25057.373284                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25057.373284                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25057.373284                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25057.373284                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25057.373284                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25057.373284                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -625,128 +640,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19567                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        19567                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        19567                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        19567                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        19567                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        19567                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    469235000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    469235000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    469235000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    469235000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    469235000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    469235000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000097                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000097                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000097                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000097                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23980.937292                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23980.937292                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23980.937292                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23980.937292                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23980.937292                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23980.937292                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19591                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        19591                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        19591                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        19591                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        19591                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        19591                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    471308000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    471308000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    471308000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    471308000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    471308000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    471308000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.373284                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24057.373284                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24057.373284                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24057.373284                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24057.373284                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24057.373284                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111231                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27646.288282                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1766920                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           142419                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.406491                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     163672087500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23475.151417                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   389.993821                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3781.143044                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.716405                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011902                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.115391                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.843698                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           111367                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27634.082837                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1767150                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           142553                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.396442                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     163253470000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23457.963317                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   389.755870                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3786.363650                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.715880                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011894                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.115551                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.843325                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31186                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4931                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25867                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951782                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         19026681                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        19026681                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      1068492                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1068492                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       255561                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255561                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16150                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        16150                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       747691                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       747691                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        16150                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1003252                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1019402                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        16150                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1003252                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1019402                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       100813                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       100813                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3417                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3417                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39772                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        39772                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3417                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       140585                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        144002                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3417                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       140585                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       144002                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7914075500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7914075500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    270270000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    270270000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3286332500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3286332500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    270270000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11200408000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11470678000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    270270000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11200408000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11470678000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      1068492                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1068492                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       356374                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       356374                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19567                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        19567                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       787463                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       787463                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        19567                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1143837                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1163404                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        19567                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1143837                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1163404                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282885                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.282885                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.174631                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.174631                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050506                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050506                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.174631                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.122906                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123776                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.174631                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.122906                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123776                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78502.529436                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78502.529436                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79095.697981                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79095.697981                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82629.299507                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82629.299507                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79095.697981                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79670.007469                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79656.379773                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79095.697981                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79670.007469                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79656.379773                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4935                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25860                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951721                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19030386                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19030386                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1068574                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1068574                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       255588                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       255588                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16163                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        16163                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       747770                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       747770                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        16163                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1003358                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1019521                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        16163                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1003358                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1019521                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       100829                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       100829                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3428                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3428                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39880                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        39880                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3428                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       140709                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        144137                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3428                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       140709                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       144137                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7904552500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7904552500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    272166000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    272166000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3286207500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3286207500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    272166000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11190760000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11462926000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    272166000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11190760000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11462926000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      1068574                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1068574                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       356417                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       356417                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19591                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        19591                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       787650                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       787650                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        19591                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1144067                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1163658                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        19591                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1144067                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1163658                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282896                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.282896                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.174978                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.174978                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050632                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050632                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.174978                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.122990                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123865                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.174978                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.122990                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123865                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78395.625267                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78395.625267                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79394.982497                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79394.982497                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82402.394684                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82402.394684                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79394.982497                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.231122                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79527.990731                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79394.982497                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.231122                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79527.990731                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -755,126 +770,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        96663                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96663                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        96704                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96704                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           15                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           14                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           17                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1183                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1183                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100813                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100813                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3415                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3415                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39757                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39757                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3415                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       140570                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       143985                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3415                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       140570                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       143985                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6905945500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6905945500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    235984000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    235984000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2887628500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2887628500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    235984000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9793574000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10029558000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    235984000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9793574000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10029558000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1193                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1193                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100829                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100829                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3426                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3426                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39866                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39866                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3426                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       140695                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       144121                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3426                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       140695                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       144121                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6896262500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6896262500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    237598000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    237598000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2886048500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2886048500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    237598000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9782311000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10019909000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    237598000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9782311000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10019909000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282885                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282885                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.174529                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050487                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050487                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122893                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123762                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174529                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122893                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123762                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68502.529436                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68502.529436                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69102.196193                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72631.951606                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72631.951606                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69670.441773                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69656.964267                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69102.196193                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69670.441773                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69656.964267                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282896                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282896                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.174876                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.174876                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050614                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050614                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174876                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122978                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123852                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174876                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122978                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123852                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        807030                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1165155                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        98658                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356374                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356374                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        19567                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       787463                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56593                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3422797                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3479390                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141589056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          142841344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      111231                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2432071                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.045735                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.208910                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        807241                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1165278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        98858                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356417                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356417                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        19591                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       787650                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56664                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3423421                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3480085                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1253824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141609024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          142862848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      111367                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2432715                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.045779                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.209005                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            2320840     95.43%     95.43% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             111231      4.57%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            2321348     95.42%     95.42% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             111367      4.58%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2432071                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2228912000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2432715                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2229248000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      29351498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      29387997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1715762985                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1716107486                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              43172                       # Transaction distribution
-system.membus.trans_dist::Writeback             96663                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            13165                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100813                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100813                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         43172                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397798                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 397798                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15401472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15401472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              43292                       # Transaction distribution
+system.membus.trans_dist::Writeback             96704                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            13244                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100829                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100829                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         43292                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       398190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 398190                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15412800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15412800                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            253813                       # Request fanout histogram
+system.membus.snoop_fanout::samples            254069                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  253813    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  254069    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              253813                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           683218000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              254069                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           683631500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          764295250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          765040250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 8909daba1..2ccb6f3ec 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -688,9 +688,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index 0b92236c6..bc3661e7a 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -156,7 +156,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -266,7 +266,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 0db544c43..0416dfaa7 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -156,7 +156,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -513,7 +513,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -579,7 +579,7 @@ system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -642,9 +642,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 67a40aa52..bfd9de2ec 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -3,17 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  5 2015 17:24:59
-gem5 started Jul  5 2015 17:25:16
+gem5 compiled Sep 14 2015 22:13:36
+gem5 started Sep 14 2015 22:14:29
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
- Reading the dictionary files: *********info: Increasing stack size by one page.
+ Reading the dictionary files: **info: Increasing stack size by one page.
+*******info: Increasing stack size by one page.
+******************************info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-**********************************info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
@@ -24,8 +25,7 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-******
+**********
  58924 words stored in 3784810 bytes
 
 
@@ -37,6 +37,10 @@ Processing sentences in batch mode
 
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+* how fast the program is it 
+* I am wondering whether to invite to the party 
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
@@ -45,10 +49,6 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-* do you know where John 's 
-* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
-* how fast the program is it 
-* I am wondering whether to invite to the party 
 * I gave him for his birthday it 
 * I thought terrible after our discussion 
 * I wonder how much money have you earned 
@@ -91,4 +91,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 417250627500 because target called exit()
+Exiting @ tick 403706643500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 0dda4ffb8..c2ca7f71b 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.417316                       # Number of seconds simulated
-sim_ticks                                417315805000                       # Number of ticks simulated
-final_tick                               417315805000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.403707                       # Number of seconds simulated
+sim_ticks                                403706643500                       # Number of ticks simulated
+final_tick                               403706643500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  92447                       # Simulator instruction rate (inst/s)
-host_op_rate                                   170945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               46657066                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 432180                       # Number of bytes of host memory used
-host_seconds                                  8944.32                       # Real time elapsed on the host
+host_inst_rate                                  76271                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141034                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               37237827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 423672                       # Number of bytes of host memory used
+host_seconds                                 10841.31                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            223744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24530944                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24754688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       223744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          223744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18881856                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18881856                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3496                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             383296                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                386792                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          295029                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               295029                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               536150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58782686                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                59318836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          536150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             536150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45245964                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45245964                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45245964                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              536150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58782686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104564801                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        386792                       # Number of read requests accepted
-system.physmem.writeReqs                       295029                       # Number of write requests accepted
-system.physmem.readBursts                      386792                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     295029                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24733440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18880128                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24754688                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18881856                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            216320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24497408                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24713728                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       216320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          216320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18869312                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18869312                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3380                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             382772                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386152                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          294833                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               294833                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               535835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             60681211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                61217046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          535835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             535835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          46740157                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               46740157                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          46740157                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              535835                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            60681211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              107957203                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386152                       # Number of read requests accepted
+system.physmem.writeReqs                       294833                       # Number of write requests accepted
+system.physmem.readBursts                      386152                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     294833                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24695616                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18112                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18867776                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24713728                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18869312                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      283                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         179000                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24059                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26401                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24741                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24611                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23500                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23770                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24546                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24382                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23722                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23975                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24786                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24066                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23221                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22949                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23843                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23888                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18612                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19924                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18985                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               19009                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18161                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18506                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               19135                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               19090                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18676                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18214                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18884                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17768                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17389                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16996                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17798                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17855                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         195189                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24028                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26400                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24980                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24600                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23395                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23728                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24595                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24357                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23707                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23543                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24760                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              23969                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23156                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22899                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23872                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23880                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18605                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19929                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               19196                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18982                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18144                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18488                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19136                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19077                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18672                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17940                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18886                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17736                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17372                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16987                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17811                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17848                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    417315698500                       # Total gap between requests
+system.physmem.totGap                    403706602500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  386792                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386152                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 295029                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    381444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 294833                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    380965                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4554                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       304                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6530                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17613                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17556                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
@@ -193,347 +193,345 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147495                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      295.684816                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.392327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.222401                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54844     37.18%     37.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        40100     27.19%     64.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13710      9.30%     73.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7409      5.02%     78.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5412      3.67%     82.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3888      2.64%     84.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3038      2.06%     87.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2781      1.89%     88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16313     11.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147495                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17511                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.068928                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      218.794243                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17500     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            6      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       146765                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.814963                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     175.408246                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     322.979648                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54126     36.88%     36.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        39824     27.13%     64.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13787      9.39%     73.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7512      5.12%     78.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5608      3.82%     82.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3872      2.64%     84.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3087      2.10%     87.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2794      1.90%     88.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16155     11.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         146765                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17509                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.037923                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      218.270562                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17499     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            3      0.02%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17511                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17511                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.846668                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.775279                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.561224                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17315     98.88%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             151      0.86%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              21      0.12%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               5      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               3      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               2      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17511                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4302860250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11548985250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1932300000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11134.04                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17509                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17509                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.837569                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.769084                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.527211                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17319     98.91%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             139      0.79%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              19      0.11%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              11      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               2      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               2      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               5      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17509                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4289653250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11524697000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1929345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11116.86                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29884.04                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          59.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.24                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       59.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.25                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29866.86                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          61.17                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          46.74                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       61.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       46.74                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.35                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     318003                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215951                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.29                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                       612060.49                       # Average gap between requests
-system.physmem.pageHitRate                      78.35                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  569562840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  310773375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1528737600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                980981280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            27256781760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63486572355                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           194697293250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             288830702460                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.121537                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   323337240250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13934960000                       # Time in different power states
+system.physmem.busUtil                           0.84                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.48                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.37                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        20.93                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     317973                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215927                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.40                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.24                       # Row buffer hit rate for writes
+system.physmem.avgGap                       592827.45                       # Average gap between requests
+system.physmem.pageHitRate                      78.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  569094120                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  310517625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1529307000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                981933840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26367818880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            62417540205                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           187468813500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             279645025170                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.702062                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   311319479750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13480480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     80039955000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     78902125750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  545136480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  297445500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1485127800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                930216960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            27256781760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61714779795                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           196251513750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             288481002045                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              691.283509                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   325936894250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13934960000                       # Time in different power states
+system.physmem_1.actEnergy                  540041040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  294665250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1479816000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                928013760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26367818880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            60324869565                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           189304489500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             279239713995                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              691.698075                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   314381404750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13480480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     77440301000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     75839865250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               230117471                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         230117471                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9743461                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            131565165                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               128785895                       # Number of BTB hits
+system.cpu.branchPred.lookups               219316547                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         219316547                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           8533340                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            124021938                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               121820147                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.887534                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                27740805                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1463511                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.224676                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                27066490                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1406992                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        834631611                       # number of cpu cycles simulated
+system.cpu.numCycles                        807413288                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          185091560                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1269611575                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   230117471                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          156526700                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     638324625                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                20217139                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        543                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                96744                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        810626                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles         1773                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          110                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 179459083                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2721482                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          834434550                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.830059                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.382636                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          175921222                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1208610344                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   219316547                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          148886637                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     621541997                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                17781141                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        241                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                95442                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        760366                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         1422                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           41                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 170776115                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2324492                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       3                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          807211301                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.786075                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.367353                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                426827210     51.15%     51.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 33688698      4.04%     55.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 32854559      3.94%     59.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 33384869      4.00%     63.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 27147041      3.25%     66.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 27739461      3.32%     69.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 37019184      4.44%     74.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 33642570      4.03%     78.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                182130958     21.83%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                417064653     51.67%     51.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32628603      4.04%     55.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31895320      3.95%     59.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 32734486      4.06%     63.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 26590994      3.29%     67.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 26897855      3.33%     70.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 35141039      4.35%     74.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 31437377      3.89%     78.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                172820974     21.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            834434550                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.275711                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.521164                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                127499737                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             374953474                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 240627559                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              81245211                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10108569                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2225588633                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               10108569                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                159647168                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               159927889                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          39744                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 285634401                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             219076779                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2175363345                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                166678                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              136608012                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               24443504                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               48002145                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2279615876                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5501425511                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3499355021                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             55759                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            807211301                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.271629                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.496892                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                120518152                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             370503139                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 225214950                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              82084490                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8890570                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2132165876                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                8890570                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                152539883                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               150620560                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          39985                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 271567858                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             223552445                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2088589695                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                134600                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              138169190                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               24839349                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               50537004                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2190785289                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5278493147                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3357262511                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             59407                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                665575022                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               3123                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2916                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 415832299                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            528432376                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           209864891                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         239237917                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         72205880                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2101284212                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               24336                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1827034633                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            401491                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       572319847                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    974276898                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          23784                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     834434550                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.189548                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.072515                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                576744435                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               3185                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2908                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 421985771                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            507135954                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           200817604                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         229019753                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         68232285                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2023164418                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22990                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1789038207                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            420221                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       494198707                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    833041498                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          22438                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     807211301                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.216320                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.070566                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           254639697     30.52%     30.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           125724347     15.07%     45.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           119353828     14.30%     59.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           111074898     13.31%     73.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            92504387     11.09%     84.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            61470741      7.37%     91.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            43061930      5.16%     96.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            19202673      2.30%     99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7402049      0.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           238530872     29.55%     29.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           123621910     15.31%     44.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           118898033     14.73%     59.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           107819129     13.36%     72.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            89545218     11.09%     84.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            60296093      7.47%     91.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            42279085      5.24%     96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            18940691      2.35%     99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             7280270      0.90%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       834434550                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       807211301                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11320186     42.67%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12172571     45.88%     88.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3037482     11.45%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11520759     42.69%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               12368193     45.83%     88.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3098262     11.48%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2711288      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1211298887     66.30%     66.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               388808      0.02%     66.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3881058      0.21%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 134      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 33      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                 403      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            435055867     23.81%     90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           173698155      9.51%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2718353      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1183132640     66.13%     66.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               368609      0.02%     66.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3881115      0.22%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 137      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 64      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                 344      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            428541213     23.95%     90.48% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170395732      9.52%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1827034633                       # Type of FU issued
-system.cpu.iq.rate                           2.189031                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    26530239                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014521                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4515402541                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2673889112                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1796964967                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               33005                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              70700                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         7229                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1850838268                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   15316                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        185431148                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1789038207                       # Type of FU issued
+system.cpu.iq.rate                           2.215765                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    26987214                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015085                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4412665624                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2517635859                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1762385104                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               29526                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              68682                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         5548                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1813294148                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12920                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        186084957                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    144332039                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       211913                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       385225                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     60704705                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    123036250                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       211434                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       371907                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     51657418                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19195                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1040                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        23176                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1099                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10108569                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               107095351                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6179627                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2101308548                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            404076                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             528434196                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            209864891                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6959                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1875437                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3414890                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         385225                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5746544                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4564008                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10310552                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1805625643                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             428837620                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          21408990                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                8890570                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                97719419                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6134161                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2023187408                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            375929                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             507138407                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            200817604                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               7250                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1817237                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3413935                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         371907                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4848104                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4143061                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8991165                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1770021029                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             423153321                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19017178                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    599025712                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                171773578                       # Number of branches executed
-system.cpu.iew.exec_stores                  170188092                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.163380                       # Inst execution rate
-system.cpu.iew.wb_sent                     1802216227                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1796972196                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1368071729                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2090120765                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    590346194                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                168990321                       # Number of branches executed
+system.cpu.iew.exec_stores                  167192873                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.192212                       # Inst execution rate
+system.cpu.iew.wb_sent                     1766892997                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1762390652                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1339756908                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2049972766                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.153012                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.654542                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.182762                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.653549                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       572398548                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       494260386                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9828987                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    756729949                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.020521                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.547401                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           8618895                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    739988037                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.066234                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.575521                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    287871292     38.04%     38.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    175370720     23.17%     61.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     57379665      7.58%     68.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     86292739     11.40%     80.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     27182541      3.59%     83.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27109377      3.58%     87.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9779675      1.29%     88.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8926185      1.18%     89.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     76817755     10.15%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    275878158     37.28%     37.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    172126899     23.26%     60.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     55937459      7.56%     68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     86300571     11.66%     79.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     25876597      3.50%     83.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26568843      3.59%     86.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9870767      1.33%     88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8919978      1.21%     89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     78508765     10.61%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    756729949                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    739988037                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -579,344 +577,344 @@ system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              76817755                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2781299443                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4280666670                       # The number of ROB writes
-system.cpu.timesIdled                            2296                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          197061                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              78508765                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2684728359                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4113896609                       # The number of ROB writes
+system.cpu.timesIdled                            2328                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          201987                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.009378                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.009378                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.990709                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.990709                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2762055581                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1465119637                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      7518                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      448                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 600894138                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                409652534                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               990211728                       # number of misc regfile reads
+system.cpu.cpi                               0.976461                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.976461                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.024106                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.024106                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2722667059                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1435857659                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      5817                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      496                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 596670071                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                405476387                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               971632449                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2534268                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.022618                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           387933013                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2538364                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            152.827968                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1679458500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.022618                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998052                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998052                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2530789                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.813367                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           381875640                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2534885                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            150.648112                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1673396500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.813367                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998001                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998001                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          875                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3171                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          871                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3172                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         784997698                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        784997698                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    239283827                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       239283827                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148189705                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148189705                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     387473532                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        387473532                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    387473532                       # number of overall hits
-system.cpu.dcache.overall_hits::total       387473532                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2785638                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2785638                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       970497                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       970497                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3756135                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3756135                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3756135                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3756135                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  59461217500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  59461217500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  30522057998                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  30522057998                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  89983275498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  89983275498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  89983275498                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  89983275498                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    242069465                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    242069465                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         772839713                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        772839713                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    233227342                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       233227342                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148173773                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148173773                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     381401115                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        381401115                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    381401115                       # number of overall hits
+system.cpu.dcache.overall_hits::total       381401115                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2764870                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2764870                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       986429                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       986429                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3751299                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3751299                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3751299                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3751299                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  58802289500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  58802289500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  31059853996                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  31059853996                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  89862143496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  89862143496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  89862143496                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  89862143496                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    235992212                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    235992212                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    391229667                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    391229667                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    391229667                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    391229667                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011508                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011508                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006506                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006506                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009601                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009601                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009601                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009601                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21345.636978                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21345.636978                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31449.925139                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31449.925139                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23956.347548                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23956.347548                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.347548                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23956.347548                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        11065                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           19                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1184                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.345439                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     9.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    385152414                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    385152414                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    385152414                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    385152414                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011716                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011716                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006613                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006613                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009740                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009740                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009740                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009740                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21267.650739                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21267.650739                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31487.166330                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31487.166330                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23954.940274                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23954.940274                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23954.940274                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23954.940274                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         9795                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            9                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1045                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.373206                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets            9                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2332624                       # number of writebacks
-system.cpu.dcache.writebacks::total           2332624                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1017670                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1017670                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19246                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        19246                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1036916                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1036916                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1036916                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1036916                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767968                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1767968                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       951251                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       951251                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2719219                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2719219                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2719219                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2719219                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33611924000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33611924000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29320675500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  29320675500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62932599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  62932599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62932599500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  62932599500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007304                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007304                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006377                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006377                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006950                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006950                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006950                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006950                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19011.613332                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19011.613332                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30823.279555                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30823.279555                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23143.630395                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23143.630395                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23143.630395                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23143.630395                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2330774                       # number of writebacks
+system.cpu.dcache.writebacks::total           2330774                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1000095                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1000095                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19339                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        19339                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1019434                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1019434                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1019434                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1019434                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764775                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764775                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       967090                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       967090                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2731865                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2731865                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2731865                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2731865                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33541518000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33541518000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29840523997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  29840523997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63382041997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  63382041997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63382041997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  63382041997                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007478                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007478                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006484                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006484                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007093                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.007093                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007093                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.007093                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19006.115794                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19006.115794                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30855.994785                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30855.994785                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23201.015422                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23201.015422                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23201.015422                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23201.015422                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              6980                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1050.498551                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           179263698                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              8570                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          20917.584364                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6640                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1037.923261                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           170565267                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8248                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          20679.591052                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1050.498551                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.512939                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.512939                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1590                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1165                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.776367                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         359107751                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        359107751                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    179266886                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       179266886                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     179266886                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        179266886                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    179266886                       # number of overall hits
-system.cpu.icache.overall_hits::total       179266886                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       192197                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        192197                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       192197                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         192197                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       192197                       # number of overall misses
-system.cpu.icache.overall_misses::total        192197                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1252320498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1252320498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1252320498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1252320498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1252320498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1252320498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    179459083                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    179459083                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    179459083                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    179459083                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    179459083                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    179459083                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001071                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001071                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001071                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001071                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001071                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001071                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6515.817094                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6515.817094                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6515.817094                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6515.817094                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6515.817094                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6515.817094                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1416                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1037.923261                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.506798                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.506798                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1608                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          322                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1153                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         341757570                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        341757570                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    170568161                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       170568161                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     170568161                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        170568161                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    170568161                       # number of overall hits
+system.cpu.icache.overall_hits::total       170568161                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       207953                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        207953                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       207953                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         207953                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       207953                       # number of overall misses
+system.cpu.icache.overall_misses::total        207953                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1300977000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1300977000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1300977000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1300977000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1300977000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1300977000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    170776114                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    170776114                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    170776114                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    170776114                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    170776114                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    170776114                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001218                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001218                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001218                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001218                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001218                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001218                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6256.110756                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6256.110756                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6256.110756                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6256.110756                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6256.110756                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6256.110756                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          718                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                21                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    67.428571                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    59.833333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2611                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2611                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2611                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2611                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2611                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2611                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       189586                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       189586                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       189586                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       189586                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       189586                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       189586                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    945150498                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    945150498                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    945150498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    945150498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    945150498                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    945150498                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001056                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001056                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001056                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001056                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001056                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001056                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4985.339097                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4985.339097                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4985.339097                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4985.339097                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4985.339097                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4985.339097                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2609                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2609                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2609                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2609                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2609                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2609                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       205344                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       205344                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       205344                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       205344                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       205344                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       205344                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    976991000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    976991000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    976991000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    976991000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    976991000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    976991000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001202                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001202                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001202                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001202                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001202                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001202                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4757.825892                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4757.825892                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4757.825892                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  4757.825892                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4757.825892                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  4757.825892                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           354113                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29616.739115                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3899842                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           386474                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.090826                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     197713230000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 20951.203852                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   251.356614                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8414.178648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.639380                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007671                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.256780                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.903831                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32361                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          244                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13363                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18669                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987579                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43221136                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43221136                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2332624                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2332624                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1893                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1893                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564122                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564122                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5120                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         5120                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590908                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1590908                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         5120                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2155030                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2160150                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         5120                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2155030                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2160150                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       178962                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       178962                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206662                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206662                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3498                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3498                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176672                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       176672                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3498                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       383334                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        386832                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3498                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       383334                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       386832                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13321000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     13321000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16381444000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16381444000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    284753500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    284753500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14216734500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  14216734500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    284753500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30598178500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30882932000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    284753500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30598178500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30882932000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2332624                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2332624                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       180855                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       180855                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       770784                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       770784                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8618                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         8618                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1767580                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1767580                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         8618                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2538364                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2546982                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         8618                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2538364                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2546982                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989533                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989533                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268119                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268119                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.405895                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.405895                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099951                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099951                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.405895                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.151016                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151879                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.405895                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.151016                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151879                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    74.434796                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    74.434796                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79266.841509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79266.841509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81404.659806                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81404.659806                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80469.652803                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80469.652803                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81404.659806                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79821.196398                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79835.515159                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81404.659806                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79821.196398                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79835.515159                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           353471                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29618.497788                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3892615                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           385807                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.089540                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     189374171500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 20946.463818                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   240.310071                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8431.723899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.639235                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.257316                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.903885                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32336                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          218                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13380                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18648                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986816                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43290247                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43290247                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2330774                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2330774                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1839                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1839                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       563945                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       563945                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4854                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         4854                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1588121                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1588121                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         4854                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2152066                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2156920                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         4854                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2152066                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2156920                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       195142                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       195142                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206554                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206554                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3382                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3382                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176265                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       176265                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3382                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       382819                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        386201                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3382                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       382819                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       386201                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13466000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     13466000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16374024500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16374024500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    275872500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    275872500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14180580000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  14180580000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    275872500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30554604500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30830477000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    275872500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30554604500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30830477000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2330774                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2330774                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       196981                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       196981                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       770499                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       770499                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8236                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8236                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1764386                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1764386                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8236                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2534885                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2543121                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8236                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2534885                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2543121                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990664                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990664                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268078                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.268078                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.410636                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.410636                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099902                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099902                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.410636                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.151020                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151861                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.410636                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.151020                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151861                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    69.006160                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    69.006160                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79272.367032                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79272.367032                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81570.816085                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81570.816085                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80450.344652                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80450.344652                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81570.816085                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.754492                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79830.132496                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81570.816085                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.754492                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79830.132496                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -925,136 +923,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       295029                       # number of writebacks
-system.cpu.l2cache.writebacks::total           295029                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       294833                       # number of writebacks
+system.cpu.l2cache.writebacks::total           294833                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2030                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         2030                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       178962                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       178962                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3497                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3497                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176672                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176672                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3497                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       383334                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       386831                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3497                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       383334                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       386831                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3764941068                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3764941068                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14314824000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14314824000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    249717000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    249717000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12450014500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12450014500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    249717000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26764838500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  27014555500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    249717000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26764838500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  27014555500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1941                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1941                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       195142                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       195142                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206554                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206554                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3381                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3381                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176265                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176265                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3381                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       382819                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       386200                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3381                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       382819                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       386200                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   4107801604                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   4107801604                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14308484500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14308484500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    242006000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    242006000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12417930000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12417930000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    242006000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26726414500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26968420500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    242006000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26726414500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26968420500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989533                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989533                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268119                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268119                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.405779                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.405779                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099951                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099951                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.405779                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151016                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151878                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.405779                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151016                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151878                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21037.656419                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21037.656419                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69266.841509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69266.841509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71408.921933                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71408.921933                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70469.652803                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70469.652803                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71408.921933                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69821.196398                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.549633                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71408.921933                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69821.196398                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.549633                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990664                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990664                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268078                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268078                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.410515                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.410515                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099902                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099902                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.410515                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151020                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151861                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.410515                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151020                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151861                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       1957165                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2627653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       256317                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       180855                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       180855                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       770784                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       770784                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       189586                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1767580                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       204722                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7961776                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8166498                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       551488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311743232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312294720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      535081                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5804166                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.061010                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.239349                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1969728                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2625607                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       254220                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       196981                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       196981                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       770499                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       770499                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       205344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1764386                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       219812                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7983854                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8203666                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       526976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311402176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          311929152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      550579                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5828110                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.060649                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.238686                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5450053     93.90%     93.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             354113      6.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5474639     93.94%     93.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             353471      6.06%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5804166                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5083850495                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     284382490                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5828110                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5096523027                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     308017990                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3897973573                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             180168                       # Transaction distribution
-system.membus.trans_dist::Writeback            295029                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            57519                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           179000                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          179000                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206624                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206624                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        180168                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1484132                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1484132                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1484132                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43636544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43636544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43636544                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy    3900818077                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             179644                       # Transaction distribution
+system.membus.trans_dist::Writeback            294833                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            57066                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           195189                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          195189                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206507                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206507                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        179645                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1514580                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1514580                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1514580                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43582976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43582976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43582976                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            918340                       # Request fanout histogram
+system.membus.snoop_fanout::samples            933240                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  918340    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  933240    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              918340                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2219848930                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2404009566                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              933240                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2243803396                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2433027599                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index de26fb04a..bab78d9da 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -134,7 +134,7 @@ system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -200,7 +200,7 @@ system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
index 607fa4fde..00495eb93 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr
index 664365742..3b53ebc6c 100644..100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
index 2951870e8..d34e3637b 100644..100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
@@ -3,14 +3,15 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  7 2014 10:41:53
-gem5 started May  7 2014 10:42:15
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:15:11
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.216667
-Exiting @ tick 220685290500 because target called exit()
+Exiting @ tick 225710988500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 1a7177e69..988455083 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.226045                       # Number of seconds simulated
-sim_ticks                                226044973500                       # Number of ticks simulated
-final_tick                               226044973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.225711                       # Number of seconds simulated
+sim_ticks                                225710988500                       # Number of ticks simulated
+final_tick                               225710988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 304016                       # Simulator instruction rate (inst/s)
-host_op_rate                                   304016                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              172378586                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302856                       # Number of bytes of host memory used
-host_seconds                                  1311.33                       # Real time elapsed on the host
+host_inst_rate                                 225638                       # Simulator instruction rate (inst/s)
+host_op_rate                                   225638                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              127748919                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297512                       # Number of bytes of host memory used
+host_seconds                                  1766.83                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            249344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            249088                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            254592                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               503936                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       249344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          249344                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3896                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               503680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       249088                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          249088                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3892                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7874                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1103073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1126289                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2229362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1103073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1103073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1103073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1126289                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2229362                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7874                       # Number of read requests accepted
+system.physmem.num_reads::total                  7870                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1103571                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1127956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2231526                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1103571                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1103571                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1103571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1127956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2231526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7870                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7874                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7870                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   503936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   503680                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    503936                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    503680                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 551                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 549                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 676                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 471                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 633                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 475                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 478                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 474                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 477                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 563                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 560                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 470                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    226044886000                       # Total gap between requests
+system.physmem.totGap                    225710901000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7874                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7870                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6812                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6816                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       969                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1551                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      323.878788                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     193.961760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.450478                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            540     34.82%     34.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          341     21.99%     56.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          198     12.77%     69.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          105      6.77%     76.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           68      4.38%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           43      2.77%     83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.13%     85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           36      2.32%     87.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          187     12.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1551                       # Bytes accessed per row activation
-system.physmem.totQLat                       53691750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 201329250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     39370000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6818.87                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1545                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      324.680906                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.047178                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.516800                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            535     34.63%     34.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          349     22.59%     57.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          192     12.43%     69.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          105      6.80%     76.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           65      4.21%     80.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           39      2.52%     83.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      2.14%     85.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           33      2.14%     87.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          194     12.56%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1545                       # Bytes accessed per row activation
+system.physmem.totQLat                       52849750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 200412250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     39350000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6715.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25568.87                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25465.34                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.23                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,70 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6316                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6317                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.21                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.27                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28707757.94                       # Average gap between requests
-system.physmem.pageHitRate                      80.21                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6811560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3716625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  34210800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28679911.18                       # Average gap between requests
+system.physmem.pageHitRate                      80.27                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6743520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3679500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  34132800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14764005360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5854324365                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           130490358000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             151153426710                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.693587                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   217080502500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7548060000                       # Time in different power states
+system.physmem_0.refreshEnergy            14742137280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5830950375                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           130309976250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             150927619725                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.685069                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   216780859000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7536880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1414335000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1390733500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4914000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2681250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  27011400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4936680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2693625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  27003600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14764005360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5569701705                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           130740027000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             151108340715                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.494129                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   217498306250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7548060000                       # Time in different power states
+system.physmem_1.refreshEnergy            14742137280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5568136200                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           130540515000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             150885422385                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.498114                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   217165940000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7536880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       997097750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1005282000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                46270920                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26727376                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1017825                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25620092                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21360645                       # Number of BTB hits
+system.cpu.branchPred.lookups                46155674                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26673496                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            964868                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25433927                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21299796                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.374584                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8341957                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.745605                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8306241                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                322                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     95612152                       # DTB read hits
-system.cpu.dtb.read_misses                        116                       # DTB read misses
+system.cpu.dtb.read_hits                     95501420                       # DTB read hits
+system.cpu.dtb.read_misses                        115                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 95612268                       # DTB read accesses
-system.cpu.dtb.write_hits                    73605970                       # DTB write hits
-system.cpu.dtb.write_misses                       858                       # DTB write misses
+system.cpu.dtb.read_accesses                 95501535                       # DTB read accesses
+system.cpu.dtb.write_hits                    73594615                       # DTB write hits
+system.cpu.dtb.write_misses                       852                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73606828                       # DTB write accesses
-system.cpu.dtb.data_hits                    169218122                       # DTB hits
-system.cpu.dtb.data_misses                        974                       # DTB misses
+system.cpu.dtb.write_accesses                73595467                       # DTB write accesses
+system.cpu.dtb.data_hits                    169096035                       # DTB hits
+system.cpu.dtb.data_misses                        967                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                169219096                       # DTB accesses
-system.cpu.itb.fetch_hits                    98739640                       # ITB hits
-system.cpu.itb.fetch_misses                      1232                       # ITB misses
+system.cpu.dtb.data_accesses                169097002                       # DTB accesses
+system.cpu.itb.fetch_hits                    98403660                       # ITB hits
+system.cpu.itb.fetch_misses                      1242                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                98740872                       # ITB accesses
+system.cpu.itb.fetch_accesses                98404902                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,83 +293,83 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        452089947                       # number of cpu cycles simulated
+system.cpu.numCycles                        451421977                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664665                       # Number of instructions committed
 system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4488161                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       4268732                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.134011                       # CPI: cycles per instruction
-system.cpu.ipc                               0.881826                       # IPC: instructions per cycle
-system.cpu.tickCycles                       448265885                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3824062                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.132335                       # CPI: cycles per instruction
+system.cpu.ipc                               0.883131                       # IPC: instructions per cycle
+system.cpu.tickCycles                       447606238                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3815739                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.715048                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168032888                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.720604                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           167948311                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40344.030732                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40323.724130                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3291.715048                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803641                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803641                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3291.720604                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803643                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803643                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3113                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336084171                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336084171                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     94518093                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94518093                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73514795                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514795                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     168032888                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168032888                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168032888                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168032888                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1180                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1180                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5935                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5935                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses         335915017                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        335915017                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     94433513                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94433513                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73514798                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514798                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     167948311                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        167948311                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    167948311                       # number of overall hits
+system.cpu.dcache.overall_hits::total       167948311                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1183                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1183                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         5932                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5932                       # number of WriteReq misses
 system.cpu.dcache.demand_misses::cpu.data         7115                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total           7115                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         7115                       # number of overall misses
 system.cpu.dcache.overall_misses::total          7115                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     87916000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     87916000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    428863500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    428863500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    516779500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    516779500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    516779500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    516779500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94519273                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94519273                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     87406500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     87406500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    430164000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    430164000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    517570500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    517570500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    517570500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    517570500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94434696                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94434696                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168040003                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168040003                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168040003                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168040003                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000012                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    167955426                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167955426                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167955426                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167955426                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000013                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000081                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72632.396346                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72632.396346                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72743.569923                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72743.569923                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -380,10 +380,10 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          654                       # number of writebacks
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2739                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2739                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          214                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          214                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2736                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2736                       # number of WriteReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data         2950                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total         2950                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data         2950                       # number of overall MSHR hits
@@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4165
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     71088500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     71088500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    239432500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    239432500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    310521000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    310521000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    310521000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    310521000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     70744000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     70744000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    240380000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    240380000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    311124000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    311124000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    311124000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    311124000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3197                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1918.682192                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98734465                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              5175                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          19079.123671                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3187                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1919.659270                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            98398495                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5165                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          19051.015489                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1918.682192                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.936857                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.936857                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1919.659270                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.937334                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.937334                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1281                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         197484455                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        197484455                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     98734465                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98734465                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      98734465                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98734465                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     98734465                       # number of overall hits
-system.cpu.icache.overall_hits::total        98734465                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5175                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5175                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5175                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5175                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5175                       # number of overall misses
-system.cpu.icache.overall_misses::total          5175                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    319209000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    319209000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    319209000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    319209000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    319209000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    319209000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     98739640                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98739640                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     98739640                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98739640                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     98739640                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98739640                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         196812485                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        196812485                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     98398495                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        98398495                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      98398495                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         98398495                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     98398495                       # number of overall hits
+system.cpu.icache.overall_hits::total        98398495                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5165                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5165                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5165                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5165                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5165                       # number of overall misses
+system.cpu.icache.overall_misses::total          5165                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    317382500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    317382500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    317382500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    317382500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    317382500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    317382500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     98403660                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     98403660                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     98403660                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     98403660                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     98403660                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     98403660                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61682.898551                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61682.898551                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.693127                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61448.693127                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.693127                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61448.693127                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -482,128 +482,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5175                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5175                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5175                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5175                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5175                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5175                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    314034000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    314034000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    314034000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    314034000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    314034000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    314034000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5165                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         5165                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         5165                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         5165                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         5165                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         5165                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312217500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    312217500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312217500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    312217500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312217500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    312217500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000052                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60682.898551                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60682.898551                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60682.898551                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60682.898551                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60682.898551                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60682.898551                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60448.693127                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 60448.693127                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60448.693127                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4426.586364                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               4808                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5274                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.911642                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4422.016724                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               4792                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5270                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.909298                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   373.093241                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3411.507533                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   641.985590                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011386                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104111                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   372.106243                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3407.923384                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   641.987096                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011356                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104002                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019592                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.135089                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.134949                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5270                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4443                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160950                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           114936                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          114936                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4439                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160828                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           114772                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          114772                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks          654                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          654                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1279                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         1279                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1273                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         1273                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          126                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          126                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1279                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         1273                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          187                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1466                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1279                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            1460                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1273                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          187                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1466                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1460                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3137                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3896                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3896                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3892                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3892                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          841                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          841                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3896                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3892                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         3978                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7874                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3896                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          7870                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3892                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3978                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7874                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    234115500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    234115500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    292841000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    292841000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     68160500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     68160500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    292841000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    302276000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    595117000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    292841000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    302276000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    595117000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total         7870                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    235063000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    235063000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    291102500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    291102500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     67816500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     67816500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    291102500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    302879500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    593982000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    291102500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    302879500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    593982000                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          654                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3198                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5175                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         5175                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5165                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         5165                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          967                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          967                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         5175                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         5165                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4165                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9340                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         5175                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9330                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         5165                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4165                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9340                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9330                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980926                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.980926                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.752850                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.752850                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753533                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753533                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.869700                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.869700                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.752850                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753533                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.955102                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.843041                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.752850                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.843516                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.753533                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955102                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.843041                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74630.379343                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74630.379343                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75164.527721                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75164.527721                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81046.967895                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81046.967895                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75164.527721                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75986.928105                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75580.010160                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75164.527721                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75986.928105                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75580.010160                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.843516                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74932.419509                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74932.419509                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74795.092497                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74795.092497                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80637.931034                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80637.931034                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74795.092497                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76138.637506                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75474.205845                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74795.092497                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76138.637506                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75474.205845                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -614,106 +614,106 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3137                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3137                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3896                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3896                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3892                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3892                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          841                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          841                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3896                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3892                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         3978                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7874                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3896                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7870                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3892                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3978                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7874                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    202745500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    202745500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    253881000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    253881000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     59750500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     59750500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    253881000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    262496000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    516377000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    253881000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    262496000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    516377000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         7870                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    203693000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    203693000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    252182500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    252182500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     59406500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     59406500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    252182500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    263099500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    515282000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    252182500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    263099500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    515282000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980926                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980926                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.752850                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.752850                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753533                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.869700                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.869700                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.752850                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.843041                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.752850                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.843516                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.843041                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.843516                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp          6142                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          6132                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         3314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         3304                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         5175                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         5165                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          967                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13547                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13517                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             22648                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       331200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             22618                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       330560                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             639616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             638976                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13308                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        13288                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              13308    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              13288    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13308                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7308000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          13288                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7298000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7762500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7747500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6247999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4737                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4733                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              3137                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             3137                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4737                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15748                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15748                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       503936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  503936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          4733                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15740                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15740                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       503680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  503680                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7874                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7870                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7874    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7870    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7874                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9183500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7870                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9171000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           41813250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           41782250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index b0756d2d6..fda724fd7 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -497,7 +497,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -546,7 +546,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -609,7 +609,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index c9fcb56b0..d6aa6688c 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:19:59
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 20:55:00
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -12,4 +14,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.066667
-Exiting @ tick 69793219500 because target called exit()
+Exiting @ tick 67874346000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index be9d713b1..49a2168d9 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.069809                       # Number of seconds simulated
-sim_ticks                                 69809049000                       # Number of ticks simulated
-final_tick                                69809049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.067874                       # Number of seconds simulated
+sim_ticks                                 67874346000                       # Number of ticks simulated
+final_tick                                67874346000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 246384                       # Simulator instruction rate (inst/s)
-host_op_rate                                   246384                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45796096                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304152                       # Number of bytes of host memory used
-host_seconds                                  1524.35                       # Real time elapsed on the host
+host_inst_rate                                 172313                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172313                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               31140671                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298536                       # Number of bytes of host memory used
+host_seconds                                  2179.60                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255680                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               477184                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221504                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3461                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3995                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7456                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3172998                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3662562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6835561                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3172998                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3172998                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3172998                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3662562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6835561                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7456                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            220544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255296                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               475840                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       220544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220544                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3446                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7435                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3249298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3761303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7010602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3249298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3249298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3249298                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3761303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7010602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7435                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7456                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7435                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   477184                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   475840                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    477184                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    475840                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 527                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 655                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 454                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 524                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 653                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 455                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 515                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 525                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 439                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 454                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 513                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 523                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 435                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 407                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                338                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                305                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                542                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                455                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                453                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                379                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     69808953500                       # Total gap between requests
+system.physmem.totGap                     67874250500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7456                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7435                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4273                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1892                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       906                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       323                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4258                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1860                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       924                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       329                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      349.142435                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     207.457712                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     347.186854                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            436     32.18%     32.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          321     23.69%     55.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          135      9.96%     65.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          103      7.60%     73.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           56      4.13%     77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           42      3.10%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           37      2.73%     83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           28      2.07%     85.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          197     14.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1355                       # Bytes accessed per row activation
-system.physmem.totQLat                       63176250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 202976250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37280000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8473.21                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1352                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      350.437870                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     208.390396                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     346.239962                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            445     32.91%     32.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          293     21.67%     54.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          153     11.32%     65.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           95      7.03%     72.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           63      4.66%     77.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           39      2.88%     80.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           40      2.96%     83.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           30      2.22%     85.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          194     14.35%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1352                       # Bytes accessed per row activation
+system.physmem.totQLat                       65565000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 204971250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37175000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8818.43                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27223.21                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.84                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27568.43                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           7.01                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        7.01                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6090                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6075                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.68                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.71                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9362788.83                       # Average gap between requests
-system.physmem.pageHitRate                      81.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5828760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3180375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  32370000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      9129018.22                       # Average gap between requests
+system.physmem.pageHitRate                      81.71                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5866560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3201000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  32260800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4559240400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2097349200                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            40042614750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              46740583485                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.597578                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    66614495250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2330900000                       # Time in different power states
+system.physmem_0.refreshEnergy             4433117520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2086073460                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            38893911750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              45454431090                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.698264                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    64700624500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2266420000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       861488750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       905970500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4399920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2400750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  25256400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4354560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2376000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  25482600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4559240400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1988059680                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            40138482750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              46717839900                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.271757                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    66771998750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2330900000                       # Time in different power states
+system.physmem_1.refreshEnergy             4433117520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1937209410                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            39024494250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              45427034340                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.294616                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    64919021500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2266420000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       701106250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       687756000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                51296431                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          29722668                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1234399                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             27069453                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23684308                       # Number of BTB hits
+system.cpu.branchPred.lookups                50012521                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          28997086                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            979524                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24735831                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                22942844                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.494594                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9353372                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                312                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.751458                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9100143                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                303                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    103786850                       # DTB read hits
-system.cpu.dtb.read_misses                      91978                       # DTB read misses
-system.cpu.dtb.read_acv                         49358                       # DTB read access violations
-system.cpu.dtb.read_accesses                103878828                       # DTB read accesses
-system.cpu.dtb.write_hits                    79421845                       # DTB write hits
-system.cpu.dtb.write_misses                      1562                       # DTB write misses
+system.cpu.dtb.read_hits                    102391599                       # DTB read hits
+system.cpu.dtb.read_misses                      62990                       # DTB read misses
+system.cpu.dtb.read_acv                         49453                       # DTB read access violations
+system.cpu.dtb.read_accesses                102454589                       # DTB read accesses
+system.cpu.dtb.write_hits                    78819200                       # DTB write hits
+system.cpu.dtb.write_misses                      1456                       # DTB write misses
 system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                79423407                       # DTB write accesses
-system.cpu.dtb.data_hits                    183208695                       # DTB hits
-system.cpu.dtb.data_misses                      93540                       # DTB misses
-system.cpu.dtb.data_acv                         49360                       # DTB access violations
-system.cpu.dtb.data_accesses                183302235                       # DTB accesses
-system.cpu.itb.fetch_hits                    51432488                       # ITB hits
-system.cpu.itb.fetch_misses                       372                       # ITB misses
+system.cpu.dtb.write_accesses                78820656                       # DTB write accesses
+system.cpu.dtb.data_hits                    181210799                       # DTB hits
+system.cpu.dtb.data_misses                      64446                       # DTB misses
+system.cpu.dtb.data_acv                         49455                       # DTB access violations
+system.cpu.dtb.data_accesses                181275245                       # DTB accesses
+system.cpu.itb.fetch_hits                    49841893                       # ITB hits
+system.cpu.itb.fetch_misses                       342                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                51432860                       # ITB accesses
+system.cpu.itb.fetch_accesses                49842235                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,239 +293,239 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        139618100                       # number of cpu cycles simulated
+system.cpu.numCycles                        135748695                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           52215637                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      458041697                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    51296431                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33037680                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      85803922                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2575582                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           50498280                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      448284151                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    50012521                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           32042987                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      83907127                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2061462                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  177                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         13927                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           49                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  51432488                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                569689                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          139321507                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.287660                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.344182                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13448                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           46                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  49841893                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                439921                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          135449808                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.309596                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.352335                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58400173     41.92%     41.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4522566      3.25%     45.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7306043      5.24%     50.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5576459      4.00%     54.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 12017776      8.63%     63.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  8032548      5.77%     68.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5948759      4.27%     73.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1886194      1.35%     74.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35630989     25.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 56539159     41.74%     41.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4401809      3.25%     44.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  7053804      5.21%     50.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5366390      3.96%     54.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11526105      8.51%     62.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7792927      5.75%     68.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5844960      4.32%     72.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1860483      1.37%     74.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35064171     25.89%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            139321507                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367405                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.280676                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45279858                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              16277373                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  71952167                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4528520                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1283589                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9590263                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4245                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              452242919                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 14142                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1283589                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 47190225                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5719256                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         519758                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  74463142                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10145537                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              448534058                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                439648                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2541243                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2902301                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3500431                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           292850852                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             590664412                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        420646005                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         170018406                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            135449808                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.368420                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.302309                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 43878250                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              15711242                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  70556820                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4276924                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1026572                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9420233                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4199                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              443516613                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 13825                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1026572                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45656178                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5038667                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         519602                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  72948338                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10260451                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              440529832                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                437774                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2529018                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2798103                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3728351                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           287391913                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             579992044                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        412277767                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         167714276                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 33318523                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37911                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            320                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  16086321                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            106433302                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            81699514                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12490023                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9782021                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  415154479                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 307                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 407277518                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            483889                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        39579977                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     18549388                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             92                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     139321507                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.923293                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.222373                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 27859584                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37459                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            301                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  15899092                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104653375                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            80643825                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12436283                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9680421                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  409213494                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 295                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 402403006                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            455901                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        33638980                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     16018200                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             80                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     135449808                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.970864                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.211480                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24043039     17.26%     17.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19688824     14.13%     31.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22672553     16.27%     47.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18939258     13.59%     61.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19545668     14.03%     75.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            14219061     10.21%     85.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9684319      6.95%     92.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6188357      4.44%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4340428      3.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            21699625     16.02%     16.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19301136     14.25%     30.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22441860     16.57%     46.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18632936     13.76%     60.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19381094     14.31%     74.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            13936411     10.29%     85.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9566467      7.06%     92.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6208123      4.58%     96.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4282156      3.16%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       139321507                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       135449808                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  265122      1.33%      1.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      1      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                151057      0.76%      2.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 93335      0.47%      2.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  3062      0.02%      2.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              3506383     17.53%     20.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1668666      8.34%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9341831     46.71%     75.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4968318     24.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  249921      1.26%      1.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                142099      0.71%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 92744      0.47%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  4235      0.02%      2.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3484759     17.51%     19.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1673016      8.41%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9313907     46.79%     75.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4943226     24.84%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             153385991     37.66%     37.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2128232      0.52%     38.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             151496219     37.65%     37.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128363      0.53%     38.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            37448194      9.19%     47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7543709      1.85%     49.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2805732      0.69%     49.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16759263      4.11%     54.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1610357      0.40%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            105461195     25.89%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            80101264     19.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            37051349      9.21%     47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7361129      1.83%     49.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2793884      0.69%     49.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16753499      4.16%     54.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1596248      0.40%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            103848617     25.81%     80.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            79340117     19.72%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              407277518                       # Type of FU issued
-system.cpu.iq.rate                           2.917083                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19997775                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.049101                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          626671270                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         266840013                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    237433052                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           347686937                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          187970906                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    163426789                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              246404368                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               180837344                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19931279                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              402403006                       # Type of FU issued
+system.cpu.iq.rate                           2.964323                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    19903907                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.049463                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          615743047                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         258422157                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    234653025                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           344872581                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          184503638                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    162319054                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              242850926                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               179422406                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19947233                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     11678815                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       164981                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        76480                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      8178785                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      9898888                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       123887                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        73372                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7123096                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       381276                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3827                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       383831                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3808                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1283589                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 4537578                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                127300                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           440164979                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            164208                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             106433302                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             81699514                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                307                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   6586                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                117247                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          76480                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1004792                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       416739                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1421531                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             403496390                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             103928218                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3781128                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1026572                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3903842                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 90265                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           434136051                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             99585                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104653375                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             80643825                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                295                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   7679                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 82299                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          73372                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         826459                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       307772                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1134231                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             399253806                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             102504065                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3149200                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      25010193                       # number of nop insts executed
-system.cpu.iew.exec_refs                    183351660                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 47000418                       # Number of branches executed
-system.cpu.iew.exec_stores                   79423442                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.890001                       # Inst execution rate
-system.cpu.iew.wb_sent                      401708524                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     400859841                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 198115569                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 284128842                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      24922262                       # number of nop insts executed
+system.cpu.iew.exec_refs                    181324750                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 46546315                       # Number of branches executed
+system.cpu.iew.exec_stores                   78820685                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.941124                       # Inst execution rate
+system.cpu.iew.wb_sent                      397727618                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     396972079                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 196558282                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 281889088                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.871117                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.697274                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.924316                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.697289                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        41501718                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        35472304                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1230197                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    133512631                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.985969                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.212275                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            975365                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    130528765                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.054228                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.231390                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     48674660     36.46%     36.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18127731     13.58%     50.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      9648746      7.23%     57.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8719124      6.53%     63.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6443109      4.83%     68.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4416607      3.31%     71.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5004547      3.75%     75.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2625621      1.97%     77.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     29852486     22.36%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     46472448     35.60%     35.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     17656165     13.53%     49.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      9417491      7.21%     56.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8632138      6.61%     62.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6273043      4.81%     67.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4304526      3.30%     71.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4966466      3.80%     74.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2588480      1.98%     76.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30218008     23.15%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    133512631                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    130528765                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,333 +571,333 @@ system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              29852486                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    543823469                       # The number of ROB reads
-system.cpu.rob.rob_writes                   886153369                       # The number of ROB writes
-system.cpu.timesIdled                            3159                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          296593                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              30218008                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    534444667                       # The number of ROB reads
+system.cpu.rob.rob_writes                   873208037                       # The number of ROB writes
+system.cpu.timesIdled                            3160                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          298887                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.371745                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.371745                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.690015                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.690015                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                403553331                       # number of integer regfile reads
-system.cpu.int_regfile_writes               172072539                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 158043337                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                105673333                       # number of floating regfile writes
+system.cpu.cpi                               0.361442                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.361442                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.766692                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.766692                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                399091287                       # number of integer regfile reads
+system.cpu.int_regfile_writes               169885620                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 156870882                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                104904950                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements               795                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3296.035456                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           156970312                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4197                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37400.598523                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               777                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3293.050932                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           155556653                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4177                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37241.238449                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3296.035456                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.804696                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.804696                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3402                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  3293.050932                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803968                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803968                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3400                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          212                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3116                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.830566                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         313987939                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        313987939                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     83469338                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        83469338                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73500964                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73500964                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           10                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           10                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     156970302                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        156970302                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    156970302                       # number of overall hits
-system.cpu.dcache.overall_hits::total       156970302                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1794                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1794                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19765                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19765                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21559                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21559                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21559                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21559                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    128871000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    128871000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1185279954                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1185279954                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1314150954                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1314150954                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1314150954                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1314150954                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     83471132                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     83471132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.830078                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         311160441                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        311160441                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     82055589                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        82055589                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501058                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501058                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     155556647                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        155556647                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    155556647                       # number of overall hits
+system.cpu.dcache.overall_hits::total       155556647                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1808                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1808                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19671                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19671                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21479                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21479                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21479                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21479                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    128709000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    128709000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1198982453                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1198982453                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1327691453                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1327691453                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1327691453                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1327691453                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     82057397                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     82057397                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           10                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           10                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    156991861                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    156991861                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    156991861                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    156991861                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000269                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000269                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000137                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000137                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000137                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000137                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71834.448161                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71834.448161                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.629092                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.629092                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60956.025511                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60956.025511                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60956.025511                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60956.025511                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        49421                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           88                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               747                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    155578126                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    155578126                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    155578126                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    155578126                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000268                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000138                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000138                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71188.606195                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71188.606195                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60951.779421                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60951.779421                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61813.466782                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61813.466782                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61813.466782                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61813.466782                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        49798                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           86                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               748                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.159304                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           88                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.574866                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           86                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          671                       # number of writebacks
-system.cpu.dcache.writebacks::total               671                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          799                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          799                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16563                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16563                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17362                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17362                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17362                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17362                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          995                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          995                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4197                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4197                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4197                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4197                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     76593500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     76593500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    246844000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    246844000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    323437500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    323437500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    323437500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    323437500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks          656                       # number of writebacks
+system.cpu.dcache.writebacks::total               656                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          820                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          820                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16482                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16482                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17302                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17302                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17302                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17302                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          988                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          988                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3189                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3189                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4177                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4177                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4177                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4177                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75199500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     75199500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    250368000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    250368000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    325567500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    325567500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    325567500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    325567500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76978.391960                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76978.391960                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77090.568395                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77090.568395                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77063.974267                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77063.974267                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77063.974267                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77063.974267                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76112.854251                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76112.854251                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78509.877705                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78509.877705                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77942.901604                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77942.901604                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77942.901604                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77942.901604                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2157                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1832.216020                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            51426803                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4084                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12592.263222                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2126                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1833.088267                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            49836296                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4054                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12293.116922                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1832.216020                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894637                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894637                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1927                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1833.088267                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.895063                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.895063                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          293                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1347                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.940918                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         102869060                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        102869060                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     51426803                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        51426803                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      51426803                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         51426803                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     51426803                       # number of overall hits
-system.cpu.icache.overall_hits::total        51426803                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5685                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5685                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5685                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5685                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5685                       # number of overall misses
-system.cpu.icache.overall_misses::total          5685                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    368406498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    368406498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    368406498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    368406498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    368406498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    368406498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     51432488                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     51432488                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     51432488                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     51432488                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     51432488                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     51432488                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000111                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000111                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000111                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000111                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000111                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000111                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64803.253826                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64803.253826                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64803.253826                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64803.253826                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64803.253826                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64803.253826                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          546                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          287                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1353                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          99687840                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         99687840                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     49836296                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        49836296                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      49836296                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         49836296                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     49836296                       # number of overall hits
+system.cpu.icache.overall_hits::total        49836296                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5597                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5597                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5597                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5597                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5597                       # number of overall misses
+system.cpu.icache.overall_misses::total          5597                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    364082499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    364082499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    364082499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    364082499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    364082499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    364082499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     49841893                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     49841893                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     49841893                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     49841893                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     49841893                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     49841893                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000112                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000112                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000112                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000112                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000112                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000112                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65049.579954                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 65049.579954                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 65049.579954                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 65049.579954                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 65049.579954                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 65049.579954                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          650                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    68.250000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    92.857143                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1601                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1601                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1601                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1601                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1601                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1601                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4084                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4084                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4084                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4084                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4084                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4084                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    275253499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    275253499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    275253499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    275253499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    275253499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    275253499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67398.016405                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67398.016405                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67398.016405                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67398.016405                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67398.016405                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67398.016405                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1543                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1543                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1543                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1543                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1543                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1543                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4054                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4054                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4054                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4054                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4054                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4054                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    273657000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    273657000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    273657000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    273657000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    273657000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    273657000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000081                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000081                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67502.960039                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67502.960039                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67502.960039                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67502.960039                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67502.960039                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67502.960039                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4020.332980                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3138                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4861                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.645546                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4002.026272                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3073                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4841                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.634786                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   372.062557                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2982.230615                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   666.039808                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011354                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.091010                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020326                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122691                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4861                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          530                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4047                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148346                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            97927                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           97927                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          671                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          671                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           71                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           71                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          623                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          623                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data          131                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total          131                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          623                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          202                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             825                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          623                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          202                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            825                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         3131                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3131                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3461                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3461                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          864                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          864                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3461                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3995                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7456                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3461                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3995                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7456                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    241202500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    241202500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262576000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    262576000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     73634500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     73634500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    262576000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    314837000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    577413000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    262576000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    314837000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    577413000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          671                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          671                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4084                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4084                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          995                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          995                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4084                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4197                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8281                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4084                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4197                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8281                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.977826                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.977826                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.847453                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.847453                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.868342                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.868342                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.847453                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.951870                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.900374                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.847453                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.951870                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.900374                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77036.889173                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77036.889173                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.090436                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.090436                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85225.115741                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85225.115741                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.090436                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78807.759700                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77442.730687                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.090436                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78807.759700                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77442.730687                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks   371.009955                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2970.733849                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   660.282469                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011322                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090660                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.020150                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.122132                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4841                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          528                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4030                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.147736                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            97102                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           97102                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks          656                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          656                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          608                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          608                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data          128                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total          128                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          608                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          188                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             796                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          608                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          188                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            796                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3129                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3129                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3446                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3446                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          860                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          860                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3446                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3989                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7435                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3446                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3989                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7435                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    244858000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    244858000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261180500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    261180500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     72283000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     72283000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    261180500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    317141000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    578321500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    261180500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    317141000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    578321500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks          656                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          656                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3189                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3189                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4054                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4054                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          988                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          988                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4054                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4177                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8231                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4054                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4177                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8231                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981185                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981185                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.850025                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.850025                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.870445                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.870445                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.850025                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.954992                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.903292                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850025                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.954992                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.903292                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78254.394375                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78254.394375                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75792.367963                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75792.367963                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        84050                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        84050                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75792.367963                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79503.885686                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77783.658373                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75792.367963                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79503.885686                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77783.658373                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -906,108 +906,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3131                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3131                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3461                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3461                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          864                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          864                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3461                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3995                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7456                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3461                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3995                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7456                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    209892500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    209892500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    227966000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    227966000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     64994500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     64994500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    227966000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    274887000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    502853000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    227966000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    274887000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    502853000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.977826                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.977826                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.847453                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.847453                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.868342                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.868342                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.847453                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.951870                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.900374                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.847453                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.951870                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.900374                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67036.889173                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67036.889173                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65867.090436                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65867.090436                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75225.115741                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75225.115741                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65867.090436                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68807.759700                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67442.730687                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65867.090436                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68807.759700                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67442.730687                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3129                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3129                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3446                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3446                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          860                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          860                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3446                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3989                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7435                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3446                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7435                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    213568000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    213568000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    226720500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    226720500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63683000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63683000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    226720500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    277251000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    503971500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    226720500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    277251000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    503971500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981185                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981185                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.850025                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.870445                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.870445                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.903292                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.903292                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68254.394375                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68254.394375                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65792.367963                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65792.367963                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        74050                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        74050                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65792.367963                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69503.885686                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67783.658373                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp          5079                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          671                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         2281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3202                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3202                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4084                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          995                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10325                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9189                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19514                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       261376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       311552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             572928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp          5042                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          656                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2247                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3189                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3189                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4054                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          988                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10234                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9131                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19365                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       259456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             568768                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        11233                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        11134                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              11233    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              11134    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          11233                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        6287500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          11134                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        6223000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6126000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6081000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6295500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6265500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4325                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3131                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3131                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4325                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       477184                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  477184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4306                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3129                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3129                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4306                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14870                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14870                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       475840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  475840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7456                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7435                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7456    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7435    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7456                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9215500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7435                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9180000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           39331250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           39204250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index ca6ea576a..427c7c717 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -118,7 +118,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -167,7 +167,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
index e8259a3e5..c0afc2364 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -759,7 +759,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
index 3857083f4..8d785cb1f 100755
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:25:17
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x3ccd9b0
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Eon, Version 1.1
@@ -14,4 +16,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.210000
-Exiting @ tick 216864820000 because target called exit()
+Exiting @ tick 215505832500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 454441ad4..333ae52c9 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,60 +1,60 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.216071                       # Number of seconds simulated
-sim_ticks                                216071083000                       # Number of ticks simulated
-final_tick                               216071083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.215506                       # Number of seconds simulated
+sim_ticks                                215505832500                       # Number of ticks simulated
+final_tick                               215505832500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173126                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207857                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              137004908                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323124                       # Number of bytes of host memory used
-host_seconds                                  1577.10                       # Real time elapsed on the host
+host_inst_rate                                 114925                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137980                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               90709005                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317788                       # Number of bytes of host memory used
+host_seconds                                  2375.79                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            219072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            218880                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               485440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219072                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3423                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               485248                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       218880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          218880                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3420                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7585                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1013889                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1232779                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2246668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1013889                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1013889                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1013889                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1232779                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2246668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7585                       # Number of read requests accepted
+system.physmem.num_reads::total                  7582                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1015657                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1236013                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2251670                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1015657                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1015657                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1015657                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1236013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2251670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7582                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7585                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7582                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   485440                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   485248                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    485440                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    485248                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 630                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 843                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 844                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 173                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 171                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 311                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 310                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                706                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                705                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    216070847500                       # Total gap between requests
+system.physmem.totGap                    215505593500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7585                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7582                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       892                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1505                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      321.445847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.975712                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.801659                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            552     36.68%     36.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          337     22.39%     59.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          156     10.37%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           81      5.38%     74.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           75      4.98%     79.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           59      3.92%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           41      2.72%     86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           29      1.93%     88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          175     11.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1505                       # Bytes accessed per row activation
-system.physmem.totQLat                       52368250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 194587000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37925000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6904.19                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1519                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      318.272548                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     188.961816                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.159233                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            550     36.21%     36.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          342     22.51%     58.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          179     11.78%     70.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           82      5.40%     75.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           73      4.81%     80.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           43      2.83%     83.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           37      2.44%     85.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           30      1.97%     87.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          183     12.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1519                       # Bytes accessed per row activation
+system.physmem.totQLat                       52046750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 194209250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37910000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6864.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25654.19                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25614.51                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6074                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6056                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.08                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.87                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28486598.22                       # Average gap between requests
-system.physmem.pageHitRate                      80.08                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5050080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2755500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  29959800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28423317.53                       # Average gap between requests
+system.physmem.pageHitRate                      79.87                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4997160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2726625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  29905200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14112540000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5672899350                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           124664991000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             144488195730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.714152                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   207389955000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7215000000                       # Time in different power states
+system.physmem_0.refreshEnergy            14075415120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5632744275                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           124359177000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             144104965380                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.699601                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   206882994500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7196020000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1464485500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1423707500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6320160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3448500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28992600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6463800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3526875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28977000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14112540000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5762856465                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           124586081250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             144500238975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.769890                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   207255387750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7215000000                       # Time in different power states
+system.physmem_1.refreshEnergy            14075415120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5808881115                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           124204671000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             144127934910                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.806188                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   206624169250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7196020000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1598323500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1683261250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                33111389                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17094855                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1552605                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17374125                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15590921                       # Number of BTB hits
+system.cpu.branchPred.lookups                32816945                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16892744                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1463888                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17497063                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                15468368                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.736439                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6603992                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             88.405511                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6575577                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,26 +377,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        432142166                       # number of cpu cycles simulated
+system.cpu.numCycles                        431011665                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037857                       # Number of instructions committed
 system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4177938                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       3889170                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.582719                       # CPI: cycles per instruction
-system.cpu.ipc                               0.631824                       # IPC: instructions per cycle
-system.cpu.tickCycles                       428506724                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3635442                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.578578                       # CPI: cycles per instruction
+system.cpu.ipc                               0.633481                       # IPC: instructions per cycle
+system.cpu.tickCycles                       427409330                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3602335                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.759854                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168767138                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3085.814933                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168714880                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37412.356019                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37400.771448                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.759854                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753359                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753359                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.814933                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753373                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753373                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
@@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           12
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337553367                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337553367                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86634356                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86634356                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82047452                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82047452                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63540                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63540                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         337448855                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337448855                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86582107                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86582107                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82047449                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82047449                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        63534                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         63534                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168681808                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168681808                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168745348                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168745348                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     168629556                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168629556                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168693090                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168693090                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         2059                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          2059                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5225                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5225                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            6                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            6                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         7284                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7284                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7290                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    134727000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    134727000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    395694000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    395694000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    530421000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    530421000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    530421000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    530421000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86636415                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86636415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         5228                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5228                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            5                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            5                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data         7287                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7287                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7292                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7292                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    135542000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    135542000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    392317500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    392317500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    527859500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    527859500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    527859500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    527859500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86584166                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86584166                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        63546                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        63546                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        63539                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        63539                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168689092                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168689092                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168752638                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168752638                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168636843                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168636843                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168700382                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168700382                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000064                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000094                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.000094                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000079                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000079                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65433.220010                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 65433.220010                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75730.909091                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75730.909091                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72820.016474                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72820.016474                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72760.082305                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72760.082305                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72438.520653                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72388.850795                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -480,109 +480,109 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks         1010                       # number of writebacks
 system.cpu.dcache.writebacks::total              1010                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          422                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          422                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2355                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2355                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2777                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2777                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2777                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2777                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1637                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1637                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          421                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          421                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2358                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2358                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2779                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2779                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2779                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2779                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1638                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1638                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         2870                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4507                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4507                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4508                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4508                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    108637000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    108637000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    220584500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    220584500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       322000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       322000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329221500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    329221500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329543500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    329543500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109498500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    109498500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    218637500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    218637500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       238000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       238000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    328136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    328136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    328374000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    328374000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000063                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000047                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000047                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66363.469762                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66363.469762                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76858.710801                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76858.710801                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        80500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        80500                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73046.705125                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73046.705125                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73053.314121                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73053.314121                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             36911                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.852805                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            73041980                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38848                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1880.199238                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             36873                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1923.841153                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            72548906                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             38809                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1869.383545                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.852805                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939870                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939870                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1923.841153                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939376                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939376                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1936                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          274                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1488                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146200506                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146200506                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     73041980                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        73041980                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      73041980                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         73041980                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     73041980                       # number of overall hits
-system.cpu.icache.overall_hits::total        73041980                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38849                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38849                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38849                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38849                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38849                       # number of overall misses
-system.cpu.icache.overall_misses::total         38849                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    726693000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    726693000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    726693000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    726693000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    726693000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    726693000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     73080829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     73080829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     73080829                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     73080829                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     73080829                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     73080829                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000532                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000532                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000532                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000532                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000532                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000532                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18705.578007                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18705.578007                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18705.578007                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18705.578007                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18705.578007                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18705.578007                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::3          276                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1485                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         145214241                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        145214241                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     72548906                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        72548906                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      72548906                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         72548906                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     72548906                       # number of overall hits
+system.cpu.icache.overall_hits::total        72548906                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        38810                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         38810                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        38810                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          38810                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        38810                       # number of overall misses
+system.cpu.icache.overall_misses::total         38810                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    726866500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    726866500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    726866500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    726866500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    726866500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    726866500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     72587716                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     72587716                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     72587716                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     72587716                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     72587716                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     72587716                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000535                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000535                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000535                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000535                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000535                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000535                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18728.845658                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18728.845658                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,129 +591,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38849                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        38849                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        38849                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        38849                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        38849                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        38849                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    687845000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    687845000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    687845000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    687845000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    687845000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    687845000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000532                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000532                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000532                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000532                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000532                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000532                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17705.603748                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17705.603748                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17705.603748                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17705.603748                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17705.603748                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17705.603748                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38810                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        38810                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        38810                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        38810                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        38810                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        38810                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    688057500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    688057500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    688057500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    688057500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    688057500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    688057500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000535                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000535                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000535                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4199.240994                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              58015                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5647                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.273597                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4197.344986                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              57958                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5644                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.268958                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.792548                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.144889                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   678.303557                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010797                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096654                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020700                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.128151                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5647                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks   353.814355                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.200376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   678.330255                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010798                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096594                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.020701                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.128093                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5644                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           42                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1251                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172333                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           541245                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          541245                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1250                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172241                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           540762                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          540762                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks         1010                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total         1010                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        35424                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        35424                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        35388                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        35388                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          291                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          291                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        35424                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        35388                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          307                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           35731                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        35424                       # number of overall hits
+system.cpu.l2cache.demand_hits::total           35695                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        35388                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          307                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          35731                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          35695                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         2854                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         2854                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3425                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3425                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3422                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3422                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1350                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total         1350                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3425                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3422                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         4204                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7629                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3425                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          7626                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3422                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4204                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7629                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    216076500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    216076500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    257626500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    257626500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    103411500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    103411500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    257626500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    319488000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    577114500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    257626500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    319488000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    577114500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total         7626                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    214130000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    214130000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    258275500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    258275500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    104189000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    104189000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    258275500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    318319000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    576594500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    258275500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    318319000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    576594500                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks         1010                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total         1010                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2870                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        38849                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        38849                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        38810                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        38810                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1641                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total         1641                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        38849                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        38810                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4511                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        43360                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        38849                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        43321                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        38810                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4511                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        43360                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        43321                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994425                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.088162                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.088162                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.088173                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.088173                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.822669                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.822669                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088162                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088173                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.931944                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.175946                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088162                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.176035                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088173                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.931944                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.175946                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75710.056062                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75710.056062                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75219.416058                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75219.416058                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76601.111111                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76601.111111                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75219.416058                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75996.194101                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75647.463626                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75219.416058                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75996.194101                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75647.463626                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.176035                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -734,106 +734,106 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           42
 system.cpu.l2cache.overall_mshr_hits::total           44                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2854                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3423                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3420                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3420                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1308                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1308                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3423                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3420                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         4162                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3423                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7582                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3420                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7585                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    187536500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    187536500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    223262000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    223262000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     87309500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     87309500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    223262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    274846000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    498108000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    223262000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    274846000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    498108000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         7582                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    185590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    185590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    223941000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    223941000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     88101000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     88101000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    223941000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    273691000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    497632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    223941000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    273691000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    497632000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088110                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088110                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088122                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088122                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797075                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088110                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088122                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.174931                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088110                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.175019                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088122                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.174931                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65710.056062                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65710.056062                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65224.072451                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65224.072451                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66750.382263                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66750.382263                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65224.072451                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66037.001442                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65670.138431                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65224.072451                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66037.001442                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65670.138431                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.175019                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp         40489                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         40450                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        22221                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        22200                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        38849                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        38810                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq         1641                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        99690                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        99591                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10260                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            109950                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2486272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            109851                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2483776                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2839616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2837120                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        81625                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        81548                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              81625    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              81548    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          81625                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       41822500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          81548                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       41784000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      58272998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      58214498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6787458                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4731                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4728                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4731                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15170                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15170                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  485440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          4728                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15164                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15164                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  485248                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7585                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7582                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7585    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7582    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7585                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8844500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7582                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             8861000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40248250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40238250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index e201ba957..be385b04e 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -688,7 +688,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 88cf501ca..cbd037166 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,13 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 11:46:25
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 01:15:27
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x2c9dca0
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Eon, Version 1.1
@@ -15,4 +16,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.110000
-Exiting @ tick 112553814500 because target called exit()
+Exiting @ tick 112687034500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 563fc0af8..a48a8bb5c 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,17 +1,19 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:27:26
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 00:56:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x56d96c0
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-OO-style eon Time= 0.210000
-Exiting @ tick 212344043000 because target called exit()
+OO-style eon Time= 0.200000
+Exiting @ tick 201717314000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index b055586ab..892e458ed 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -156,7 +156,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -266,7 +266,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index 9d7fb2434..d5cd58d2c 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,17 +1,19 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:29:04
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 03:56:42
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x4c37d00
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-OO-style eon Time= 0.520000
-Exiting @ tick 525834342000 because target called exit()
+OO-style eon Time= 0.510000
+Exiting @ tick 517235407500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
index 7c811432f..cd33c8a8d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
index cf5d2b5cc..41d370561 100644..100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
index fadc32183..0aa9c6519 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  3 2015 14:54:12
-gem5 started Jul  3 2015 15:19:41
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:30:12
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
 
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 560939897000 because target called exit()
+Exiting @ tick 560939659000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index f751a40d2..0cd2c8d2d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.560940                       # Number of seconds simulated
-sim_ticks                                560939897000                       # Number of ticks simulated
-final_tick                               560939897000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                560939659000                       # Number of ticks simulated
+final_tick                               560939659000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 309766                       # Simulator instruction rate (inst/s)
-host_op_rate                                   309766                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              187082277                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305868                       # Number of bytes of host memory used
-host_seconds                                  2998.36                       # Real time elapsed on the host
+host_inst_rate                                 234960                       # Simulator instruction rate (inst/s)
+host_op_rate                                   234960                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              141903449                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300504                       # Number of bytes of host memory used
+host_seconds                                  3952.97                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            186880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18514240                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18701120                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       186880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          186880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            186816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18514112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18700928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       186816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          186816                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2920                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289285                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292205                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2919                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289283                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292202                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               333155                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33005746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33338902                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          333155                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             333155                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7608145                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7608145                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7608145                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              333155                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33005746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40947046                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292205                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               333041                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             33005532                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33338573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          333041                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             333041                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7608148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7608148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7608148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              333041                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            33005532                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40946722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292202                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292205                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292202                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18680832                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266304                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18701120                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18682112                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18816                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18700928                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      294                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18030                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18359                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18394                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18343                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18248                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18243                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18313                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18291                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18223                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18225                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18213                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18377                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18256                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18128                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18060                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18185                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18035                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18362                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18392                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18337                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18250                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18249                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18316                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18295                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18230                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18228                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18207                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18382                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18252                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18131                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18059                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18183                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4185                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4186                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    560939815000                       # Total gap between requests
+system.physmem.totGap                    560939577000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292205                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292202                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    291384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    291402                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       476                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,20 +144,20 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4047                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                     4049                       # What write queue length does an incoming req see
@@ -193,46 +193,44 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       103977                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      220.682651                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     142.922946                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     267.989820                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          38271     36.81%     36.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43979     42.30%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8888      8.55%     87.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          756      0.73%     88.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1408      1.35%     89.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1167      1.12%     90.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          628      0.60%     91.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          577      0.55%     92.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8303      7.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         103977                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       104019                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      220.607081                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.832345                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     268.107277                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          38319     36.84%     36.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43999     42.30%     79.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8903      8.56%     87.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          723      0.70%     88.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1372      1.32%     89.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1141      1.10%     90.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          666      0.64%     91.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          599      0.58%     92.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8297      7.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         104019                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4049                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        70.413929                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.545155                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      755.096124                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        70.696468                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.574169                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      760.359503                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023           4041     99.80%     99.80% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            2      0.05%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            3      0.07%     99.90% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            3      0.07%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            4049                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          4049                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.463571                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.442765                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.845366                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3112     76.86%     76.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                934     23.07%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.463818                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.443063                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.844207                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3110     76.81%     76.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                939     23.19%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4049                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2918754250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8391654250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459440000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9999.57                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     2923147000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8396422000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459540000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10013.93                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28749.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          33.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28763.93                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          33.31                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.61                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       33.34                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        7.61                       # Average system write bandwidth in MiByte/s
@@ -241,71 +239,71 @@ system.physmem.busUtil                           0.32                       # Da
 system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.25                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202534                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52030                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.39                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1562994.07                       # Average gap between requests
-system.physmem.pageHitRate                      70.99                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  391812120                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  213786375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1140274200                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        24.30                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202517                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52027                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.38                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.02                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1563006.47                       # Average gap between requests
+system.physmem.pageHitRate                      70.98                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  392311080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  214058625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1140422400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy            36637679520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           109227211875                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           240749028000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             388576230570                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.726692                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   399826633250                       # Time in different power states
+system.physmem_0.actBackEnergy           109190821365                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           240780947250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             388572678720                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.720364                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   399879041250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     18730920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    142379745750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    142327335000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  394193520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  215085750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136148000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215524800                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  394019640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  214990875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136187000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy            36637679520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           109501586505                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           240508346250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             388608564345                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              692.784339                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   399420466000                       # Time in different power states
+system.physmem_1.actBackEnergy           109681250220                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           240350746500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             388630405035                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              692.823275                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   399158044000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     18730920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    142786637000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    143048821000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               125749081                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          81144339                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12157133                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            103971313                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83513402                       # Number of BTB hits
+system.cpu.branchPred.lookups               125747730                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          81143399                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12156451                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            103980487                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83512673                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.323504                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18691072                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               9449                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.315716                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18691015                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               9451                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    237538494                       # DTB read hits
-system.cpu.dtb.read_misses                     198467                       # DTB read misses
+system.cpu.dtb.read_hits                    237537770                       # DTB read hits
+system.cpu.dtb.read_misses                     198464                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                237736961                       # DTB read accesses
-system.cpu.dtb.write_hits                    98305022                       # DTB write hits
-system.cpu.dtb.write_misses                      7216                       # DTB write misses
+system.cpu.dtb.read_accesses                237736234                       # DTB read accesses
+system.cpu.dtb.write_hits                    98304947                       # DTB write hits
+system.cpu.dtb.write_misses                      7177                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312238                       # DTB write accesses
-system.cpu.dtb.data_hits                    335843516                       # DTB hits
-system.cpu.dtb.data_misses                     205683                       # DTB misses
+system.cpu.dtb.write_accesses                98312124                       # DTB write accesses
+system.cpu.dtb.data_hits                    335842717                       # DTB hits
+system.cpu.dtb.data_misses                     205641                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336049199                       # DTB accesses
-system.cpu.itb.fetch_hits                   316987000                       # ITB hits
+system.cpu.dtb.data_accesses                336048358                       # DTB accesses
+system.cpu.itb.fetch_hits                   316984864                       # ITB hits
 system.cpu.itb.fetch_misses                       120                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               316987120                       # ITB accesses
+system.cpu.itb.fetch_accesses               316984984                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -319,67 +317,67 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1121879794                       # number of cpu cycles simulated
+system.cpu.numCycles                       1121879318                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      30863449                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      30861365                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                               1.207895                       # CPI: cycles per instruction
 system.cpu.ipc                               0.827887                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1059714780                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        62165014                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            776532                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.723334                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322867251                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            780628                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            413.599373                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         899878500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.723334                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999200                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999200                       # Average percentage of cache occupancy
+system.cpu.tickCycles                      1059707231                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        62172087                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            776530                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.727909                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           322866545                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780626                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            413.599528                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         898816500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.727909                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999201                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999201                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          952                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          951                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         1242                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1642                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         648213288                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        648213288                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    224703201                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       224703201                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     98164050                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164050                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     322867251                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        322867251                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    322867251                       # number of overall hits
-system.cpu.dcache.overall_hits::total       322867251                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         648211884                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        648211884                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    224702500                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       224702500                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98164045                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164045                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     322866545                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        322866545                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    322866545                       # number of overall hits
+system.cpu.dcache.overall_hits::total       322866545                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       711929                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        711929                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137150                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137150                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       849079                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         849079                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       849079                       # number of overall misses
-system.cpu.dcache.overall_misses::total        849079                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24888612000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24888612000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9943107500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9943107500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34831719500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34831719500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34831719500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34831719500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    225415130                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    225415130                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       137155                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137155                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       849084                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         849084                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       849084                       # number of overall misses
+system.cpu.dcache.overall_misses::total        849084                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24888766500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24888766500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9955853000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9955853000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34844619500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34844619500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34844619500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34844619500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    225414429                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    225414429                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    323716330                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    323716330                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    323716330                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323716330                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    323715629                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    323715629                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    323715629                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    323715629                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003158                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003158                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
@@ -388,14 +386,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002623
 system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002623                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.401850                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.401850                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72498.049581                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72498.049581                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41022.943095                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41022.943095                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41022.943095                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41022.943095                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.618866                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.618866                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72588.334366                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72588.334366                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41037.894366                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41037.894366                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41037.894366                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41037.894366                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -404,32 +402,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88848                       # number of writebacks
-system.cpu.dcache.writebacks::total             88848                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          312                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          312                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68139                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68139                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68451                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68451                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68451                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68451                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711617                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       711617                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks        88852                       # number of writebacks
+system.cpu.dcache.writebacks::total             88852                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          314                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          314                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68144                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68144                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        68458                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68458                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        68458                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68458                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711615                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        69011                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       780628                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       780628                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       780628                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       780628                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24170012500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24170012500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4987370000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4987370000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29157382500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29157382500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29157382500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29157382500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       780626                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780626                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       780626                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780626                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24170053000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24170053000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4993475000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4993475000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29163528000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29163528000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29163528000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29163528000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003157                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
@@ -438,69 +436,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002411
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002411                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33964.917224                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33964.917224                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72269.203460                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72269.203460                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37351.187121                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37351.187121                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37351.187121                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37351.187121                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33965.069595                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33965.069595                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72357.667618                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72357.667618                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37359.155345                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37359.155345                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37359.155345                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37359.155345                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             10610                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1686.330189                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           316974647                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12352                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25661.807562                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             10565                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1685.376392                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           316972557                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12306                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25757.561921                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1686.330189                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.823403                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.823403                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1685.376392                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.822938                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.822938                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1741                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         633986352                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        633986352                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    316974647                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       316974647                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     316974647                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        316974647                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    316974647                       # number of overall hits
-system.cpu.icache.overall_hits::total       316974647                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12353                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12353                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12353                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12353                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12353                       # number of overall misses
-system.cpu.icache.overall_misses::total         12353                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    352286000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    352286000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    352286000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    352286000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    352286000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    352286000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    316987000                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    316987000                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    316987000                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    316987000                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    316987000                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    316987000                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1571                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         633982034                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        633982034                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    316972557                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       316972557                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     316972557                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        316972557                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    316972557                       # number of overall hits
+system.cpu.icache.overall_hits::total       316972557                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12307                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12307                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12307                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12307                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12307                       # number of overall misses
+system.cpu.icache.overall_misses::total         12307                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    350414000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    350414000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    350414000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    350414000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    350414000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    350414000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    316984864                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    316984864                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    316984864                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    316984864                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    316984864                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    316984864                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28518.254675                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28518.254675                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28518.254675                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28518.254675                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28518.254675                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28518.254675                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28472.739092                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28472.739092                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28472.739092                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28472.739092                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28472.739092                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28472.739092                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -509,129 +507,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12353                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12353                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12353                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12353                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12353                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12353                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    339934000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    339934000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    339934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    339934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    339934000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    339934000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12307                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12307                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12307                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12307                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12307                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12307                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    338108000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    338108000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    338108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    338108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    338108000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    338108000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27518.335627                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27518.335627                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27518.335627                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27518.335627                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27518.335627                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27518.335627                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27472.820346                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27472.820346                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27472.820346                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 27472.820346                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27472.820346                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 27472.820346                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259426                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32593.023927                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1218366                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292162                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.170173                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           259423                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32592.990901                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1218275                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292159                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.169904                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2589.520333                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    84.221668                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.281926                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.079026                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002570                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.913064                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994660                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2589.705025                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    83.650991                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.634886                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.079032                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002553                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.913075                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994659                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          272                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2658                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29475                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2659                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29473                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13002157                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13002157                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        88848                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        88848                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         13001394                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13001394                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks        88852                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        88852                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9432                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         9432                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9387                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         9387                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data       488977                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total       488977                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         9432                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         9387                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       491343                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          500775                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         9432                       # number of overall hits
+system.cpu.l2cache.demand_hits::total          500730                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         9387                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data       491343                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         500775                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         500730                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66645                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66645                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2921                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2921                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222640                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222640                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2921                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       289285                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        292206                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2921                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       289285                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       292206                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4858983000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4858983000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    222370000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    222370000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17968315500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17968315500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    222370000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22827298500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23049668500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    222370000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22827298500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23049668500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        88848                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        88848                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2920                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2920                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222638                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222638                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2920                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       289283                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        292203                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2920                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       289283                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       292203                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4865088000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4865088000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    221085500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    221085500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17968357500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  17968357500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    221085500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  22833445500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  23054531000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    221085500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  22833445500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  23054531000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks        88852                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        88852                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69011                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69011                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12353                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        12353                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       711617                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       711617                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        12353                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       780628                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       792981                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        12353                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       780628                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       792981                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12307                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        12307                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       711615                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       711615                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        12307                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       780626                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       792933                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        12307                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       780626                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       792933                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965716                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.965716                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.236461                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.236461                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312865                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312865                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.236461                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.370580                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.368491                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.236461                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370580                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.368491                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.440243                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.440243                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76128.038343                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76128.038343                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80705.693047                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80705.693047                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76128.038343                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78909.374838                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78881.571563                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76128.038343                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78909.374838                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78881.571563                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.237263                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.237263                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312863                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312863                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.237263                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370578                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.368509                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.237263                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370578                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.368509                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73000.045015                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73000.045015                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75714.212329                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75714.212329                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80706.606689                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80706.606689                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75714.212329                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78931.169478                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78899.022255                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75714.212329                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78931.169478                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78899.022255                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -642,114 +640,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          453                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          453                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          452                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          452                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66645                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2921                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2921                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222640                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222640                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2921                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289285                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292206                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2921                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289285                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292206                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4192533000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4192533000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    193170000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    193170000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15741915500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15741915500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193170000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19934448500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20127618500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193170000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19934448500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20127618500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2920                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2920                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222638                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222638                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2920                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289283                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292203                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2920                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289283                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292203                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4198638000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4198638000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    191895500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    191895500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15741977500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15741977500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    191895500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19940615500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20132511000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    191895500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19940615500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20132511000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.236461                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.236461                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312865                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312865                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.236461                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370580                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.368491                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.236461                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370580                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.368491                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62908.440243                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62908.440243                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66131.461828                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66131.461828                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70705.693047                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70705.693047                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66131.461828                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68909.374838                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68881.605785                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66131.461828                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68909.374838                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68881.605785                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.237263                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.237263                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312863                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312863                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.237263                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370578                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.368509                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.237263                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370578                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.368509                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63000.045015                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63000.045015                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65717.636986                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65717.636986                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70706.606689                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70706.606689                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65717.636986                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68931.169478                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68899.056478                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        723969                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155531                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       891037                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155535                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       890983                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        12353                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       711617                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35315                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337788                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2373103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       790528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55646464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56436992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259426                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1839549                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.141027                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.348049                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12307                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       711615                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35178                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337782                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2372960                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       787584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55646592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56434176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259423                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1839451                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.141033                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.348056                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1580123     85.90%     85.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             259426     14.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1580028     85.90%     85.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             259423     14.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1839549                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      878909500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1839451                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      878866000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18528000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      18459000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1170942000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1170939000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225560                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225557                       # Transaction distribution
 system.membus.trans_dist::Writeback             66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191116                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191114                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225560                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842209                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842209                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22968832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22968832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225557                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842201                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842201                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22968640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22968640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            550004                       # Request fanout histogram
+system.membus.snoop_fanout::samples            549999                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  550004    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  549999    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              550004                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           918579000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              549999                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           918564500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1556120750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1556125250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 3af7f6d2b..0cac95bfa 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -497,7 +497,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -546,7 +546,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -609,7 +609,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 408e44e03..c3e095b5a 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:48:44
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 20:54:31
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -648,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 279668927000 because target called exit()
+Exiting @ tick 276406029500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 7d418bd2e..4ab8a79d0 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.279557                       # Number of seconds simulated
-sim_ticks                                279556845500                       # Number of ticks simulated
-final_tick                               279556845500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.276406                       # Number of seconds simulated
+sim_ticks                                276406029500                       # Number of ticks simulated
+final_tick                               276406029500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 180071                       # Simulator instruction rate (inst/s)
-host_op_rate                                   180071                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59759118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307148                       # Number of bytes of host memory used
-host_seconds                                  4678.06                       # Real time elapsed on the host
+host_inst_rate                                 130885                       # Simulator instruction rate (inst/s)
+host_op_rate                                   130885                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42946592                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301528                       # Number of bytes of host memory used
+host_seconds                                  6436.04                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            176320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18520448                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18696768                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       176320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          176320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            173952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18519360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18693312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       173952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          173952                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2755                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289382                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292137                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2718                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289365                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292083                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               630713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             66249310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                66880022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          630713                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             630713                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          15265990                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               15265990                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          15265990                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              630713                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            66249310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               82146012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292137                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               629335                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             67000564                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                67629900                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          629335                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             629335                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          15440011                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               15440011                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          15440011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              629335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            67000564                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               83069910                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292083                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292137                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292083                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18678144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18624                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4265920                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18696768                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18672064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266752                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18693312                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      291                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18015                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18332                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18407                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18336                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18249                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18230                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18323                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18299                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18010                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18319                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18376                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18330                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18231                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18221                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18322                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18297                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               18226                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18222                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18209                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18393                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18246                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18127                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18048                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18184                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18218                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18207                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18389                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18249                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18121                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18052                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18183                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4180                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4149                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    279556756000                       # Total gap between requests
+system.physmem.totGap                    276405940000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292137                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292083                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,13 +97,13 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    215113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47042                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29481                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    216501                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     47240                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     27808                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       172                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      908                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      907                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::16                      908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -193,120 +193,121 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        99332                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      230.959771                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     149.026626                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     277.596004                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          34426     34.66%     34.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        42079     42.36%     77.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        10100     10.17%     87.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          831      0.84%     88.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1119      1.13%     89.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          640      0.64%     89.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          198      0.20%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1366      1.38%     91.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8573      8.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          99332                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4052                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        69.011846                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.507282                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      732.804018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4044     99.80%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            5      0.12%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        99437                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      230.668262                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     148.414135                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     279.665008                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          34391     34.59%     34.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        42842     43.08%     77.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        10220     10.28%     87.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          417      0.42%     88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          400      0.40%     88.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          621      0.62%     89.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          466      0.47%     89.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1450      1.46%     91.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8630      8.68%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          99437                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4053                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        71.663212                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.607328                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      761.755251                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4044     99.78%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4052                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4052                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.449901                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.429330                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.841533                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3145     77.62%     77.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                903     22.29%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  2      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4052                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3589265250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9061377750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459230000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12298.49                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4053                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4053                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.449050                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.428679                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.836709                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3145     77.60%     77.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                905     22.33%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  2      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4053                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3647206250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9117537500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1458755000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12501.09                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31048.49                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          66.81                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          15.26                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       66.88                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       15.27                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31251.09                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          67.55                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          15.44                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       67.63                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       15.44                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.64                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.52                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.65                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.53                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.19                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     207190                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51966                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   70.99                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.93                       # Row buffer hit rate for writes
-system.physmem.avgGap                       779100.26                       # Average gap between requests
-system.physmem.pageHitRate                      72.28                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  374756760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  204480375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1139564400                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        24.13                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     206989                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51984                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   70.95                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.96                       # Row buffer hit rate for writes
+system.physmem.avgGap                       770435.16                       # Average gap between requests
+system.physmem.pageHitRate                      72.25                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  373947840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  204039000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1139408400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            18258829680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80335161315                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            97260556500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             197789787510                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              707.529215                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   161282435500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      9334780000                       # Time in different power states
+system.physmem_0.refreshEnergy            18053371440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80174383695                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            95514202500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             195675791355                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              707.933114                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   158383013500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      9229740000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    108932951500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    108791696000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  375943680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  205128000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1135750200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215485920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            18258829680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80056140615                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            97505311500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             197752589595                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              707.396151                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   161684152500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      9334780000                       # Time in different power states
+system.physmem_1.actEnergy                  377742960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  206109750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1135890600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            18053371440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80329865445                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            95377815000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             195696365355                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              708.007549                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   158148138750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      9229740000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    108531075000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    109026483750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               192642813                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         125666016                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11886398                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            146763457                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               126951211                       # Number of BTB hits
+system.cpu.branchPred.lookups               192576076                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         126054565                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          11561227                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            137875170                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               126274438                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             86.500559                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                29013974                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                143                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             91.586062                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                28678363                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                136                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    244534581                       # DTB read hits
-system.cpu.dtb.read_misses                     309538                       # DTB read misses
+system.cpu.dtb.read_hits                    242441387                       # DTB read hits
+system.cpu.dtb.read_misses                     312131                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                244844119                       # DTB read accesses
-system.cpu.dtb.write_hits                   135677576                       # DTB write hits
-system.cpu.dtb.write_misses                     31395                       # DTB write misses
+system.cpu.dtb.read_accesses                242753518                       # DTB read accesses
+system.cpu.dtb.write_hits                   135445935                       # DTB write hits
+system.cpu.dtb.write_misses                     31631                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               135708971                       # DTB write accesses
-system.cpu.dtb.data_hits                    380212157                       # DTB hits
-system.cpu.dtb.data_misses                     340933                       # DTB misses
+system.cpu.dtb.write_accesses               135477566                       # DTB write accesses
+system.cpu.dtb.data_hits                    377887322                       # DTB hits
+system.cpu.dtb.data_misses                     343762                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                380553090                       # DTB accesses
-system.cpu.itb.fetch_hits                   197116758                       # ITB hits
-system.cpu.itb.fetch_misses                       277                       # ITB misses
+system.cpu.dtb.data_accesses                378231084                       # DTB accesses
+system.cpu.itb.fetch_hits                   194828154                       # ITB hits
+system.cpu.itb.fetch_misses                       242                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               197117035                       # ITB accesses
+system.cpu.itb.fetch_accesses               194828396                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -320,238 +321,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                        559113692                       # number of cpu cycles simulated
+system.cpu.numCycles                        552812060                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          202267120                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1648589560                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   192642813                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          155965185                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     344477338                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                24241354                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  146                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6562                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 197116758                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               7079440                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          558871871                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.949852                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.174628                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          198850471                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1637321626                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   192576076                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          154952801                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     341917067                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                23591046                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          6993                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 194828154                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               7885913                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          552570202                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.963102                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.176487                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                239606568     42.87%     42.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30232310      5.41%     48.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 22062681      3.95%     52.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 36416175      6.52%     58.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 68096392     12.18%     70.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 21641580      3.87%     74.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 19299985      3.45%     78.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3539455      0.63%     78.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                117976725     21.11%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                236054473     42.72%     42.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29638362      5.36%     48.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 21702458      3.93%     52.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 35773228      6.47%     58.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 67707960     12.25%     70.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 21595876      3.91%     74.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 19328628      3.50%     78.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3978060      0.72%     78.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                116791157     21.14%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            558871871                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.344550                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.948577                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                168941255                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              91534254                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 273571884                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              12710570                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               12113908                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             15306458                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  6991                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1583914254                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 25227                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               12113908                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                176800339                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                61738556                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14140                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 278402636                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29802292                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1538072104                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  9577                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2573672                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               20322038                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7208635                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1027250775                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1768837330                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1729119220                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          39718109                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            552570202                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.348357                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.961805                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                166802287                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              90542864                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 271199395                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              12236841                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               11788815                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             15468328                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  6932                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1567838176                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 24969                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               11788815                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                173688859                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                60716441                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13717                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 276533617                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              29828753                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1529250735                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  8190                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2401406                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               20516503                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7198838                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1021411513                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1760089033                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1720202399                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          39886633                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                388283617                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1370                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             93                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9395851                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            372336921                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           175495034                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          40680070                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11286315                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1304559063                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  83                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1015639240                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           8789930                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       462177116                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    427685030                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     558871871                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.817302                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.903889                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                382444355                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1364                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             84                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   9081858                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            369185264                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           173801333                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          40211283                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11128775                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1296786218                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  72                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1011356527                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           8787388                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       454404260                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    422537101                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             35                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     552570202                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.830277                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.913640                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           199951896     35.78%     35.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            92994240     16.64%     52.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            91399550     16.35%     68.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            59708328     10.68%     79.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            56828177     10.17%     89.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            29755879      5.32%     94.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            17031836      3.05%     98.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             7177923      1.28%     99.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4024042      0.72%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           197270443     35.70%     35.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            90785192     16.43%     52.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            90547416     16.39%     68.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            58763251     10.63%     79.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            57064914     10.33%     89.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            29634790      5.36%     94.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            16885134      3.06%     97.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             7510156      1.36%     99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4108906      0.74%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       558871871                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       552570202                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2464205     10.45%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               15633751     66.29%     76.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5485030     23.26%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2519726     10.56%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               15983640     67.00%     77.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5352814     22.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             579358124     57.04%     57.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7924      0.00%     57.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            13180764      1.30%     58.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             3826542      0.38%     58.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             3339800      0.33%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            276992447     27.27%     86.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           138932359     13.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             577739239     57.13%     57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7929      0.00%     57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13232477      1.31%     58.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826542      0.38%     58.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             3339799      0.33%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            274563645     27.15%     86.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           138645616     13.71%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1015639240                       # Type of FU issued
-system.cpu.iq.rate                           1.816516                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23582986                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023220                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2551718253                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1725674688                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    939925074                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            70805014                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           41106869                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     34423614                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1002860612                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                36360338                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         50469534                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1011356527                       # Type of FU issued
+system.cpu.iq.rate                           1.829476                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    23856180                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023588                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2536915249                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1709850818                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    936642710                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            71011575                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           41384719                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34526976                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              998747828                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                36463603                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         49725855                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    134826324                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses      1160001                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        45767                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     77193834                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    131674667                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses      1209013                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        45363                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     75500133                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2684                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4171                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2715                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4018                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               12113908                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                60768232                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                187260                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1479124792                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             20793                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             372336921                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            175495034                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 81                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  15841                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                182755                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          45767                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       11880363                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        16467                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11896830                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             976089984                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             244844291                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          39549256                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               11788815                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                59738270                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                197040                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1470367053                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             17961                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             369185264                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            173801333                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 72                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  15881                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                192528                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          45363                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       11555967                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        14465                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11570432                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             973002630                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             242753693                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          38353897                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     174565646                       # number of nop insts executed
-system.cpu.iew.exec_refs                    380553668                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                129052167                       # Number of branches executed
-system.cpu.iew.exec_stores                  135709377                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.745781                       # Inst execution rate
-system.cpu.iew.wb_sent                      974867255                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     974348688                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 556190036                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 832343662                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     173580763                       # number of nop insts executed
+system.cpu.iew.exec_refs                    378231547                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                128483828                       # Number of branches executed
+system.cpu.iew.exec_stores                  135477854                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.760097                       # Inst execution rate
+system.cpu.iew.wb_sent                      971735885                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     971169686                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 554962956                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 830927766                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.742666                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.668222                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.756781                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.667884                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       543293982                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       534548617                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          11879630                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    486147412                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.910095                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.597279                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          11554520                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    481206030                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.929709                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.612045                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    208054375     42.80%     42.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    102342395     21.05%     63.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     51700065     10.63%     74.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     25702081      5.29%     79.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     21547094      4.43%     84.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      9129205      1.88%     86.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10401484      2.14%     88.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6670149      1.37%     89.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     50600564     10.41%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    204042568     42.40%     42.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    101511322     21.10%     63.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     52351761     10.88%     74.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     25424969      5.28%     79.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     20905527      4.34%     84.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8991227      1.87%     85.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10032438      2.08%     87.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6244738      1.30%     89.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     51701480     10.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    486147412                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    481206030                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
 system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -597,335 +598,345 @@ system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              50600564                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1904807320                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3016488956                       # The number of ROB writes
-system.cpu.timesIdled                            3196                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          241821                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              51701480                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1890019657                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2997637733                       # The number of ROB writes
+system.cpu.timesIdled                            3185                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          241858                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
 system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.663729                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.663729                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.506638                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.506638                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1237184723                       # number of integer regfile reads
-system.cpu.int_regfile_writes               705784215                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  36689750                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 24410793                       # number of floating regfile writes
+system.cpu.cpi                               0.656249                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.656249                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.523813                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.523813                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1234257247                       # number of integer regfile reads
+system.cpu.int_regfile_writes               703449538                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36844878                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24462480                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            777216                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.910211                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           289913128                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            781312                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            371.059357                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         371553500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.910211                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999246                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999246                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            777154                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.899235                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           288564425                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            781250                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            369.362464                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         369553500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.899235                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999243                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999243                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          967                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2498                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          253                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2490                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          256                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         585500596                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        585500596                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    192503314                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       192503314                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     97409790                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       97409790                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           24                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           24                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     289913104                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        289913104                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    289913104                       # number of overall hits
-system.cpu.dcache.overall_hits::total       289913104                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1555104                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1555104                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       891410                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       891410                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2446514                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2446514                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2446514                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2446514                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  83796204000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  83796204000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  61715896841                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  61715896841                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145512100841                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145512100841                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145512100841                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145512100841                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    194058418                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    194058418                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         582801760                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        582801760                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    191156368                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       191156368                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     97408043                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       97408043                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           14                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           14                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     288564411                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        288564411                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    288564411                       # number of overall hits
+system.cpu.dcache.overall_hits::total       288564411                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1552672                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1552672                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       893157                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       893157                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2445829                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2445829                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2445829                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2445829                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  83271101000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  83271101000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  62352545333                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  62352545333                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        82500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        82500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145623646333                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145623646333                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145623646333                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145623646333                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    192709040                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    192709040                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           24                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           24                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    292359618                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    292359618                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    292359618                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    292359618                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008014                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.008014                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009068                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009068                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008368                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008368                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008368                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008368                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53884.630224                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53884.630224                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69234.018960                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69234.018960                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59477.321953                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59477.321953                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59477.321953                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59477.321953                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        22265                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        67906                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               347                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             515                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    64.164265                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   131.856311                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    291010240                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    291010240                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    291010240                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    291010240                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008057                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008057                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009086                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009086                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.066667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.066667                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008405                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008405                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008405                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008405                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53630.838323                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53630.838323                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69811.405311                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69811.405311                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        82500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        82500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59539.586101                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59539.586101                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59539.586101                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59539.586101                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        22515                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        72899                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               341                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             517                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.026393                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   141.003868                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88850                       # number of writebacks
-system.cpu.dcache.writebacks::total             88850                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842619                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       842619                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       822583                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       822583                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1665202                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1665202                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1665202                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1665202                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712485                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712485                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68827                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        68827                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       781312                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       781312                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       781312                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       781312                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24145312000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24145312000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5651970498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5651970498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29797282498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29797282498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29797282498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29797282498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003671                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003671                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks        88880                       # number of writebacks
+system.cpu.dcache.writebacks::total             88880                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       840227                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       840227                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       824352                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       824352                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1664579                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1664579                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1664579                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1664579                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712445                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712445                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68805                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        68805                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       781250                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       781250                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       781250                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       781250                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24193547500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24193547500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5688085497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5688085497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29881632997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29881632997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29881632997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29881632997                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003697                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003697                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000700                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002672                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002672                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002672                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002672                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33888.870643                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33888.870643                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82118.507243                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82118.507243                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38137.495006                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 38137.495006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38137.495006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 38137.495006                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002685                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002685                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33958.477497                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33958.477497                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82669.653325                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82669.653325                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38248.490236                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38248.490236                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38248.490236                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38248.490236                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              4695                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1651.888032                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           197108400                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6404                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          30778.950656                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4598                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1641.391736                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           194819915                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6300                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          30923.796032                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1651.888032                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.806586                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.806586                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1709                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           75                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1641.391736                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801461                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801461                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1702                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1553                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.834473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         394239920                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        394239920                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    197108400                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       197108400                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     197108400                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        197108400                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    197108400                       # number of overall hits
-system.cpu.icache.overall_hits::total       197108400                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8358                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8358                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8358                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8358                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8358                       # number of overall misses
-system.cpu.icache.overall_misses::total          8358                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    354830499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    354830499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    354830499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    354830499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    354830499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    354830499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    197116758                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    197116758                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    197116758                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    197116758                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    197116758                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    197116758                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1537                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.831055                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         389662608                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        389662608                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    194819915                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       194819915                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     194819915                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        194819915                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    194819915                       # number of overall hits
+system.cpu.icache.overall_hits::total       194819915                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8239                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8239                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8239                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8239                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8239                       # number of overall misses
+system.cpu.icache.overall_misses::total          8239                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    351244499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    351244499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    351244499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    351244499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    351244499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    351244499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    194828154                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    194828154                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    194828154                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    194828154                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    194828154                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    194828154                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42453.996052                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42453.996052                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42453.996052                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42453.996052                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42453.996052                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42453.996052                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          620                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42631.933366                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42631.933366                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42631.933366                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42631.933366                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42631.933366                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42631.933366                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          510                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    56.363636                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    46.363636                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1953                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1953                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1953                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1953                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1953                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1953                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6405                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6405                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6405                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6405                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6405                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6405                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    268250499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    268250499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    268250499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    268250499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    268250499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    268250499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1938                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1938                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1938                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1938                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1938                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1938                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6301                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6301                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6301                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6301                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6301                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6301                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    261165999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    261165999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    261165999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    261165999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    261165999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    261165999                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41881.420609                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41881.420609                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41881.420609                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41881.420609                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41881.420609                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41881.420609                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41448.341374                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41448.341374                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41448.341374                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 41448.341374                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41448.341374                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41448.341374                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259359                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32631.025486                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1208176                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292097                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.136215                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           259305                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32630.134515                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1207948                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292043                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.136199                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2513.776004                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    69.329948                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30047.919535                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.076714                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002116                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.916990                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995820                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2512.609153                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    65.430826                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30052.094536                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.076679                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001997                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.917117                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995793                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32738                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          160                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          531                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          533                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5296                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26549                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26539                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999084                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12917948                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12917948                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        88850                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        88850                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         2199                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         2199                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3649                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         3649                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489731                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       489731                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3649                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       491930                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          495579                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3649                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       491930                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         495579                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66628                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66628                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2756                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2756                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222754                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222754                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2756                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       289382                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        292138                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2756                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       289382                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       292138                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5525354500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5525354500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    220303000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    220303000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17928202500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17928202500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    220303000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  23453557000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23673860000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    220303000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  23453557000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23673860000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        88850                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        88850                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        68827                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        68827                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6405                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         6405                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712485                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       712485                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6405                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       781312                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       787717                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6405                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       781312                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       787717                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.968050                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.968050                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.430289                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.430289                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312644                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312644                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.430289                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.370380                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.370867                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.430289                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370380                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.370867                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82928.415981                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82928.415981                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79935.776488                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79935.776488                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80484.312291                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80484.312291                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79935.776488                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81047.048538                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81036.564911                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79935.776488                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81047.048538                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81036.564911                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses         12915272                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12915272                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks        88880                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        88880                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         2178                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         2178                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3582                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         3582                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489707                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       489707                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3582                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       491885                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          495467                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3582                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       491885                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         495467                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66627                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66627                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2719                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2719                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222738                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222738                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2719                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       289365                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        292084                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2719                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       289365                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       292084                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5561753000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5561753000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    214081500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    214081500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17977592000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  17977592000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    214081500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  23539345000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  23753426500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    214081500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  23539345000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  23753426500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks        88880                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        88880                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        68805                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        68805                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6301                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         6301                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712445                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       712445                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6301                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       781250                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       787551                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6301                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       781250                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       787551                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.968345                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.968345                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.431519                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.431519                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312639                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312639                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.431519                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370387                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.370876                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.431519                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370387                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.370876                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83475.963198                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83475.963198                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78735.380655                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78735.380655                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80711.831838                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80711.831838                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78735.380655                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81348.279854                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81323.956465                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78735.380655                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81348.279854                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81323.956465                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -936,114 +947,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          405                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          405                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66628                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66628                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2756                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2756                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222754                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222754                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2756                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289382                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2756                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289382                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292138                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4859074500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4859074500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    192753000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    192753000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15700662500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15700662500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    192753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20559737000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20752490000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    192753000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20559737000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20752490000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          394                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          394                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2719                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2719                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222738                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222738                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2719                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289365                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292084                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2719                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289365                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292084                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4895483000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4895483000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    186901500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    186901500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15750212000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15750212000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    186901500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20645695000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20832596500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    186901500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20645695000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20832596500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.968050                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.968050                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.430289                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.430289                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312644                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312644                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.430289                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370380                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.370867                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.430289                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370380                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.370867                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72928.415981                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72928.415981                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69939.404935                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69939.404935                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70484.312291                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70484.312291                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69939.404935                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71047.048538                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71036.599142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69939.404935                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71047.048538                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71036.599142                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.968345                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.968345                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.431519                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312639                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312639                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370387                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.370876                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370387                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.370876                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73475.963198                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73475.963198                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68739.058477                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70711.831838                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70711.831838                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71348.279854                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71323.990701                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        718889                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155533                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       885737                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        68827                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        68827                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         6405                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712485                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17504                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339840                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2357344                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       409856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55690368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56100224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259359                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1828987                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        718745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155563                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       885494                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        68805                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        68805                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6301                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712445                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17199                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339654                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2356853                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       403200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55688320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56091520                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259305                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1828608                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        1.141805                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.348850                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1569628     85.82%     85.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             259359     14.18%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1569303     85.82%     85.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             259305     14.18%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1828987                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      873664000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1828608                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      873531500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       9606000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       9450000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1171968000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1171875499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225509                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225456                       # Transaction distribution
 system.membus.trans_dist::Writeback             66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191067                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66628                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66628                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225509                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842024                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842024                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22964480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22964480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::CleanEvict           191030                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66627                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66627                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        225456                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       841879                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 841879                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22961024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22961024                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            549887                       # Request fanout histogram
+system.membus.snoop_fanout::samples            549796                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  549887    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  549796    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              549887                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           853984000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              549796                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           880960000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1551628500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1551840500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 588b633d1..82e107e36 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -118,7 +118,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -167,7 +167,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
index c3a686fba..bd7f67190 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -759,7 +759,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
index b094041b5..d77f0dbd5 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 03:24:21
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x2ccb000
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
@@ -648,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 545056655500 because target called exit()
+Exiting @ tick 542257602500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index cc0a8b561..53f1e9393 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.541068                       # Number of seconds simulated
-sim_ticks                                541067717500                       # Number of ticks simulated
-final_tick                               541067717500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.542258                       # Number of seconds simulated
+sim_ticks                                542257602500                       # Number of ticks simulated
+final_tick                               542257602500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 180313                       # Simulator instruction rate (inst/s)
-host_op_rate                                   221989                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              152283805                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322972                       # Number of bytes of host memory used
-host_seconds                                  3553.02                       # Real time elapsed on the host
+host_inst_rate                                 121737                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149875                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              103039759                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317376                       # Number of bytes of host memory used
+host_seconds                                  5262.61                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            164736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18470272                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18635008                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       164736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          164736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            164672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18470528                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18635200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       164672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          164672                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2574                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288598                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291172                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2573                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288602                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291175                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               304465                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             34136710                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34441175                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          304465                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             304465                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7818378                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7818378                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7818378                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              304465                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            34136710                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42259553                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291172                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               303679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             34062276                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34365954                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          303679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             303679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7801222                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7801222                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7801222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              303679                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            34062276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42167176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291175                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      291172                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      291175                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18613824                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21184                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228224                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18635008                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18614208                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20992                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228480                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18635200                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      331                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      328                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18127                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18214                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18173                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18274                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18402                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18180                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17989                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18022                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18061                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18102                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18198                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18134                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18219                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18172                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18271                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18399                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18176                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17991                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18028                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18057                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18104                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18195                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              18215                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18265                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18268                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              18078                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18259                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18258                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4222                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4092                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4097                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    541067624000                       # Total gap between requests
+system.physmem.totGap                    542257509000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291172                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291175                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290452                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       372                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290456                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       377                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4015                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
@@ -158,9 +158,9 @@ system.physmem.wrQLenPdf::25                     4018                       # Wh
 system.physmem.wrQLenPdf::26                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
@@ -193,94 +193,96 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       110882                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      205.996862                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.129754                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     256.860056                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45611     41.13%     41.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43911     39.60%     80.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9208      8.30%     89.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1504      1.36%     90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          772      0.70%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          428      0.39%     91.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          846      0.76%     92.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          594      0.54%     92.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8008      7.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         110882                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       111041                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      205.695554                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.912944                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.637901                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          45880     41.32%     41.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43577     39.24%     80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9434      8.50%     89.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1633      1.47%     90.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          691      0.62%     91.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          667      0.60%     91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          515      0.46%     92.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          550      0.50%     92.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8094      7.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         111041                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.509335                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.234035                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.719748                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.509833                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.246439                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.588678                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.446602                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.426400                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.833021                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3120     77.67%     77.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                897     22.33%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.447598                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.427351                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.833980                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3118     77.62%     77.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     77.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                897     22.33%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3065169000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8518437750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454205000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10538.99                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     2871354000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8324735250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454235000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9872.39                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29288.99                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          34.40                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.81                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       34.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.82                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28622.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          34.33                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           7.80                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       34.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        7.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        28.63                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194425                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51597                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   66.85                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.06                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1514450.20                       # Average gap between requests
-system.physmem.pageHitRate                      68.93                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  420041160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  229189125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1135976400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            35339834400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           108869403780                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           229140586500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             375350562645                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              693.723181                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   380482098250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18067400000                       # Time in different power states
+system.physmem.avgWrQLen                        26.15                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     194229                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51633                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   66.78                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1517767.95                       # Average gap between requests
+system.physmem.pageHitRate                      68.88                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  420124320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  229234500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1135836000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215518320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            35417135520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           107502461415                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           231049769250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             375970079325                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              693.351550                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   383670371250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18106920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    142518050750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    140473012000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  418226760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  228199125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1132497600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212576400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            35339834400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           107776907010                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           230098917000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             375207158295                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              693.458141                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   382081982750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18067400000                       # Time in different power states
+system.physmem_1.actEnergy                  419247360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  228756000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1132271400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212615280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            35417135520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           108055650690                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           230564511000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             376030187250                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              693.462409                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   382864555750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18106920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    140917403500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    141281958750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               157565509                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         107229273                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12892751                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             98103751                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                81778311                       # Number of BTB hits
+system.cpu.branchPred.lookups               154805772                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         105138293                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12875884                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90693369                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83089320                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.359005                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19318729                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1315                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             91.615651                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19277594                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1316                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -399,99 +401,99 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1082135435                       # number of cpu cycles simulated
+system.cpu.numCycles                       1084515205                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      23942424                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      23906785                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.689108                       # CPI: cycles per instruction
-system.cpu.ipc                               0.592029                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1024380125                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        57755310                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            778330                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.458630                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378454621                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782426                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.693820                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         795587500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.458630                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999135                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999135                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.692822                       # CPI: cycles per instruction
+system.cpu.ipc                               0.590729                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1025899032                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        58616173                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            778339                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.484062                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378456435                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782435                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.690575                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         792553500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.484062                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999142                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999142                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          964                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         1346                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1586                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1585                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759395078                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759395078                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    249625893                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249625893                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         759398763                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759398763                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249627706                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249627706                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3485                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3485                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3486                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3486                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378439658                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378439658                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378443143                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378443143                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       713852                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713852                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     378441471                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378441471                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378444957                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378444957                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       713876                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713876                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       851564                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         851564                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       851705                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851705                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24973506500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24973506500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10064105500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10064105500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35037612000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35037612000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35037612000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35037612000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250339745                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250339745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       851588                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851588                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       851729                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851729                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24762813000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24762813000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10105718500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10105718500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34868531500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34868531500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34868531500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34868531500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250341582                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250341582                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3626                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3626                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3627                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3627                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379291222                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379291222                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379294848                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379294848                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    379293059                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379293059                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379296686                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379296686                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038886                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.038886                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038875                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.038875                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41145.013176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41138.201607                       # average overall miss latency
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002246                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002246                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40945.306298                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40938.527982                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -500,109 +502,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88940                       # number of writebacks
-system.cpu.dcache.writebacks::total             88940                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          887                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          887                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        88920                       # number of writebacks
+system.cpu.dcache.writebacks::total             88920                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          902                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          902                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        69277                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        69277                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        69277                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        69277                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712965                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712965                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data        69292                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        69292                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        69292                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69292                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712974                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712974                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782287                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782287                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782426                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782426                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24245308500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24245308500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5047418500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5047418500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29292727000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29292727000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29294515000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29294515000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       782296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782435                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782435                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24034165000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24034165000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5067912500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5067912500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1855000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1855000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29102077500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29102077500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29103932500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29103932500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038334                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038334                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038324                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038324                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             23593                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1712.048816                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           288484492                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25344                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11382.752999                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             23591                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1713.095623                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           291576498                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             25342                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11505.662458                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1712.048816                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835961                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835961                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1713.095623                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836472                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836472                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1603                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1600                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         577045018                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        577045018                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    288484492                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       288484492                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     288484492                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        288484492                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    288484492                       # number of overall hits
-system.cpu.icache.overall_hits::total       288484492                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        25345                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         25345                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        25345                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          25345                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        25345                       # number of overall misses
-system.cpu.icache.overall_misses::total         25345                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    499936000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    499936000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    499936000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    499936000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    499936000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    499936000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    288509837                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    288509837                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    288509837                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    288509837                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    288509837                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    288509837                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000088                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000088                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000088                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000088                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000088                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000088                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19725.231801                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19725.231801                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19725.231801                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19725.231801                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19725.231801                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19725.231801                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         583229024                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        583229024                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    291576498                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       291576498                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     291576498                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        291576498                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    291576498                       # number of overall hits
+system.cpu.icache.overall_hits::total       291576498                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        25343                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         25343                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        25343                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          25343                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        25343                       # number of overall misses
+system.cpu.icache.overall_misses::total         25343                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    498098000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    498098000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    498098000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    498098000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    498098000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    498098000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    291601841                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    291601841                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    291601841                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    291601841                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    291601841                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    291601841                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19654.263505                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19654.263505                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -611,129 +613,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25345                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        25345                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        25345                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        25345                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        25345                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        25345                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    474592000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    474592000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    474592000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    474592000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    474592000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    474592000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000088                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000088                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18725.271257                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18725.271257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18725.271257                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25343                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        25343                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        25343                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        25343                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        25343                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        25343                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    472756000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    472756000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    472756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    472756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    472756000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    472756000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258392                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32574.171271                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1245331                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291136                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.277489                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258395                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32574.709364                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1245326                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291139                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.277428                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2589.797972                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.410409                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29893.962890                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.079034                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002759                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.912291                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994085                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2589.156166                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.700113                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.079015                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002768                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.912319                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994101                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2812                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29416                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29412                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13211274                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13211274                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        88940                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        88940                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         13211317                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13211317                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks        88920                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        88920                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        22766                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        22766                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490569                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       490569                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        22766                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       493800                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          516566                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        22766                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       493800                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         516566                       # number of overall hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        22765                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        22765                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490574                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       490574                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        22765                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       493805                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          516570                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        22765                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       493805                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         516570                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66091                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2579                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2579                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222535                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222535                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2579                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       288626                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        291205                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2579                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       288626                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       291205                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4909508000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4909508000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    197530500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    197530500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18026385000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  18026385000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    197530500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22935893000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23133423500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    197530500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22935893000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23133423500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        88940                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        88940                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2578                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2578                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222539                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222539                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2578                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       288630                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        291208                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2578                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       288630                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       291208                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4930001500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4930001500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    195708000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    195708000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17815243000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  17815243000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    195708000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  22745244500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  22940952500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    195708000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  22745244500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  22940952500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks        88920                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        88920                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        25345                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        25345                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       713104                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       713104                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        25345                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       782426                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       807771                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        25345                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       782426                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       807771                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        25343                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        25343                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       713113                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       713113                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        25343                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       782435                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       807778                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        25343                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       782435                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       807778                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.101756                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.101756                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312065                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312065                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101756                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.368886                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.360504                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101756                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.368886                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.360504                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74284.062883                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74284.062883                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76591.896084                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76591.896084                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81004.718359                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81004.718359                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76591.896084                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79465.789638                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79440.337563                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76591.896084                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79465.789638                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79440.337563                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.101724                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.101724                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312067                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312067                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101724                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.368887                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.360505                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101724                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368887                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.360505                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74594.142924                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75914.662529                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75914.662529                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80054.475845                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80054.475845                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75914.662529                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78804.159304                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78778.579229                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75914.662529                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78804.159304                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -754,114 +756,114 @@ system.cpu.l2cache.demand_mshr_hits::total           32                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           28                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          369                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          369                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          376                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          376                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2575                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2575                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222507                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222507                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2575                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288598                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       291173                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2575                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288598                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       291173                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4248598000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4248598000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    171535500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    171535500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15799227000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15799227000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20047825000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20219360500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171535500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20047825000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20219360500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2574                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2574                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222511                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222511                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2574                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288602                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       291176                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2574                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288602                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       291176                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4269091500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4269091500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    169723000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    169723000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15588307500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15588307500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169723000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19857399000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20027122000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169723000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19857399000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20027122000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101598                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312026                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312026                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368850                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.101567                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101567                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312028                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312028                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101567                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368851                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.360465                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368850                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101567                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368851                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.360465                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64594.142924                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64594.142924                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        738448                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155038                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       901935                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        738455                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       155018                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       901956                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        25345                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       713104                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        72953                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341169                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2414122                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55767424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57389440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      258392                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1868086                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        25343                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       713113                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        72942                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341192                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2414134                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1621888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55766720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57388608                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258395                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1868103                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        1.138319                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.345235                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1609694     86.17%     86.17% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             258392     13.83%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            1609708     86.17%     86.17% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             258395     13.83%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1868086                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      893787000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1868103                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      893774000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      38017996                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      38014996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1173652972                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1173666472                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225081                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225084                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190637                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190644                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225081                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839079                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 839079                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22865280                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22865280                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225084                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839092                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839092                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22865472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22865472                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            547907                       # Request fanout histogram
+system.membus.snoop_fanout::samples            547917                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  547907    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  547917    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              547907                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           916769500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              547917                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           917948500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1554235250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1554418250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 2898b2e51..d3d29952c 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -688,7 +688,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index fc759c123..261f6c290 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -156,7 +156,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -266,7 +266,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
index 75824f793..a6321b5a0 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr
index de77515a1..f0a9a7c93 100644..100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
index bfc5e794b..9dd4d1ffb 100644..100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout
@@ -3,11 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  7 2014 10:41:53
-gem5 started May  7 2014 11:01:25
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:22:43
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 58222132000 because target called exit()
+Exiting @ tick 59549031000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index dfd14c576..c8b76a216 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.059580                       # Number of seconds simulated
-sim_ticks                                 59579614000                       # Number of ticks simulated
-final_tick                                59579614000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.059549                       # Number of seconds simulated
+sim_ticks                                 59549031000                       # Number of ticks simulated
+final_tick                                59549031000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 321432                       # Simulator instruction rate (inst/s)
-host_op_rate                                   321432                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              216544599                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304972                       # Number of bytes of host memory used
-host_seconds                                   275.14                       # Real time elapsed on the host
+host_inst_rate                                 231283                       # Simulator instruction rate (inst/s)
+host_op_rate                                   231283                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              155732739                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299636                       # Number of bytes of host memory used
+host_seconds                                   382.38                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            500672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10147648                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10648320                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       500672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          500672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7320576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7320576                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7823                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166380                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114384                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114384                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8403411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            170320808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               178724219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8403411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8403411                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         122870484                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              122870484                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         122870484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8403411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           170320808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              301594703                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166380                       # Number of read requests accepted
-system.physmem.writeReqs                       114384                       # Number of write requests accepted
-system.physmem.readBursts                      166380                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114384                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10648064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       256                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7319040                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10648320                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7320576                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        4                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            500352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10147264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10647616                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       500352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          500352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7320640                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7320640                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7818                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158551                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166369                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114385                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114385                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8402353                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            170401832                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               178804186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8402353                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8402353                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         122934662                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              122934662                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         122934662                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8402353                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           170401832                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              301738848                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166369                       # Number of read requests accepted
+system.physmem.writeReqs                       114385                       # Number of write requests accepted
+system.physmem.readBursts                      166369                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114385                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10647296                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7318592                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10647616                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7320640                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10451                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10447                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10284                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10088                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10415                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10418                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10283                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10092                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10413                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10414                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                9828                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10277                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10274                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               10580                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10645                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10557                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10259                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10298                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10623                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10516                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10631                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10558                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10261                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10296                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10620                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10515                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10632                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7162                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7274                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7273                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7295                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6999                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7000                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7182                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6834                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7095                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7222                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7181                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6833                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7224                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                6994                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7111                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6990                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7296                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7306                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7113                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6992                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7295                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     59579590000                       # Total gap between requests
+system.physmem.totGap                     59549007000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166380                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166369                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114384                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164758                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1592                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114385                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    164750                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1588                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7084                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7071                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -193,122 +193,122 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54737                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      328.220838                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     195.100573                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.685535                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19472     35.57%     35.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11861     21.67%     57.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5645     10.31%     67.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        54768                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      328.014023                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     195.067660                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.383666                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19491     35.59%     35.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11850     21.64%     57.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5663     10.34%     67.57% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511         3680      6.72%     74.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2860      5.22%     79.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2018      3.69%     83.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1694      3.09%     86.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1489      2.72%     89.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6018     10.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54737                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7040                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.631676                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      336.376134                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7037     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::512-639         2902      5.30%     79.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2048      3.74%     83.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1635      2.99%     86.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1469      2.68%     88.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6030     11.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54768                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7038                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.634839                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.413145                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7035     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7040                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7040                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.244318                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.229045                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.737232                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6278     89.18%     89.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 16      0.23%     89.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                578      8.21%     97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                145      2.06%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 15      0.21%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  3      0.04%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7038                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7038                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.247940                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.232365                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.745442                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6264     89.00%     89.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 17      0.24%     89.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                601      8.54%     97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                122      1.73%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 23      0.33%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  6      0.09%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7040                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2004219750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5123769750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    831880000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12046.33                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7038                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2001235750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5120560750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    831820000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12029.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30796.33                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         178.72                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         122.84                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      178.72                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      122.87                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30779.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         178.80                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         122.90                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      178.80                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      122.93                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.36                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.40                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.96                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144447                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81540                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.82                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.29                       # Row buffer hit rate for writes
-system.physmem.avgGap                       212205.23                       # Average gap between requests
-system.physmem.pageHitRate                      80.49                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  199372320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  108784500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 641464200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                368938800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3890992560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            12501731340                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24777284250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42488567970                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              713.220229                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    41071172000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1989260000                       # Time in different power states
+system.physmem.avgWrQLen                        24.01                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144462                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81475                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   86.83                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                       212103.86                       # Average gap between requests
+system.physmem.pageHitRate                      80.48                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  199614240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  108916500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 641355000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                368899920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3888958320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            12587581890                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24683289750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42478615620                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              713.426150                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    40913813750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1988220000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16512675000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16639693750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  214189920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116869500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 655792800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                371790000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3890992560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13114227690                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24240006750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42603869220                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              715.155695                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40171909250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1989260000                       # Time in different power states
+system.physmem_1.actEnergy                  214137000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116840625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 655777200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                371764080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3888958320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13157757450                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24183135750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42588370425                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              715.269477                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40075806250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1988220000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17411703250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17478332750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14668515                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9490335                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            391198                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9984003                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6387554                       # Number of BTB hits
+system.cpu.branchPred.lookups                14666095                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9488989                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            386100                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9897774                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6385513                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             63.977885                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1708558                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              85259                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             64.514637                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1708089                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              84886                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20570256                       # DTB read hits
-system.cpu.dtb.read_misses                      97321                       # DTB read misses
+system.cpu.dtb.read_hits                     20569916                       # DTB read hits
+system.cpu.dtb.read_misses                      97322                       # DTB read misses
 system.cpu.dtb.read_acv                            10                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20667577                       # DTB read accesses
-system.cpu.dtb.write_hits                    14665734                       # DTB write hits
-system.cpu.dtb.write_misses                      9406                       # DTB write misses
+system.cpu.dtb.read_accesses                 20667238                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665322                       # DTB write hits
+system.cpu.dtb.write_misses                      9407                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14675140                       # DTB write accesses
-system.cpu.dtb.data_hits                     35235990                       # DTB hits
-system.cpu.dtb.data_misses                     106727                       # DTB misses
+system.cpu.dtb.write_accesses                14674729                       # DTB write accesses
+system.cpu.dtb.data_hits                     35235238                       # DTB hits
+system.cpu.dtb.data_misses                     106729                       # DTB misses
 system.cpu.dtb.data_acv                            10                       # DTB access violations
-system.cpu.dtb.data_accesses                 35342717                       # DTB accesses
-system.cpu.itb.fetch_hits                    25623202                       # ITB hits
-system.cpu.itb.fetch_misses                      5252                       # ITB misses
+system.cpu.dtb.data_accesses                 35341967                       # DTB accesses
+system.cpu.itb.fetch_hits                    25606453                       # ITB hits
+system.cpu.itb.fetch_misses                      5227                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25628454                       # ITB accesses
+system.cpu.itb.fetch_accesses                25611680                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -322,81 +322,81 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        119159228                       # number of cpu cycles simulated
+system.cpu.numCycles                        119098062                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1111760                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1106110                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.347375                       # CPI: cycles per instruction
-system.cpu.ipc                               0.742184                       # IPC: instructions per cycle
-system.cpu.tickCycles                        91522395                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        27636833                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            200775                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.716592                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34616548                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204871                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.967536                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         688117500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.716592                       # Average occupied blocks per requestor
+system.cpu.cpi                               1.346683                       # CPI: cycles per instruction
+system.cpu.ipc                               0.742565                       # IPC: instructions per cycle
+system.cpu.tickCycles                        91473495                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        27624567                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            200766                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.715334                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34616231                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204862                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            168.973411                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         687575500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.715334                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993827                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993827                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3359                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          686                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3360                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70177059                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70177059                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20283298                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20283298                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14333250                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333250                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34616548                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34616548                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34616548                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34616548                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89419                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89419                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       280127                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280127                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       369546                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369546                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       369546                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369546                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4766015000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4766015000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21725113500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21725113500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  26491128500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  26491128500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  26491128500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  26491128500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20372717                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20372717                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70176386                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70176386                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20282965                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20282965                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333266                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333266                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34616231                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34616231                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34616231                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34616231                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89420                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89420                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       280111                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280111                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       369531                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369531                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       369531                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369531                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4765724000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4765724000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21723340000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21723340000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  26489064000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  26489064000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  26489064000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  26489064000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20372385                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20372385                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34986094                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34986094                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34986094                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34986094                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     34985762                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34985762                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34985762                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34985762                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004389                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004389                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019169                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019169                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.010563                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010563                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.010563                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010563                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53299.802055                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53299.802055                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77554.514559                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77554.514559                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71685.604769                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71685.604769                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71685.604769                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71685.604769                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019168                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010562                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010562                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010562                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010562                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53295.951689                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53295.951689                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77552.613071                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77552.613071                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71682.927819                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71682.927819                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71682.927819                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71682.927819                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -405,32 +405,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168451                       # number of writebacks
-system.cpu.dcache.writebacks::total            168451                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28112                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136563                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136563                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       164675                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164675                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       164675                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164675                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61307                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61307                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143564                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143564                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       204871                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204871                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       204871                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204871                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2678080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2678080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10985374000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10985374000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13663454000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13663454000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13663454000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13663454000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       168453                       # number of writebacks
+system.cpu.dcache.writebacks::total            168453                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28115                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28115                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136554                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136554                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       164669                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164669                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       164669                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164669                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61305                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61305                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143557                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143557                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       204862                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204862                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204862                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204862                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2678183500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2678183500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10981560500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10981560500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13659744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13659744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13659744000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13659744000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
@@ -439,69 +439,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43683.103071                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43683.103071                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76519.001978                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76519.001978                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66692.962889                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66692.962889                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66692.962889                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66692.962889                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43686.216459                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43686.216459                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76496.168769                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76496.168769                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66677.783093                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66677.783093                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66677.783093                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66677.783093                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            153439                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1932.585595                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25467714                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            155487                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            163.793205                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42332946500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1932.585595                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.943645                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.943645                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            152851                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1932.369225                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25451553                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            154899                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            164.310635                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42309465500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1932.369225                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.943540                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.943540                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1043                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1041                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          798                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51401891                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51401891                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25467714                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25467714                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25467714                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25467714                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25467714                       # number of overall hits
-system.cpu.icache.overall_hits::total        25467714                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       155488                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        155488                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       155488                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         155488                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       155488                       # number of overall misses
-system.cpu.icache.overall_misses::total        155488                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2558679500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2558679500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2558679500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2558679500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2558679500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2558679500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25623202                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25623202                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25623202                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25623202                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25623202                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25623202                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006068                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006068                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006068                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006068                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006068                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006068                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16455.800448                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16455.800448                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16455.800448                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16455.800448                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16455.800448                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16455.800448                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51367805                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51367805                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25451553                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25451553                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25451553                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25451553                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25451553                       # number of overall hits
+system.cpu.icache.overall_hits::total        25451553                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       154900                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        154900                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       154900                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         154900                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       154900                       # number of overall misses
+system.cpu.icache.overall_misses::total        154900                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2550963000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2550963000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2550963000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2550963000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2550963000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2550963000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25606453                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25606453                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25606453                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25606453                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25606453                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25606453                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006049                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006049                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006049                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006049                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006049                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006049                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16468.450613                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16468.450613                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16468.450613                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16468.450613                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16468.450613                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16468.450613                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -510,129 +510,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       155488                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       155488                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       155488                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       155488                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       155488                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       155488                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2403192500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2403192500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2403192500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2403192500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2403192500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2403192500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006068                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006068                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006068                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006068                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006068                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006068                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15455.806879                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15455.806879                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15455.806879                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15455.806879                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15455.806879                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15455.806879                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154900                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       154900                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       154900                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       154900                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       154900                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       154900                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2396064000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2396064000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2396064000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2396064000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2396064000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2396064000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006049                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006049                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006049                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15468.457069                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15468.457069                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15468.457069                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15468.457069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15468.457069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15468.457069                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132455                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30425.611503                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             404125                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164531                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.456224                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132445                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30425.579826                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             402950                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164521                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.449231                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 25960.344438                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2481.956505                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1983.310560                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.792247                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075743                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.060526                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.928516                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 25961.899693                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2481.819774                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1981.860360                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.792294                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075739                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.060482                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.928515                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32076                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          937                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11867                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19026                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          938                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11872                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19020                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          126                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978882                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          6024680                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         6024680                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       168451                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168451                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12683                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12683                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       147664                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       147664                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33631                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        33631                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       147664                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46314                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          193978                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       147664                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46314                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         193978                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses          6015111                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         6015111                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       168453                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168453                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12676                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12676                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       147081                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       147081                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33635                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        33635                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       147081                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46311                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          193392                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       147081                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46311                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         193392                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       130882                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       130882                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         7824                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         7824                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27675                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27675                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7824                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158557                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166381                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7824                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158557                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166381                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10636812500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10636812500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    619419000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    619419000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2232532000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2232532000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    619419000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12869344500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13488763500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    619419000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12869344500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13488763500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       168451                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168451                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143565                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143565                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       155488                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       155488                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61306                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        61306                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       155488                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       204871                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       360359                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       155488                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       204871                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       360359                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911657                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911657                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.050319                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.050319                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.451424                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.451424                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.050319                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.773936                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.461709                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.050319                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.773936                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.461709                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81270.247246                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81270.247246                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79169.095092                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79169.095092                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80669.629630                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80669.629630                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79169.095092                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81165.413700                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81071.537615                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79169.095092                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81165.413700                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81071.537615                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         7819                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         7819                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27669                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27669                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7819                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158551                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        166370                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7819                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158551                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       166370                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10633082500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10633082500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    619293500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    619293500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2232602500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2232602500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    619293500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  12865685000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13484978500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    619293500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12865685000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13484978500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       168453                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168453                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143558                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143558                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       154900                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       154900                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61304                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        61304                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       154900                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       204862                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       359762                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       154900                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       204862                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       359762                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911701                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911701                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.050478                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.050478                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.451341                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.451341                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.050478                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.773941                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.462445                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.050478                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.773941                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.462445                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81241.748292                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81241.748292                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79203.670546                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79203.670546                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80689.670751                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80689.670751                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79203.670546                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81145.404318                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81054.147382                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79203.670546                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81145.404318                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81054.147382                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -641,116 +641,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114384                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114384                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2093                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         2093                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.writebacks::writebacks       114385                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114385                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2091                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         2091                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130882                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130882                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         7824                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         7824                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27675                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27675                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7824                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158557                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166381                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7824                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158557                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166381                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9327992500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9327992500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    541189000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    541189000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1955782000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1955782000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    541189000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11283774500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11824963500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    541189000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11283774500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11824963500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         7819                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         7819                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27669                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27669                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7819                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158551                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166370                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7819                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158551                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       166370                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9324262500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9324262500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    541113500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    541113500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1955912500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1955912500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    541113500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11280175000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11821288500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    541113500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11280175000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11821288500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911657                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911657                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.050319                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451424                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451424                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773936                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.461709                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773936                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.461709                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71270.247246                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71270.247246                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69170.373211                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69170.373211                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70669.629630                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70669.629630                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69170.373211                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71165.413700                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71071.597718                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69170.373211                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71165.413700                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71071.597718                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911701                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911701                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.050478                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.050478                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451341                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451341                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.050478                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773941                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.462445                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.050478                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773941                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.462445                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71241.748292                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71241.748292                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69204.949482                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69204.949482                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70689.670751                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70689.670751                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69204.949482                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71145.404318                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71054.207489                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        216793                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       282835                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       203834                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       155488                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        61306                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       464414                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610517                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1074931                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9951168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23892608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           33843776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      132455                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       847028                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.156376                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.363212                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        216203                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       282838                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       203224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143558                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143558                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       154900                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        61304                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462650                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610490                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1073140                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9913536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23892160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           33805696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      132445                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       845824                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.156587                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.363411                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             714573     84.36%     84.36% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             132455     15.64%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             713379     84.34%     84.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             132445     15.66%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         847028                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      525737500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         845824                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      525142500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     233232496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     232349997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     307309993                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     307296493                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              35498                       # Transaction distribution
-system.membus.trans_dist::Writeback            114384                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            16134                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35487                       # Transaction distribution
+system.membus.trans_dist::Writeback            114385                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16125                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            130882                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           130882                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         35498                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463278                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 463278                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17968896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17968896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         35487                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463248                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 463248                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17968256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17968256                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            296898                       # Request fanout histogram
+system.membus.snoop_fanout::samples            296879                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  296898    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  296879    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              296898                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           824886500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              296879                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           824874000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          878487500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          878418750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 7662c92f8..3a9ebdb7f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -497,7 +497,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -546,7 +546,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -609,7 +609,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 2061356b3..92f71955f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022637                       # Number of seconds simulated
-sim_ticks                                 22637068500                       # Number of ticks simulated
-final_tick                                22637068500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022357                       # Number of seconds simulated
+sim_ticks                                 22356634500                       # Number of ticks simulated
+final_tick                                22356634500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 222882                       # Simulator instruction rate (inst/s)
-host_op_rate                                   222882                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63391012                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306268                       # Number of bytes of host memory used
-host_seconds                                   357.10                       # Real time elapsed on the host
+host_inst_rate                                 154709                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154709                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43456447                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300660                       # Number of bytes of host memory used
+host_seconds                                   514.46                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            472384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10153088                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10625472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       472384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          472384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7318784                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7318784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7381                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158642                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166023                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114356                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114356                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             20867720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            448516026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               469383746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        20867720                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           20867720                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         323309708                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              323309708                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         323309708                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            20867720                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           448516026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              792693453                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166023                       # Number of read requests accepted
-system.physmem.writeReqs                       114356                       # Number of write requests accepted
-system.physmem.readBursts                      166023                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114356                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10625216                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       256                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7317504                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10625472                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7318784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        4                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            471552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10150720                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10622272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       471552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          471552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7318272                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7318272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7368                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158605                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165973                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114348                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114348                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             21092262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            454036139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               475128401                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        21092262                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           21092262                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         327342293                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              327342293                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         327342293                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            21092262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           454036139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              802470694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165973                       # Number of read requests accepted
+system.physmem.writeReqs                       114348                       # Number of write requests accepted
+system.physmem.readBursts                      165973                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114348                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10621952                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7316672                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10622272                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7318272                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10427                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10469                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10420                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10451                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10285                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10058                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10410                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10383                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9823                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10285                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10562                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10635                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10512                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10227                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10266                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10590                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10056                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10402                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10375                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9822                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10280                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10559                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10640                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10517                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10263                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10582                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10475                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10612                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10613                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7161                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7270                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7267                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7294                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7175                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7171                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6835                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                7095                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                6995                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7100                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6993                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7294                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7101                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6988                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7292                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22637037500                       # Total gap between requests
+system.physmem.totGap                     22356603500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166023                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165973                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114356                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     52265                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     42988                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     38514                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32235                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114348                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     52267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     43039                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     38487                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      835                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::16                      860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1884                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6911                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -193,123 +193,125 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52301                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      343.050573                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     202.162039                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.313279                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18282     34.96%     34.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10576     20.22%     55.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5922     11.32%     66.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2988      5.71%     72.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3062      5.85%     78.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1483      2.84%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1989      3.80%     84.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1021      1.95%     86.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6978     13.34%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52301                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6994                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.736917                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      336.159441                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6991     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        52288                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      343.051408                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     202.164629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.365120                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18284     34.97%     34.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10551     20.18%     55.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5984     11.44%     66.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2964      5.67%     72.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2982      5.70%     77.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1592      3.04%     81.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1956      3.74%     84.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          963      1.84%     86.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7012     13.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52288                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6989                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.745743                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      338.273336                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6986     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6994                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6994                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.347727                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.319415                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.025091                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6123     87.55%     87.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 26      0.37%     87.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                468      6.69%     94.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                194      2.77%     97.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 92      1.32%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 55      0.79%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 18      0.26%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.14%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.09%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6994                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5783499750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8896356000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    830095000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34836.37                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6989                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6989                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.357562                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.328073                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.050353                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6097     87.24%     87.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 30      0.43%     87.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                474      6.78%     94.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                201      2.88%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 97      1.39%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 49      0.70%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 24      0.34%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  8      0.11%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.07%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6989                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5746744750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8858644750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    829840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34625.62                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  53586.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         469.37                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         323.25                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      469.38                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      323.31                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53375.62                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         475.11                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         327.27                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      475.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      327.34                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           6.19                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.67                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      2.53                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.92                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145949                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82096                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.91                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                        80737.28                       # Average gap between requests
-system.physmem.pageHitRate                      81.34                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  190852200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  104135625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 640543800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                368925840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1478383920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6748287570                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7661408250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              17192537205                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              759.557739                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12661521500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       755820000                       # Time in different power states
+system.physmem.busUtil                           6.27                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.71                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      2.56                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145973                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82020                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.95                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                        79753.58                       # Average gap between requests
+system.physmem.pageHitRate                      81.33                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  190882440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  104152125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 640161600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                368899920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             1460075760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             6647542920                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             7581572250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              16993287015                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              760.170138                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    12528806000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       746460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9217738000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9079331500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  204354360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  111502875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654108000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                371764080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1478383920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6845140260                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             7576424250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              17241677745                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              761.730174                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    12521267250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       755820000                       # Time in different power states
+system.physmem_1.actEnergy                  204271200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  111457500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 654100200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                371699280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             1460075760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             6857633520                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             7397282250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              17056519710                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              762.998761                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    12224344750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       746460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9357815250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9383970250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16666171                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10777513                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            373740                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11097684                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7405754                       # Number of BTB hits
+system.cpu.branchPred.lookups                16500558                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10689411                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            329507                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9043813                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7288978                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             66.732428                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1996658                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               2898                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.596293                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1974529                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               2931                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22620977                       # DTB read hits
-system.cpu.dtb.read_misses                     226849                       # DTB read misses
-system.cpu.dtb.read_acv                            27                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22847826                       # DTB read accesses
-system.cpu.dtb.write_hits                    15870488                       # DTB write hits
-system.cpu.dtb.write_misses                     45057                       # DTB write misses
-system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                15915545                       # DTB write accesses
-system.cpu.dtb.data_hits                     38491465                       # DTB hits
-system.cpu.dtb.data_misses                     271906                       # DTB misses
-system.cpu.dtb.data_acv                            31                       # DTB access violations
-system.cpu.dtb.data_accesses                 38763371                       # DTB accesses
-system.cpu.itb.fetch_hits                    13971550                       # ITB hits
-system.cpu.itb.fetch_misses                     35700                       # ITB misses
+system.cpu.dtb.read_hits                     22520885                       # DTB read hits
+system.cpu.dtb.read_misses                     225850                       # DTB read misses
+system.cpu.dtb.read_acv                            12                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22746735                       # DTB read accesses
+system.cpu.dtb.write_hits                    15825785                       # DTB write hits
+system.cpu.dtb.write_misses                     44675                       # DTB write misses
+system.cpu.dtb.write_acv                            5                       # DTB write access violations
+system.cpu.dtb.write_accesses                15870460                       # DTB write accesses
+system.cpu.dtb.data_hits                     38346670                       # DTB hits
+system.cpu.dtb.data_misses                     270525                       # DTB misses
+system.cpu.dtb.data_acv                            17                       # DTB access violations
+system.cpu.dtb.data_accesses                 38617195                       # DTB accesses
+system.cpu.itb.fetch_hits                    13761847                       # ITB hits
+system.cpu.itb.fetch_misses                     29330                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                14007250                       # ITB accesses
+system.cpu.itb.fetch_accesses                13791177                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -323,100 +325,100 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         45274140                       # number of cpu cycles simulated
+system.cpu.numCycles                         44713274                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15840684                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      106412182                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16666171                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9402412                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      27820247                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  987192                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        787                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 5202                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        343767                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          103                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13971550                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                209132                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           15584768                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105191572                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16500558                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9263507                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      27593237                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  896542                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        162                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 4764                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        325871                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          110                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13761847                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                191924                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           44504386                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.391049                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.126296                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples           43957183                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.393046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.127676                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24724412     55.56%     55.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1545163      3.47%     59.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1406842      3.16%     62.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1520478      3.42%     65.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4242713      9.53%     75.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1851895      4.16%     79.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   685374      1.54%     80.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1070742      2.41%     83.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7456767     16.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24416716     55.55%     55.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1522401      3.46%     59.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1379227      3.14%     62.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1505485      3.42%     65.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4199085      9.55%     75.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1828470      4.16%     79.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   669319      1.52%     80.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1052182      2.39%     83.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7384298     16.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44504386                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.368117                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.350397                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15190182                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9797968                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18517517                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                603822                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 394897                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3753615                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                100898                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              104278713                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                316536                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 394897                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15562376                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4515044                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          96153                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18732590                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5203326                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              103086111                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  6702                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  93508                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 341438                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4700364                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            62061981                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             124384146                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        124055114                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            329031                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43957183                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369030                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.352580                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14931500                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9767964                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18310970                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                595597                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 351152                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3708003                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 98860                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103215952                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                311866                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 351152                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15279451                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4431592                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          96231                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18542963                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5255794                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102192828                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  5698                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  95463                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 341437                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4753642                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            61435412                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123253139                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        122935807                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            317331                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9515100                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5718                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5766                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   2349661                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23316234                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16465365                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1246740                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           545757                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   91441079                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5553                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  89167924                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             83024                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11854875                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4801848                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            970                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44504386                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.003576                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.243462                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  8888531                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5692                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5745                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2361848                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23156457                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16385404                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1258348                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           502815                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90834629                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5552                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88691609                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             70456                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11248424                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4497706                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            969                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43957183                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.017682                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.245665                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17850579     40.11%     40.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5788896     13.01%     53.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5155949     11.59%     64.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4393297      9.87%     74.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4359248      9.80%     84.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2645472      5.94%     90.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1941559      4.36%     94.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1381555      3.10%     97.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              987831      2.22%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17476881     39.76%     39.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5730177     13.04%     52.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5107740     11.62%     64.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4380373      9.97%     74.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4328154      9.85%     84.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2635103      5.99%     90.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1947598      4.43%     94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1378142      3.14%     97.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              973015      2.21%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44504386                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43957183                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  244058      9.64%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  243362      9.64%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.64% # attempts to use FU when none available
@@ -445,118 +447,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.64% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.64% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1174802     46.40%     56.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1112961     43.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1165216     46.16%     55.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1115524     44.19%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49705550     55.74%     55.74% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                44198      0.05%     55.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121960      0.14%     55.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     55.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              121539      0.14%     56.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 56      0.00%     56.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               39076      0.04%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23058691     25.86%     81.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16076765     18.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49430492     55.73%     55.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43978      0.05%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121147      0.14%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  93      0.00%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              120628      0.14%     56.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 63      0.00%     56.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39084      0.04%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22917985     25.84%     81.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            16018139     18.06%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               89167924                       # Type of FU issued
-system.cpu.iq.rate                           1.969511                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2531821                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.028394                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          224839378                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         102887543                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87218101                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              615701                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             435266                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       300894                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               91391726                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  308019                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1669932                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88691609                       # Type of FU issued
+system.cpu.iq.rate                           1.983563                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2524102                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028459                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          223325364                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101690449                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86898361                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              609595                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             418176                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       299341                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90910760                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  304951                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1670602                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3039596                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6284                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        21688                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1851988                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2879819                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5660                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20258                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1772027                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3150                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        205518                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3047                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        205936                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 394897                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1352665                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2733681                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100982224                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            167502                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23316234                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16465365                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5553                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3853                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2732159                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          21688                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         162395                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       158558                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               320953                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              88354535                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22848688                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            813389                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 351152                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1286887                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2706445                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100341607                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            125884                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23156457                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16385404                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5552                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3769                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               2705021                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20258                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         121859                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       151192                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               273051                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87981340                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22747403                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            710269                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9535592                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38764588                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15181336                       # Number of branches executed
-system.cpu.iew.exec_stores                   15915900                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.951545                       # Inst execution rate
-system.cpu.iew.wb_sent                       87941007                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87518995                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33890392                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44346264                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9501426                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38618193                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15127263                       # Number of branches executed
+system.cpu.iew.exec_stores                   15870790                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.967678                       # Inst execution rate
+system.cpu.iew.wb_sent                       87600358                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87197702                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33849535                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44277575                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.933090                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764222                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.950152                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764485                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         9432406                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         8791000                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            275041                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43112835                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.049057                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.870632                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            232388                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     42666920                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.070472                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.884283                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     21537439     49.96%     49.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6339258     14.70%     64.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2938097      6.81%     71.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1767481      4.10%     75.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1703049      3.95%     79.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1136594      2.64%     82.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1201073      2.79%     84.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       797579      1.85%     86.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5692265     13.20%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     21190783     49.67%     49.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6285871     14.73%     64.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2905995      6.81%     71.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1744112      4.09%     75.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1680276      3.94%     79.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1128586      2.65%     81.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1203447      2.82%     84.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       797041      1.87%     86.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5730809     13.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43112835                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     42666920                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -602,349 +604,333 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5692265                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    133876306                       # The number of ROB reads
-system.cpu.rob.rob_writes                   196941310                       # The number of ROB writes
-system.cpu.timesIdled                           47582                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          769754                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               5730809                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    132750441                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195556891                       # The number of ROB writes
+system.cpu.timesIdled                           46372                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          756091                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.568830                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.568830                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.757996                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.757996                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116950893                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57974920                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    255771                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   241359                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38164                       # number of misc regfile reads
+system.cpu.cpi                               0.561783                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.561783                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.780048                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.780048                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116466074                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57713698                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255059                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   240376                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38265                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            201397                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.850359                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34098493                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205493                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.935059                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         231077500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.850359                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993860                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993860                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            201297                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.745765                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33997888                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205393                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.526031                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         229746500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.745765                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993834                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993834                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2777                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1229                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2788                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1232                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          71045365                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         71045365                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20537317                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20537317                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13561115                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13561115                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      34098432                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34098432                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34098432                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34098432                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       269180                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        269180                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1052262                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1052262                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1321442                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1321442                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1321442                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1321442                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  17386725500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  17386725500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  89260696666                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  89260696666                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        99000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        99000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 106647422166                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 106647422166                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 106647422166                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 106647422166                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20806497                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20806497                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70843209                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70843209                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20436554                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20436554                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13561278                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13561278                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           56                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           56                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      33997832                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33997832                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33997832                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33997832                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       268921                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        268921                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1052099                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1052099                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1321020                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1321020                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1321020                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1321020                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  17355062000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  17355062000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  89131929604                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  89131929604                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 106486991604                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 106486991604                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 106486991604                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 106486991604                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20705475                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20705475                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           62                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           62                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35419874                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35419874                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35419874                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35419874                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012937                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012937                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072007                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.072007                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.016129                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.016129                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037308                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037308                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037308                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037308                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64591.446244                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64591.446244                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84827.444749                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 84827.444749                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        99000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        99000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80705.337174                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80705.337174                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80705.337174                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80705.337174                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      6894813                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           56                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           56                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35318852                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35318852                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35318852                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35318852                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012988                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012988                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071996                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071996                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037403                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037403                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037403                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037403                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80609.674043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80609.674043                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      6869550                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             88842                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             88969                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.607584                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.212849                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168840                       # number of writebacks
-system.cpu.dcache.writebacks::total            168840                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207085                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       207085                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908865                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       908865                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1115950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1115950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1115950                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1115950                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62095                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62095                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168788                       # number of writebacks
+system.cpu.dcache.writebacks::total            168788                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       206925                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       206925                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908702                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       908702                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115627                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115627                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115627                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115627                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61996                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61996                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143397                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       143397                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205492                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205492                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205492                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205492                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3215385000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3215385000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14267732202                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14267732202                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        98000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        98000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17483117202                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17483117202                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17483117202                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17483117202                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002984                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002984                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205393                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205393                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205393                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205393                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3212836500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3212836500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14233206202                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14233206202                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17446042702                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17446042702                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17446042702                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17446042702                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002994                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002994                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.016129                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.016129                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005802                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005802                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005802                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005802                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51781.705451                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51781.705451                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99498.122011                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99498.122011                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        98000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        98000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85079.308207                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 85079.308207                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85079.308207                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 85079.308207                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005815                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005815                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005815                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005815                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             93160                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1916.318628                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13863089                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             95208                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            145.608447                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       19085068500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1916.318628                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.935702                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.935702                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             91498                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1915.935564                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13655300                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             93546                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            145.974173                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18815415500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1915.935564                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.935515                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.935515                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1486                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          371                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1476                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          380                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          28038306                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         28038306                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13863089                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13863089                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13863089                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13863089                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13863089                       # number of overall hits
-system.cpu.icache.overall_hits::total        13863089                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       108460                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        108460                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       108460                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         108460                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       108460                       # number of overall misses
-system.cpu.icache.overall_misses::total        108460                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2048888998                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2048888998                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2048888998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2048888998                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2048888998                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2048888998                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13971549                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13971549                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13971549                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13971549                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13971549                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13971549                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007763                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007763                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007763                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007763                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007763                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007763                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18890.733893                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18890.733893                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18890.733893                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18890.733893                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18890.733893                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18890.733893                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1159                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27617236                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27617236                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13655300                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13655300                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13655300                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13655300                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13655300                       # number of overall hits
+system.cpu.icache.overall_hits::total        13655300                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       106545                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        106545                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       106545                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         106545                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       106545                       # number of overall misses
+system.cpu.icache.overall_misses::total        106545                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2015171999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2015171999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2015171999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2015171999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2015171999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2015171999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13761845                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13761845                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13761845                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13761845                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13761845                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13761845                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007742                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007742                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007742                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007742                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007742                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007742                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18913.811056                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18913.811056                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18913.811056                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18913.811056                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18913.811056                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18913.811056                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1468                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    82.785714                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    77.263158                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        13251                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        13251                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        13251                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        13251                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        13251                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        13251                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        95209                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        95209                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        95209                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        95209                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        95209                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        95209                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1668176000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1668176000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1668176000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1668176000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1668176000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1668176000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006814                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006814                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006814                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006814                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006814                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006814                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17521.200727                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17521.200727                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17521.200727                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17521.200727                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17521.200727                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17521.200727                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12998                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        12998                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        12998                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        12998                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        12998                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        12998                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93547                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        93547                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        93547                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        93547                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        93547                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        93547                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1645041500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1645041500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1645041500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1645041500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1645041500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1645041500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006798                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006798                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006798                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006798                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006798                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006798                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17585.187125                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17585.187125                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17585.187125                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17585.187125                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17585.187125                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17585.187125                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132107                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30604.111406                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             285364                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164184                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.738074                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132064                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30597.382084                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             281892                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164129                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.717503                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26463.213686                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2221.858475                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1919.039245                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.807593                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.067806                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.058564                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.933963                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32077                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          185                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3041                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28427                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          365                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4           59                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978912                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          5069653                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         5069653                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       168840                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168840                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 26451.406117                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2221.195572                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1924.780395                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.807233                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.067786                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.058740                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.933758                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32065                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3040                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28434                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          367                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978546                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          5041408                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         5041408                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       168788                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168788                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        12616                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        12616                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        87827                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        87827                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34235                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        34235                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        87827                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46851                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          134678                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        87827                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46851                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         134678                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130781                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130781                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         7382                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         7382                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27861                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27861                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7382                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158642                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166024                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7382                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158642                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166024                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13916068500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13916068500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    602620000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    602620000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2758143500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2758143500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    602620000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  16674212000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  17276832000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    602620000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  16674212000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  17276832000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       168840                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168840                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143397                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143397                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        95209                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        95209                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62096                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        62096                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        95209                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205493                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       300702                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        95209                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205493                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       300702                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912020                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.912020                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.077535                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.077535                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448676                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448676                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.077535                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.772007                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.552121                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.077535                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.772007                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.552121                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106407.417744                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106407.417744                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81633.703603                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81633.703603                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98996.572269                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98996.572269                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81633.703603                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105105.911423                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 104062.256059                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81633.703603                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105105.911423                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 104062.256059                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        86178                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        86178                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34172                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        34172                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        86178                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46788                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          132966                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        86178                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46788                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         132966                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130783                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130783                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         7369                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         7369                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27822                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27822                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7369                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158605                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        165974                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7369                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158605                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       165974                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13881530500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  13881530500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    599246500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    599246500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2756158500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2756158500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    599246500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  16637689000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17236935500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    599246500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  16637689000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17236935500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       168788                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168788                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143399                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143399                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        93547                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        93547                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61994                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        61994                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        93547                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205393                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       298940                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        93547                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205393                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       298940                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912022                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.912022                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.078773                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.078773                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448785                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448785                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.078773                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.772203                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.555208                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.078773                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.772203                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.555208                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106141.704197                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106141.704197                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81319.921292                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81319.921292                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99063.996118                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99063.996118                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81319.921292                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104900.154472                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 103853.227011                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81319.921292                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104900.154472                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 103853.227011                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -953,116 +939,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114356                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114356                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2054                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         2054                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130781                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130781                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         7382                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         7382                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27861                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27861                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7382                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158642                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166024                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7382                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158642                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166024                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12608258500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12608258500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    528810000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    528810000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2479533500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2479533500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    528810000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15087792000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15616602000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    528810000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15087792000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15616602000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       114348                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114348                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2056                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         2056                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130783                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130783                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         7369                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         7369                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27822                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27822                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7369                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158605                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       165974                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7369                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158605                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       165974                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12573700500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12573700500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    525566500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    525566500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2477938500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2477938500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    525566500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15051639000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  15577205500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    525566500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15051639000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  15577205500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912020                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912020                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.077535                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.077535                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448676                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448676                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.077535                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772007                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.552121                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.077535                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772007                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.552121                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96407.417744                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96407.417744                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71635.058250                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71635.058250                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88996.572269                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88996.572269                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71635.058250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95105.911423                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94062.316292                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71635.058250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95105.911423                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94062.316292                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912022                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912022                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.078773                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.078773                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448785                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448785                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.078773                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772203                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.555208                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.078773                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772203                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.555208                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96141.704197                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96141.704197                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71321.278328                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71321.278328                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89063.996118                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89063.996118                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71321.278328                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94900.154472                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93853.287262                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp        157304                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       283196                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       143468                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143397                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143397                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        95209                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        62096                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       283577                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612383                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            895960                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6093312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23957312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           30050624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      132107                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       727366                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.181624                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.385534                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        155540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       283136                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       141723                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        93547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        61994                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       278591                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612083                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            890674                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5986944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23947584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           29934528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      132064                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       723799                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.182459                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.386223                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             595259     81.84%     81.84% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             132107     18.16%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             591735     81.75%     81.75% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             132064     18.25%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         727366                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      466469500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         723799                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      464655500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     142819485                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     140327982                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     308243991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     308097983                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              35242                       # Transaction distribution
-system.membus.trans_dist::Writeback            114356                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15775                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130781                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130781                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         35242                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462177                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 462177                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17944256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17944256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              35190                       # Transaction distribution
+system.membus.trans_dist::Writeback            114348                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15746                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130783                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130783                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         35190                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462040                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 462040                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17940544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17940544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            296154                       # Request fanout histogram
+system.membus.snoop_fanout::samples            296067                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  296154    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  296067    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              296154                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           778878000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          857917500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              296067                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           778875000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          857731250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
index 5bde02f67..802d9b780 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -759,7 +759,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
index 0ebe6ca65..f97f5968b 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 03:05:45
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x3b079b0
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 57738195500 because target called exit()
+Exiting @ tick 56986224500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index a8d113a77..227ff6a79 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.057054                       # Number of seconds simulated
-sim_ticks                                 57053790500                       # Number of ticks simulated
-final_tick                                57053790500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.056986                       # Number of seconds simulated
+sim_ticks                                 56986224500                       # Number of ticks simulated
+final_tick                                56986224500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 195523                       # Simulator instruction rate (inst/s)
-host_op_rate                                   250045                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              157305109                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323528                       # Number of bytes of host memory used
-host_seconds                                   362.70                       # Real time elapsed on the host
+host_inst_rate                                 135704                       # Simulator instruction rate (inst/s)
+host_op_rate                                   173546                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              109049636                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317176                       # Number of bytes of host memory used
+host_seconds                                   522.57                       # Real time elapsed on the host
 sim_insts                                    70915128                       # Number of instructions simulated
 sim_ops                                      90690084                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            319296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7924224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8243520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       319296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          319296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5514240                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5514240                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             123816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128805                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           86160                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                86160                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5596403                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            138890404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               144486807                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5596403                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5596403                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          96649845                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               96649845                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          96649845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5596403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           138890404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              241136652                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128805                       # Number of read requests accepted
-system.physmem.writeReqs                        86160                       # Number of write requests accepted
-system.physmem.readBursts                      128805                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      86160                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8243200                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5512512                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8243520                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5514240                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            318720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7923904                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8242624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       318720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          318720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5514048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5514048                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4980                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             123811                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128791                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           86157                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                86157                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5592931                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            139049464                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               144642395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5592931                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5592931                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          96761069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               96761069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          96761069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5592931                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           139049464                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              241403464                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128791                       # Number of read requests accepted
+system.physmem.writeReqs                        86157                       # Number of write requests accepted
+system.physmem.readBursts                      128791                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      86157                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8242176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5512000                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8242624                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5514048                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8145                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8375                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8247                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8144                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8370                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8248                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                8170                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8318                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8434                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8315                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8436                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7957                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8058                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7633                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7816                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7955                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8060                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7629                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7815                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               7829                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7879                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               7996                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7878                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7975                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               7995                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                5393                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5541                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                5463                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5328                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                5352                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5550                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5247                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5545                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5246                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                5180                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                5155                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5102                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5101                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5289                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5270                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5531                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5597                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               5703                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5432                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5431                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     57053759500                       # Total gap between requests
+system.physmem.totGap                     56986193500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128805                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128791                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  86160                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116563                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12216                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  86157                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    116559                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        23                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      641                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -193,97 +193,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38707                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      355.314336                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     216.053807                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.949103                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12175     31.45%     31.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8182     21.14%     52.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4142     10.70%     63.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2786      7.20%     70.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2727      7.05%     77.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1625      4.20%     81.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1301      3.36%     85.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1172      3.03%     88.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4597     11.88%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38707                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5298                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.311061                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      351.967739                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5296     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        38656                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      355.735099                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     216.399320                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.915140                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12161     31.46%     31.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8166     21.12%     52.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4096     10.60%     63.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2818      7.29%     70.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2687      6.95%     77.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1672      4.33%     81.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1300      3.36%     85.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1153      2.98%     88.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4603     11.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38656                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5291                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.313362                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      352.121472                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5289     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5298                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5297                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.259581                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.243681                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.749380                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4690     88.54%     88.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  4      0.08%     88.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                472      8.91%     97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                106      2.00%     99.53% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5291                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5291                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.277641                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.260577                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.779844                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4640     87.70%     87.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  6      0.11%     87.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                513      9.70%     97.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                107      2.02%     99.53% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::20                 18      0.34%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  5      0.09%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5297                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1693807750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4108807750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    644000000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13150.68                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::21                  4      0.08%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5291                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1688662500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4103362500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    643920000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13112.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31900.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         144.48                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          96.62                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      144.49                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       96.65                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31862.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         144.63                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          96.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      144.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       96.76                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.88                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.89                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.13                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.75                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112096                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64121                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.03                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.42                       # Row buffer hit rate for writes
-system.physmem.avgGap                       265409.53                       # Average gap between requests
-system.physmem.pageHitRate                      81.98                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  151956000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   82912500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 512405400                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        23.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112105                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64137                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.05                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                       265116.18                       # Average gap between requests
+system.physmem.pageHitRate                      82.00                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  152069400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   82974375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 512194800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                278951040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3726219120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11612859660                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24043349250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              40408652970                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              708.301006                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    39871864500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1905020000                       # Time in different power states
+system.physmem_0.refreshEnergy             3721642080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11693696490                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            23930394000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              40371922185                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              708.527477                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    39682710000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1902680000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15273243000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     15394661250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  140638680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76737375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 491797800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                279151920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3726219120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11026970910                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24557286750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              40298802555                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              706.375499                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40728832250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1905020000                       # Time in different power states
+system.physmem_1.actEnergy                  140086800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   76436250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 491673000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                279138960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3721642080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11090732535                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24459309750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              40259019375                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              706.546032                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40563908250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1902680000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14416275250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14513554250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14816555                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9915062                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            392110                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9527196                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6742365                       # Number of BTB hits
+system.cpu.branchPred.lookups                14800511                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9905691                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            381680                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9439152                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6732150                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.769668                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1716488                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             71.321555                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1714112                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -403,97 +404,97 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        114107581                       # number of cpu cycles simulated
+system.cpu.numCycles                        113972449                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915128                       # Number of instructions committed
 system.cpu.committedOps                      90690084                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1163698                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1144886                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.609072                       # CPI: cycles per instruction
-system.cpu.ipc                               0.621476                       # IPC: instructions per cycle
-system.cpu.tickCycles                        95702284                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        18405297                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            156420                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.153595                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42625103                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160516                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.550493                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         823362500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.153595                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992957                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992957                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.607167                       # CPI: cycles per instruction
+system.cpu.ipc                               0.622213                       # IPC: instructions per cycle
+system.cpu.tickCycles                        95596263                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18376186                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156435                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.140403                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42624247                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160531                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.520348                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         822680500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.140403                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992954                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992954                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1109                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1113                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2936                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86018450                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86018450                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22867482                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22867482                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642183                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642183                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83600                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83600                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86016733                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86016733                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22866807                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22866807                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642189                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642189                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83413                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83413                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42509665                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42509665                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42593265                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42593265                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        51591                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         51591                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207718                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207718                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        44555                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        44555                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       259309                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         259309                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       303864                       # number of overall misses
-system.cpu.dcache.overall_misses::total        303864                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1486882500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1486882500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16821632500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16821632500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18308515000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18308515000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18308515000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18308515000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22919073                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22919073                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42508996                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42508996                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42592409                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42592409                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        51550                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         51550                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207712                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207712                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        44592                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        44592                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       259262                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         259262                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       303854                       # number of overall misses
+system.cpu.dcache.overall_misses::total        303854                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1489104500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1489104500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  16802314000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  16802314000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18291418500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18291418500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18291418500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18291418500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22918357                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22918357                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128155                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128155                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128005                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128005                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42768974                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42768974                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42897129                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42897129                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002251                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002251                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     42768258                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42768258                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42896263                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42896263                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002249                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002249                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.347665                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.347665                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006063                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006063                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007084                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007084                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28820.579171                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28820.579171                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80983.027470                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80983.027470                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70605.011781                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70605.011781                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60252.333281                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60252.333281                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348361                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.348361                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007083                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007083                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70551.868380                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60198.050709                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -502,110 +503,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128380                       # number of writebacks
-system.cpu.dcache.writebacks::total            128380                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22097                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        22097                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100690                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100690                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       122787                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       122787                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       122787                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       122787                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29494                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29494                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       128400                       # number of writebacks
+system.cpu.dcache.writebacks::total            128400                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22032                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22032                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100684                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100684                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       122716                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       122716                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       122716                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       122716                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29518                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29518                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107028                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       107028                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23994                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        23994                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136522                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136522                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       160516                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160516                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    572555000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    572555000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8494060500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8494060500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1717129000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1717129000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9066615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9066615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10783744500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10783744500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001287                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001287                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23985                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        23985                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136546                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136546                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160531                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160531                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    574723500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    574723500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8485443000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8485443000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1719503000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1719503000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9060166500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9060166500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10779669500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10779669500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001288                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187226                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187226                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003192                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003192                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187375                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187375                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003193                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003193                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.592392                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.592392                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79362.975109                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79362.975109                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71564.932900                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71564.932900                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66411.387908                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66411.387908                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67181.742007                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67181.742007                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             42980                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.974873                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24976744                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             45022                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            554.767536                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             42865                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1852.538301                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24941041                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             44907                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            555.393168                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.974873                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.904773                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.904773                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1852.538301                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.904560                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.904560                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          914                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1007                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          918                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1004                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50088556                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50088556                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24976744                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24976744                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24976744                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24976744                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24976744                       # number of overall hits
-system.cpu.icache.overall_hits::total        24976744                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        45023                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         45023                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        45023                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          45023                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        45023                       # number of overall misses
-system.cpu.icache.overall_misses::total         45023                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    929482000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    929482000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    929482000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    929482000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    929482000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    929482000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25021767                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25021767                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25021767                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25021767                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25021767                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25021767                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001799                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001799                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001799                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001799                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001799                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001799                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20644.603869                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20644.603869                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20644.603869                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20644.603869                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20644.603869                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20644.603869                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          50016805                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         50016805                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     24941041                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        24941041                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      24941041                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         24941041                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     24941041                       # number of overall hits
+system.cpu.icache.overall_hits::total        24941041                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        44908                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         44908                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        44908                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          44908                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        44908                       # number of overall misses
+system.cpu.icache.overall_misses::total         44908                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    926324500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    926324500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    926324500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    926324500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    926324500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    926324500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24985949                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24985949                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     24985949                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     24985949                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24985949                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24985949                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001797                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001797                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001797                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001797                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001797                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001797                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20627.159971                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20627.159971                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20627.159971                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20627.159971                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20627.159971                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20627.159971                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -614,129 +615,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45023                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        45023                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        45023                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        45023                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        45023                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        45023                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    884460000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    884460000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    884460000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    884460000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    884460000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    884460000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001799                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001799                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001799                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001799                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19644.626080                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19644.626080                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19644.626080                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19644.626080                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19644.626080                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19644.626080                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44908                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        44908                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        44908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        44908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        44908                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        44908                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    881417500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    881417500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    881417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    881417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    881417500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    881417500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001797                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001797                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001797                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19627.182239                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19627.182239                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19627.182239                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19627.182239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19627.182239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19627.182239                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95667                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29860.905352                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             161834                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126786                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.276434                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            95654                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29860.809495                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             161643                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           126772                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.275069                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26582.278991                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1621.458035                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1657.168326                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.811227                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049483                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.050573                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.911283                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31119                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1810                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12715                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 26579.265460                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1620.835593                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1660.708442                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.811135                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049464                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.050681                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.911280                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31118                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1806                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12714                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15870                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          601                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949677                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3410862                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3410862                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       128380                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       128380                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4747                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4747                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        40023                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        40023                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31889                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        31889                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        40023                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        36636                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           76659                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        40023                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        36636                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          76659                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102281                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102281                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         5000                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         5000                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21599                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        21599                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         5000                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       123880                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        128880                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         5000                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       123880                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128880                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8283634000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8283634000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    396631500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    396631500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1874203500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1874203500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    396631500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10157837500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10554469000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    396631500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10157837500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10554469000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       128380                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       128380                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          604                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949646                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3409200                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3409200                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks       128400                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       128400                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        39917                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        39917                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31903                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        31903                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        39917                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        36655                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           76572                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        39917                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        36655                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          76572                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102276                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102276                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4991                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         4991                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21600                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        21600                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         4991                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       123876                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        128867                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4991                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       123876                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       128867                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8274960000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8274960000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    394876000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    394876000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1878573500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1878573500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    394876000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10153533500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10548409500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    394876000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10153533500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10548409500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks       128400                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       128400                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       107028                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       107028                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        45023                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        45023                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        53488                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        53488                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        45023                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       160516                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       205539                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        45023                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       160516                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       205539                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955647                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955647                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111054                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111054                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403810                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403810                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111054                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771761                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.627034                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111054                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771761                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.627034                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80988.981336                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80988.981336                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79326.300000                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79326.300000                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86772.697810                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86772.697810                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79326.300000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81997.396674                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81893.769398                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79326.300000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81997.396674                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81893.769398                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        44908                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        44908                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        53503                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        53503                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        44908                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       160531                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       205439                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        44908                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       160531                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       205439                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955600                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955600                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111138                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111138                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403716                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403716                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111138                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771664                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.627276                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111138                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771664                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.627276                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80908.130940                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80908.130940                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79117.611701                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79117.611701                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86970.995370                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86970.995370                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79117.611701                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81965.299977                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81855.009428                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79117.611701                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81965.299977                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81855.009428                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -745,126 +746,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        86160                       # number of writebacks
-system.cpu.l2cache.writebacks::total            86160                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        86157                       # number of writebacks
+system.cpu.l2cache.writebacks::total            86157                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           10                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           10                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           64                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           64                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           65                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           65                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           75                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           74                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1376                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1376                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102281                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102281                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4990                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4990                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data           65                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           75                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1374                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1374                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102276                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102276                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4981                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4981                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21535                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21535                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         4990                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       123816                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       128806                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         4990                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       123816                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128806                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7260824000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7260824000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    346082000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    346082000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1654286500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1654286500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    346082000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8915110500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9261192500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    346082000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8915110500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9261192500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4981                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       123811                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       128792                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4981                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       123811                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       128792                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7252200000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7252200000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    344388000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    344388000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1658643500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1658643500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    344388000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8910843500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9255231500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    344388000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8910843500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9255231500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955647                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955647                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110832                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402614                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402614                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771362                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.626674                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.110832                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771362                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.626674                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70988.981336                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70988.981336                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69355.110220                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76818.504760                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76818.504760                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72002.895425                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71900.319085                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69355.110220                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72002.895425                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71900.319085                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955600                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955600                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.110916                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110916                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402501                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402501                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.110916                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771259                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.626911                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.110916                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771259                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.626911                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp         98510                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       214540                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        72719                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         98410                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       214557                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        72583                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       107028                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       107028                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        45023                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        53488                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       129456                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473213                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            602669                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2881408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18489344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           21370752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       95667                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       500606                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.191102                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.393170                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        44908                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        53503                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       129101                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473262                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            602363                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2874048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18491584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           21365632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       95654                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       500393                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.191158                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.393213                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             404939     80.89%     80.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              95667     19.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             404739     80.88%     80.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              95654     19.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         500606                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      330849500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         500393                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      330769500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      67538489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      67366488                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     240805936                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     240828935                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              26524                       # Transaction distribution
-system.membus.trans_dist::Writeback             86160                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7518                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102281                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102281                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         26524                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       351288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 351288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13757760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13757760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              26515                       # Transaction distribution
+system.membus.trans_dist::Writeback             86157                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7510                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102276                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102276                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         26515                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       351249                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 351249                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13756672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13756672                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            222483                       # Request fanout histogram
+system.membus.snoop_fanout::samples            222458                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  222483    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  222458    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              222483                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           591579500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              222458                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           591536000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          679724750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          679701000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 4695f21d9..af3d3e8bc 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -688,7 +688,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
index e5802151f..dc295a8fa 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index baff53399..46df80677 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.209315                       # Number of seconds simulated
-sim_ticks                                1209314565500                       # Number of ticks simulated
-final_tick                               1209314565500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.208801                       # Number of seconds simulated
+sim_ticks                                1208800797500                       # Number of ticks simulated
+final_tick                               1208800797500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 310001                       # Simulator instruction rate (inst/s)
-host_op_rate                                   310001                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              205263152                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296916                       # Number of bytes of host memory used
-host_seconds                                  5891.53                       # Real time elapsed on the host
+host_inst_rate                                 239332                       # Simulator instruction rate (inst/s)
+host_op_rate                                   239332                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              158403619                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 291552                       # Number of bytes of host memory used
+host_seconds                                  7631.14                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             61312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         124968128                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125029440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65415808                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65415808                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                958                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1952627                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1953585                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1022122                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1022122                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                50700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            103337983                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103388683                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           50700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              50700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54093294                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54093294                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54093294                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               50700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           103337983                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              157481977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1953585                       # Number of read requests accepted
-system.physmem.writeReqs                      1022122                       # Number of write requests accepted
-system.physmem.readBursts                     1953585                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1022122                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                124947328                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     82112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65414528                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125029440                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65415808                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1283                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             61248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124969728                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125030976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65417024                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65417024                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                957                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1952652                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1953609                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1022141                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022141                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                50668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            103383228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103433896                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           50668                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              50668                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54117291                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54117291                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54117291                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               50668                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           103383228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              157551187                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1953609                       # Number of read requests accepted
+system.physmem.writeReqs                      1022141                       # Number of write requests accepted
+system.physmem.readBursts                     1953609                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1022141                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                124949504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     81472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65415744                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125030976                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65417024                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1273                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118324                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113533                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              115739                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117256                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117310                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117130                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119399                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124116                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126631                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118329                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113529                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              115744                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117255                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117308                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117125                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119396                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124121                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126643                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              129581                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128158                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             129926                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             125582                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             124841                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122135                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             122641                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128162                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             129917                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125585                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             124851                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122145                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             122645                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               61422                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61664                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60721                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61393                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61822                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63305                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64352                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65861                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65572                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66032                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65638                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65947                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64508                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64525                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64898                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64442                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61663                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60725                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61394                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61815                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63308                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64356                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65855                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65579                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66031                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65643                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65948                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64510                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64527                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64896                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64449                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1209314463000                       # Total gap between requests
+system.physmem.totGap                    1208800695000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1953585                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1953609                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1022122                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1829869                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    122416                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1022141                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1830062                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    122257                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    31995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    60176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    60206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    60194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    60633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    30676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    32058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60694                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -193,29 +193,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1831684                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.926852                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.136404                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.467751                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1453241     79.34%     79.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       261868     14.30%     93.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48841      2.67%     96.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20589      1.12%     97.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13172      0.72%     98.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7181      0.39%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5391      0.29%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4514      0.25%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16887      0.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1831684                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59621                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.743530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      149.210927                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59467     99.74%     99.74% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          109      0.18%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            6      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            6      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            6      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1831783                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.923052                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.128953                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.461416                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1453465     79.35%     79.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       261783     14.29%     93.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        48685      2.66%     96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20654      1.13%     97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13128      0.72%     98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7168      0.39%     98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5621      0.31%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4509      0.25%     99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16770      0.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1831783                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59616                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.746846                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      147.774131                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59455     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          113      0.19%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           11      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            8      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            4      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-3583            3      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3584-4095            3      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
@@ -225,104 +225,103 @@ system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # R
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10752-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-13823            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59621                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59621                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.143322                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.107211                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.116873                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27512     46.14%     46.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1216      2.04%     48.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              26386     44.26%     92.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3971      6.66%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                453      0.76%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 62      0.10%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 10      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  9      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59621                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36542895500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73148558000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9761510000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18717.85                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           59616                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59616                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.145079                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.109083                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.114634                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27440     46.03%     46.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1214      2.04%     48.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              26474     44.41%     92.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3953      6.63%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                450      0.75%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 71      0.12%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 11      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59616                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36544132750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73150432750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9761680000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18718.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37467.85                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         103.32                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          54.09                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      103.39                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       54.09                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37468.16                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         103.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          54.12                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      103.43                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       54.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.77                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     723569                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    419148                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     723493                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    419177                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.06                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  41.01                       # Row buffer hit rate for writes
-system.physmem.avgGap                       406395.68                       # Average gap between requests
+system.physmem.avgGap                       406217.15                       # Average gap between requests
 system.physmem.pageHitRate                      38.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6717619440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3665367750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7353894600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3243499200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            78986487840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           416110602285                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           360579035250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             876656506365                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              724.920562                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   597088834750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     40381640000                       # Time in different power states
+system.physmem_0.actEnergy                 6716750040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3664893375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7353886800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3243486240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            78952922880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           415155955455                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           361108109250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             876196004040                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              724.847786                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   597970225000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     40364480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    571843431500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    570465308750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7129911600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3890328750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7873975200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3379721760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            78986487840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           426511213875                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           351455691750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             879227330775                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              727.046416                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   581836550250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     40381640000                       # Time in different power states
+system.physmem_1.actEnergy                 7131529440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3891211500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7874240400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3379857840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            78952922880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           426545221500                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           351117525000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             878892508560                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              727.078515                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   581276348750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     40364480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    587095716000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    587159309750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               246216332                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186427958                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15694657                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            167633562                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               165258832                       # Number of BTB hits
+system.cpu.branchPred.lookups               246104681                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186361047                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15590665                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            167674402                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165200232                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.583380                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18428300                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104795                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.524420                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18413418                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104179                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452931478                       # DTB read hits
-system.cpu.dtb.read_misses                    4979966                       # DTB read misses
+system.cpu.dtb.read_hits                    452862393                       # DTB read hits
+system.cpu.dtb.read_misses                    4979628                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457911444                       # DTB read accesses
-system.cpu.dtb.write_hits                   161379324                       # DTB write hits
-system.cpu.dtb.write_misses                   1710368                       # DTB write misses
+system.cpu.dtb.read_accesses                457842021                       # DTB read accesses
+system.cpu.dtb.write_hits                   161378642                       # DTB write hits
+system.cpu.dtb.write_misses                   1709394                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163089692                       # DTB write accesses
-system.cpu.dtb.data_hits                    614310802                       # DTB hits
-system.cpu.dtb.data_misses                    6690334                       # DTB misses
+system.cpu.dtb.write_accesses               163088036                       # DTB write accesses
+system.cpu.dtb.data_hits                    614241035                       # DTB hits
+system.cpu.dtb.data_misses                    6689022                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                621001136                       # DTB accesses
-system.cpu.itb.fetch_hits                   598312460                       # ITB hits
+system.cpu.dtb.data_accesses                620930057                       # DTB accesses
+system.cpu.itb.fetch_hits                   597998986                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               598312479                       # ITB accesses
+system.cpu.itb.fetch_accesses               597999005                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -336,82 +335,82 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2418629131                       # number of cpu cycles simulated
+system.cpu.numCycles                       2417601595                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      52090489                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      51825441                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.324276                       # CPI: cycles per instruction
-system.cpu.ipc                               0.755130                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2076311536                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       342317595                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9121994                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.733344                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           601608000                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126090                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.921769                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       16821289500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4080.733344                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.996273                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996273                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.323713                       # CPI: cycles per instruction
+system.cpu.ipc                               0.755451                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2075284528                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       342317067                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9121986                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.726688                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           601540360                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126082                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.914415                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       16821281500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4080.726688                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.996271                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1558                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2405                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1562                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2407                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1231414126                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1231414126                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    443125970                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       443125970                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    158482030                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158482030                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     601608000                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        601608000                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    601608000                       # number of overall hits
-system.cpu.dcache.overall_hits::total       601608000                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7289546                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289546                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2246472                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2246472                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9536018                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9536018                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9536018                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9536018                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 185444020000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 185444020000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108463697500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108463697500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 293907717500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 293907717500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 293907717500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 293907717500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    450415516                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    450415516                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1231278878                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1231278878                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    443058336                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       443058336                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158482024                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158482024                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     601540360                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        601540360                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    601540360                       # number of overall hits
+system.cpu.dcache.overall_hits::total       601540360                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7289560                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289560                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2246478                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2246478                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9536038                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9536038                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9536038                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9536038                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 185462944500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 185462944500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 108451503000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 108451503000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 293914447500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 293914447500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 293914447500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 293914447500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    450347896                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    450347896                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    611144018                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    611144018                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    611144018                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    611144018                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016184                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.016184                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    611076398                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    611076398                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    611076398                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    611076398                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016187                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.016187                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013977                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.015604                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015604                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015604                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015604                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25439.721486                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25439.721486                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48281.793630                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48281.793630                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30820.801460                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30820.801460                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30820.801460                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30820.801460                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015605                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015605                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015605                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015605                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25442.268738                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25442.268738                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48276.236402                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48276.236402                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30821.442563                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30821.442563                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30821.442563                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30821.442563                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -420,100 +419,100 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3686660                       # number of writebacks
-system.cpu.dcache.writebacks::total           3686660                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50795                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50795                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359133                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       359133                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       409928                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       409928                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       409928                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       409928                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238751                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238751                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887339                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887339                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9126090                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126090                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9126090                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126090                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176979090000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 176979090000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83292376000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83292376000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260271466000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 260271466000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260271466000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 260271466000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016071                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016071                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks      3686591                       # number of writebacks
+system.cpu.dcache.writebacks::total           3686591                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50801                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50801                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359155                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       359155                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       409956                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       409956                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       409956                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       409956                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238759                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238759                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887323                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887323                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9126082                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126082                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9126082                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126082                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176998396500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 176998396500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83275965000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83275965000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260274361500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 260274361500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260274361500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 260274361500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016074                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011742                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014933                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014933                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014933                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014933                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.843454                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.843454                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44132.175513                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44132.175513                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.493671                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.493671                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.493671                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.493671                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014934                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014934                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24451.483535                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24451.483535                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44123.854263                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44123.854263                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.835949                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.835949                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.835949                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.835949                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           751.748828                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           598311502                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          624542.277662                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           749.172343                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           597998029                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               957                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          624867.323929                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   751.748828                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.367065                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.367065                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          875                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1196625878                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1196625878                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    598311502                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       598311502                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     598311502                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        598311502                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    598311502                       # number of overall hits
-system.cpu.icache.overall_hits::total       598311502                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
-system.cpu.icache.overall_misses::total           958                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     76821500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     76821500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     76821500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     76821500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     76821500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     76821500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    598312460                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    598312460                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    598312460                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    598312460                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    598312460                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    598312460                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst   749.172343                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.365807                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.365807                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          873                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1195998929                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1195998929                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    597998029                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       597998029                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     597998029                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        597998029                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    597998029                       # number of overall hits
+system.cpu.icache.overall_hits::total       597998029                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          957                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           957                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            957                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          957                       # number of overall misses
+system.cpu.icache.overall_misses::total           957                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     77181000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     77181000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     77181000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     77181000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     77181000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     77181000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    597998986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    597998986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    597998986                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    597998986                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    597998986                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    597998986                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80189.457203                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 80189.457203                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 80189.457203                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 80189.457203                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 80189.457203                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 80189.457203                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80648.902821                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 80648.902821                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 80648.902821                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 80648.902821                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 80648.902821                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 80648.902821                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -522,125 +521,125 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          958                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          958                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          958                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75863500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75863500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75863500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75863500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75863500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75863500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          957                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          957                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          957                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          957                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76224000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     76224000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76224000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     76224000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76224000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     76224000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79189.457203                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79189.457203                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79189.457203                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 79189.457203                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79189.457203                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 79189.457203                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79648.902821                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79648.902821                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79648.902821                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 79648.902821                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79648.902821                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 79648.902821                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1920858                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30765.976815                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14409764                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1950662                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.387115                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      89228358000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14799.543915                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.897848                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.535052                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.451646                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001309                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.485948                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.938903                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1920882                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30765.249465                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14409739                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1950686                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.387011                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      89219766000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14798.314674                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.741446                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.193345                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.451609                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001304                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.485968                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.938881                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29804                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1217                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12865                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15535                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15534                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149830361                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149830361                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3686660                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3686660                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106821                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106821                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066642                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6066642                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7173463                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7173463                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7173463                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7173463                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       780518                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       780518                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          958                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          958                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172109                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1172109                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1952627                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1953585                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          958                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1952627                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1953585                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68770136000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  68770136000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74424500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     74424500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102393190500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 102393190500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     74424500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 171163326500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 171237751000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74424500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 171163326500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 171237751000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3686660                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3686660                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887339                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887339                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          958                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          958                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238751                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7238751                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          958                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9126090                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9127048                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          958                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9126090                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9127048                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.tag_accesses        149830233                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149830233                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      3686591                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3686591                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1106811                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1106811                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066619                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6066619                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7173430                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7173430                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7173430                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7173430                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       780512                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       780512                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          957                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          957                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172140                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1172140                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1952652                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1953609                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          957                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1952652                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1953609                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68753946000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  68753946000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74786500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     74786500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102412790500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 102412790500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     74786500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 171166736500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 171241523000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     74786500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 171166736500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 171241523000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      3686591                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3686591                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887323                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1887323                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          957                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          957                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238759                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7238759                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          957                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9126082                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9127039                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          957                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9126082                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9127039                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413555                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.413555                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161921                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161921                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161926                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161926                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.213961                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214043                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.213964                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214046                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.213961                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214043                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88108.328059                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88108.328059                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77687.369520                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77687.369520                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87358.078899                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87358.078899                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77687.369520                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87657.973848                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87653.084458                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77687.369520                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87657.973848                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87653.084458                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.213964                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214046                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88088.262576                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88088.262576                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78146.812957                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78146.812957                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87372.490061                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87372.490061                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78146.812957                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87658.597897                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87653.938429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78146.812957                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87658.597897                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87653.938429                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -649,116 +648,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1022122                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1022122                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1022141                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022141                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          245                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          245                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780518                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       780518                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          958                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          958                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172109                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172109                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1952627                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1953585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1952627                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1953585                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60964956000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60964956000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64844500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64844500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90672100500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90672100500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64844500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151637056500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 151701901000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64844500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151637056500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 151701901000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780512                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       780512                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          957                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          957                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172140                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172140                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1952652                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1953609                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1952652                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1953609                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60948826000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60948826000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65216500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65216500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90691390500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90691390500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65216500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151640216500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 151705433000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65216500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151640216500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 151705433000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413555                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413555                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161921                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161921                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161926                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161926                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213961                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214043                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213964                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214046                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213961                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214043                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78108.328059                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78108.328059                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67687.369520                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67687.369520                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77358.078899                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77358.078899                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67687.369520                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77657.973848                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.084458                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67687.369520                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77657.973848                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.084458                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213964                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214046                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78088.262576                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78088.262576                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68146.812957                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68146.812957                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77372.490061                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77372.490061                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68146.812957                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77658.597897                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.938429                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       7239709                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4708782                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6334073                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          958                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238751                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1919                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374174                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27376093                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820016000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820077312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1920858                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20169903                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.095234                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.293538                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7239716                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4708732                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6334139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          957                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238759                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1917                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374150                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27376067                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820011072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          820072320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1920882                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20169910                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.095235                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.293539                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           18249045     90.48%     90.48% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1920858      9.52%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18249028     90.48%     90.48% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1920882      9.52%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20169903                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12811182500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       20169910                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12811105000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1437000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1435500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13689135000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13689123000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1173067                       # Transaction distribution
-system.membus.trans_dist::Writeback           1022122                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           897712                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            780518                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           780518                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1173067                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827004                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5827004                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190445248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190445248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1173097                       # Transaction distribution
+system.membus.trans_dist::Writeback           1022141                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897719                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            780512                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780512                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1173097                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827078                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5827078                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190448000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190448000                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3873419                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3873469                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3873419    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3873469    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3873419                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8427454000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3873469                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8428000500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10685206000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10685481750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 0be38fe21..88e337781 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -497,7 +497,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -546,7 +546,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -609,7 +609,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 488ad0a2f..abe06b1e2 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:36:02
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:26:54
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -24,4 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 672881519500 because target called exit()
+Exiting @ tick 669556582000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index fd8f8a2dd..cb7ba764c 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.671755                       # Number of seconds simulated
-sim_ticks                                671754803000                       # Number of ticks simulated
-final_tick                               671754803000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.669557                       # Number of seconds simulated
+sim_ticks                                669556582000                       # Number of ticks simulated
+final_tick                               669556582000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168955                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168955                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               65376371                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298196                       # Number of bytes of host memory used
-host_seconds                                 10275.19                       # Real time elapsed on the host
+host_inst_rate                                 125035                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125035                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48223337                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292576                       # Number of bytes of host memory used
+host_seconds                                 13884.49                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             62400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125486976                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125549376                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        62400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           62400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65552256                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65552256                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                975                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1960734                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961709                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1024254                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1024254                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                92891                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            186804732                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               186897623                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           92891                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              92891                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          97583606                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               97583606                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          97583606                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               92891                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           186804732                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              284481229                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961709                       # Number of read requests accepted
-system.physmem.writeReqs                      1024254                       # Number of write requests accepted
-system.physmem.readBursts                     1961709                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1024254                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125464000                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     85376                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65551040                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125549376                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65552256                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1334                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             60864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125490304                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125551168                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        60864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           60864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65555584                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65555584                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                951                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1960786                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961737                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1024306                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1024306                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                90902                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            187423001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               187513903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           90902                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90902                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97908953                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97908953                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97908953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               90902                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           187423001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              285422856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961737                       # Number of read requests accepted
+system.physmem.writeReqs                      1024306                       # Number of write requests accepted
+system.physmem.readBursts                     1961737                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1024306                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125467392                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83776                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65553984                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125551168                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65555584                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1309                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118672                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113926                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116092                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117630                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117777                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117495                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119900                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124641                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127326                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130085                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128786                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130484                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126296                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125416                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122597                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123252                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61496                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61762                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60827                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61508                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61962                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63415                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64494                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65970                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65774                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66157                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65800                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              66076                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118679                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113901                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116111                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117641                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117753                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117515                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119854                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124644                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127345                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130108                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128796                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130507                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126297                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125432                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122623                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123222                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61508                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61766                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60825                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61511                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61967                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63434                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64481                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65996                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65770                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66159                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65809                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66083                       # Per bank write bursts
 system.physmem.perBankWrBursts::12              64701                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64671                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              65003                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64619                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64659                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65023                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64589                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    671754707500                       # Total gap between requests
+system.physmem.totGap                    669556486500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961709                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961737                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1024254                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1618535                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    241019                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     69861                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     30932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1024306                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1618471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    241016                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     69944                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     30981                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    27711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49355                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    56824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59458                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    65054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    26250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    27792                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56790                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61507                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63649                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    65159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,150 +193,149 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1769993                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      107.917046                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.949504                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     137.477186                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1374954     77.68%     77.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       271630     15.35%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53313      3.01%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21496      1.21%     97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12783      0.72%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6453      0.36%     98.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4820      0.27%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3869      0.22%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20675      1.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1769993                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60112                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.611592                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      146.109791                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59940     99.71%     99.71% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          128      0.21%     99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1769592                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.945804                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.951779                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     137.536097                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1374979     77.70%     77.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       270914     15.31%     93.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53662      3.03%     96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21295      1.20%     97.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12785      0.72%     97.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6489      0.37%     98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4949      0.28%     98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3948      0.22%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20571      1.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1769592                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60107                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.574625                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      148.683386                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59945     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          118      0.20%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            7      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            6      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            4      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            6      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            5      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            3      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607            1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-8703            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60112                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60112                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.038778                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.996488                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.239516                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              31933     53.12%     53.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1463      2.43%     55.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              20988     34.91%     90.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4635      7.71%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                815      1.36%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                185      0.31%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 40      0.07%     99.91% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::14848-15359            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60107                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60107                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.040960                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.998792                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.235687                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              31915     53.10%     53.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1364      2.27%     55.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              21027     34.98%     90.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4732      7.87%     98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                816      1.36%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                161      0.27%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 44      0.07%     99.92% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::23                 14      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 10      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  8      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.00%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::26                  3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  3      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  2      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::35                  1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60112                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40612494250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77369525500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9801875000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20716.70                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::36                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60107                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40555708000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77313733000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9802140000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20687.17                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39466.70                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         186.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          97.58                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      186.90                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       97.58                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39437.17                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         187.39                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          97.91                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      187.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       97.91                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.22                       # Data bus utilization in percentage
+system.physmem.busUtil                           2.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     792670                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    421939                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.19                       # Row buffer hit rate for writes
-system.physmem.avgGap                       224970.87                       # Average gap between requests
-system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6484688280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3538272375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7379814000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3249285840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            43875505440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           305078205825                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           135438254250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             505044026010                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.831975                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   223329404750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     22431240000                       # Time in different power states
+system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     792895                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    422217                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.44                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       224228.68                       # Average gap between requests
+system.physmem.pageHitRate                      40.71                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6483387960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3537562875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7379541000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3249642240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            43732091520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           304280359155                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           134820686250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             503483271000                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.966482                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   222309059500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     22357920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    425992710250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    424888778500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 6896405880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3762919875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7910526000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3387653280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            43875505440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           312108901605                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           129270987000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             507212899080                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              755.060642                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   213031369750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     22431240000                       # Time in different power states
+system.physmem_1.actEnergy                 6894704880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3761991750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7911610200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3387698640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            43732091520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           311328000180                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           128638545000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             505654642170                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              755.209486                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   211980924500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22357920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    436288612000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    435216639250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               410738673                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         319032195                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          16276977                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            282876736                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               279471264                       # Number of BTB hits
+system.cpu.branchPred.lookups               409355418                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         318166975                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15963047                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282312141                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               278580615                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.796129                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                26377862                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.678227                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26172204                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 20                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    646528255                       # DTB read hits
-system.cpu.dtb.read_misses                   12150594                       # DTB read misses
+system.cpu.dtb.read_hits                    644928587                       # DTB read hits
+system.cpu.dtb.read_misses                   12158902                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                658678849                       # DTB read accesses
-system.cpu.dtb.write_hits                   218209856                       # DTB write hits
-system.cpu.dtb.write_misses                   7511426                       # DTB write misses
+system.cpu.dtb.read_accesses                657087489                       # DTB read accesses
+system.cpu.dtb.write_hits                   218092717                       # DTB write hits
+system.cpu.dtb.write_misses                   7512154                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               225721282                       # DTB write accesses
-system.cpu.dtb.data_hits                    864738111                       # DTB hits
-system.cpu.dtb.data_misses                   19662020                       # DTB misses
+system.cpu.dtb.write_accesses               225604871                       # DTB write accesses
+system.cpu.dtb.data_hits                    863021304                       # DTB hits
+system.cpu.dtb.data_misses                   19671056                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                884400131                       # DTB accesses
-system.cpu.itb.fetch_hits                   422614397                       # ITB hits
-system.cpu.itb.fetch_misses                        44                       # ITB misses
+system.cpu.dtb.data_accesses                882692360                       # DTB accesses
+system.cpu.itb.fetch_hits                   420625120                       # ITB hits
+system.cpu.itb.fetch_misses                        37                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               422614441                       # ITB accesses
+system.cpu.itb.fetch_accesses               420625157                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -350,238 +349,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1343509607                       # number of cpu cycles simulated
+system.cpu.numCycles                       1339113165                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          433913722                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3420789895                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   410738673                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          305849126                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     886512749                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                46016020                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                   29                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1692                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           55                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 422614397                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8419525                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1343436257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.546299                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.150257                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          431760554                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3410003764                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   409355418                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          304752819                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     884588278                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                45380492                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1660                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           27                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 420625120                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8288982                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1339040790                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.546602                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.150665                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                716181443     53.31%     53.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 48040729      3.58%     56.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 24412482      1.82%     58.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 45272149      3.37%     62.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                143062816     10.65%     72.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 66221905      4.93%     77.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 43789018      3.26%     80.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 29632862      2.21%     83.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                226822853     16.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                714026661     53.32%     53.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 47659433      3.56%     56.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24224234      1.81%     58.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45105968      3.37%     62.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                142792146     10.66%     72.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 65943853      4.92%     77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43594254      3.26%     80.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29429342      2.20%     83.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226264899     16.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1343436257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.305721                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.546160                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                355607674                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             404003493                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 525762782                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              35055109                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               23007199                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             62310513                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   875                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3265200378                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2135                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               23007199                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                373983702                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               211600441                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6939                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 538809166                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             196028810                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3182220984                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1833786                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20271739                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents              149993150                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30859152                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2378179455                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4128151916                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4127979405                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            172510                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1339040790                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305691                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.546464                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                353769612                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             403558275                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 524215531                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              34807834                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               22689538                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62027781                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   752                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3256129377                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2069                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               22689538                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                372008249                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               212535269                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7646                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 537155328                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             194644760                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3173788478                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1809495                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20462310                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              148566154                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30882701                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2371842618                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4117718959                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4117582524                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            136434                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1001976492                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                195                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            195                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  99605318                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            719399499                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           272964536                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          90785513                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         58783416                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2890757443                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 174                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2624793649                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1589988                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1154713835                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    506306579                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            145                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1343436257                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.953791                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.147325                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                995639655                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                143                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            142                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99637264                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            717251547                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272457871                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90453848                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         58428187                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2884203449                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 122                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2620051581                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1544935                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1148159789                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    502731368                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             93                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1339040790                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.956663                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.148213                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           538259461     40.07%     40.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           170012804     12.66%     52.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           158478310     11.80%     64.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           149374624     11.12%     75.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           126330762      9.40%     85.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            84386661      6.28%     91.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            68107665      5.07%     96.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            34089750      2.54%     98.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            14396220      1.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           535540081     39.99%     39.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           169652118     12.67%     52.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           157969981     11.80%     64.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149186997     11.14%     75.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           125999252      9.41%     85.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84166081      6.29%     91.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68019052      5.08%     96.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            34101039      2.55%     98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14406189      1.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1343436257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1339040790                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                13176390     35.76%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               19068779     51.75%     87.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4600766     12.49%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13157777     35.84%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18965028     51.65%     87.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4592425     12.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1719677353     65.52%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                  114      0.00%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              897887      0.03%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  16      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 158      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 22      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            673327193     25.65%     91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           230890880      8.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1716938805     65.53%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              896154      0.03%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 163      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 30      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            671533572     25.63%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230682699      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2624793649                       # Type of FU issued
-system.cpu.iq.rate                           1.953684                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36845935                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014038                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6629473751                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4044314699                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2522399915                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1985727                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1304235                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       894550                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2660653801                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  985783                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         69567792                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2620051581                       # Type of FU issued
+system.cpu.iq.rate                           1.956557                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36715230                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014013                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6615464746                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4031257680                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2518620612                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1939371                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1248863                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       886699                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2655799836                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  966975                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69396280                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    274803836                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       379517                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       149864                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    112236034                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    272655884                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       373351                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       145486                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    111729369                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          312                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       6300661                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          229                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6306976                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               23007199                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               150535686                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              19606000                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3042042837                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6687461                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             719399499                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            272964536                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                174                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 810054                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              19058140                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         149864                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10895731                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8841524                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19737255                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2579092054                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             658678856                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          45701595                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               22689538                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               149806110                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              21267531                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3035207367                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6595956                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             717251547                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272457871                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                122                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 801675                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              20722786                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         145486                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10633585                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8701131                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19334716                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2574896999                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             657087498                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45154582                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     151285220                       # number of nop insts executed
-system.cpu.iew.exec_refs                    884400225                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                315980786                       # Number of branches executed
-system.cpu.iew.exec_stores                  225721369                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.919668                       # Inst execution rate
-system.cpu.iew.wb_sent                     2553280591                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2523294465                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1489396348                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1920808747                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     151003796                       # number of nop insts executed
+system.cpu.iew.exec_refs                    882692437                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315488895                       # Number of branches executed
+system.cpu.iew.exec_stores                  225604939                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.922837                       # Inst execution rate
+system.cpu.iew.wb_sent                     2549331117                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2519507311                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1487495376                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918378348                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.878137                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.775401                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.881475                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775392                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts      1006176660                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       998666714                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16276166                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1204408845                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.510932                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.544476                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15962339                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1201055691                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.515150                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.548433                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    715098033     59.37%     59.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    159881136     13.27%     72.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     79829015      6.63%     79.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     52096588      4.33%     83.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28578407      2.37%     85.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     19544658      1.62%     87.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     20010855      1.66%     89.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     23112076      1.92%     91.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106258077      8.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    712334289     59.31%     59.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159635442     13.29%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79514551      6.62%     79.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52029279      4.33%     83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28475742      2.37%     85.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19476450      1.62%     87.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19964545      1.66%     89.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23047887      1.92%     91.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106577506      8.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1204408845                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1201055691                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -627,344 +626,343 @@ system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             106258077                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3838328354                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5791077348                       # The number of ROB writes
-system.cpu.timesIdled                             692                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           73350                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events             106577506                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3827145825                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5775013033                       # The number of ROB writes
+system.cpu.timesIdled                             710                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           72375                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.773892                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.773892                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.292171                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.292171                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3468538615                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2022734233                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     46009                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      540                       # number of floating regfile writes
+system.cpu.cpi                               0.771359                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.771359                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.296413                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.296413                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3463596666                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2019349968                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     39643                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      588                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9208722                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.471997                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           713777147                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9212818                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             77.476527                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5130746500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.471997                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997918                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997918                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9207223                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.441459                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           712346742                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9211319                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.333848                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5127954500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.441459                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997911                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997911                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          709                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2958                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          707                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2960                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1473023486                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1473023486                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    558278644                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       558278644                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155498498                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155498498                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            5                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            5                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     713777142                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        713777142                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    713777142                       # number of overall hits
-system.cpu.dcache.overall_hits::total       713777142                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12898182                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12898182                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5230004                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5230004                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1470153653                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1470153653                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    556848599                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       556848599                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155498140                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155498140                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     712346739                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        712346739                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    712346739                       # number of overall hits
+system.cpu.dcache.overall_hits::total       712346739                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12894062                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12894062                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5230362                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5230362                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     18128186                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       18128186                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     18128186                       # number of overall misses
-system.cpu.dcache.overall_misses::total      18128186                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 411532558500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 411532558500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 315240579886                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 315240579886                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     18124424                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       18124424                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     18124424                       # number of overall misses
+system.cpu.dcache.overall_misses::total      18124424                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 412011773000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 412011773000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 315105865697                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 315105865697                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 726773138386                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 726773138386                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 726773138386                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 726773138386                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    571176826                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    571176826                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 727117638697                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 727117638697                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 727117638697                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 727117638697                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    569742661                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    569742661                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    731905328                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    731905328                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    731905328                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    731905328                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022582                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022582                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032539                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032539                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.166667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.166667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024768                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024768                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.024768                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.024768                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31906.245275                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31906.245275                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60275.399385                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60275.399385                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    730471163                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    730471163                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    730471163                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    730471163                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022631                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022631                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032542                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032542                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024812                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024812                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024812                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024812                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31953.605698                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31953.605698                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60245.517556                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60245.517556                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40090.781195                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40090.781195                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40090.781195                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40090.781195                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     15662934                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      9568706                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1102908                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67982                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.201487                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   140.753523                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40118.110164                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40118.110164                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40118.110164                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40118.110164                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     15661523                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      9569226                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1103711                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           68026                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.189877                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   140.670126                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3728522                       # number of writebacks
-system.cpu.dcache.writebacks::total           3728522                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5564399                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5564399                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3350970                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3350970                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      8915369                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      8915369                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      8915369                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      8915369                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7333783                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7333783                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879034                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1879034                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3727748                       # number of writebacks
+system.cpu.dcache.writebacks::total           3727748                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5561934                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5561934                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3351172                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3351172                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8913106                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8913106                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8913106                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8913106                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332128                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7332128                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879190                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879190                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9212817                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9212817                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9212817                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9212817                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183008143000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 183008143000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84351384400                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84351384400                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9211318                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9211318                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9211318                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9211318                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182959853500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 182959853500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84331903655                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84331903655                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267359527400                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 267359527400                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267359527400                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 267359527400                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012840                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012840                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011691                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011691                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.166667                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.166667                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012587                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012587                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012587                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012587                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.125722                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.125722                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44890.823902                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44890.823902                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267291757155                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 267291757155                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267291757155                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 267291757155                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012869                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012869                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012610                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012610                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24953.172326                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24953.172326                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.730748                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.730748                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29020.388378                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29020.388378                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29020.388378                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29020.388378                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.753719                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.753719                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.753719                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.753719                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           774.831914                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           422612882                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               975                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          433449.109744                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           755.106219                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           420623640                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               951                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          442296.151420                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   774.831914                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.378336                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.378336                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          974                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   755.106219                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.368704                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.368704                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          950                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          909                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.475586                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         845229769                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        845229769                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    422612882                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       422612882                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     422612882                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        422612882                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    422612882                       # number of overall hits
-system.cpu.icache.overall_hits::total       422612882                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1515                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1515                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1515                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1515                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1515                       # number of overall misses
-system.cpu.icache.overall_misses::total          1515                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    116523500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    116523500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    116523500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    116523500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    116523500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    116523500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    422614397                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    422614397                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    422614397                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    422614397                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    422614397                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    422614397                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          886                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.463867                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         841251191                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        841251191                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    420623640                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       420623640                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     420623640                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        420623640                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    420623640                       # number of overall hits
+system.cpu.icache.overall_hits::total       420623640                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1480                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1480                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1480                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1480                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1480                       # number of overall misses
+system.cpu.icache.overall_misses::total          1480                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    114807500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    114807500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    114807500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    114807500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    114807500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    114807500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    420625120                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    420625120                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    420625120                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    420625120                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    420625120                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    420625120                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76913.201320                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76913.201320                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76913.201320                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76913.201320                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76913.201320                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76913.201320                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          961                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77572.635135                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77572.635135                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77572.635135                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77572.635135                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77572.635135                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77572.635135                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          288                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   120.125000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    57.600000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          540                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          540                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          540                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          540                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          540                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          975                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          975                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          975                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          975                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     82864500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     82864500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     82864500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     82864500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     82864500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     82864500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          529                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          529                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          529                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          529                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          529                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          951                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          951                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          951                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          951                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          951                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          951                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79672000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     79672000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     79672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     79672000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     79672000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84989.230769                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84989.230769                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84989.230769                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 84989.230769                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84989.230769                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 84989.230769                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83777.076761                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 83777.076761                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 83777.076761                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1929005                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31411.908280                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14583396                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1958793                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.445093                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      28154888000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14369.814431                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.748786                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17015.345063                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.438532                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000816                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.519267                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958615                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29788                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          974                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1929031                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31408.547403                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14580190                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1958818                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.443361                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      28140218000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14352.760847                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.833600                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.952956                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.438012                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000788                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.519713                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.958513                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29787                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          975                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10555                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909058                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        151217969                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       151217969                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3728522                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3728522                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106786                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106786                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6145298                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6145298                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7252084                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7252084                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7252084                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7252084                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       772262                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       772262                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          975                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          975                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1188472                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1188472                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          975                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1960734                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1961709                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          975                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1960734                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1961709                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  69352569000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  69352569000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     81396500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     81396500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106533689500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 106533689500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     81396500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 175886258500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 175967655000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     81396500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 175886258500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 175967655000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3728522                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3728522                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879048                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1879048                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          975                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          975                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7333770                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7333770                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          975                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9212818                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9213793                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          975                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9212818                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9213793                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.410986                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.410986                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17547                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10494                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909027                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        151193976                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       151193976                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      3727748                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3727748                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1106790                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1106790                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6143743                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6143743                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7250533                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7250533                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7250533                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7250533                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       772416                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       772416                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          951                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          951                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1188370                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1188370                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          951                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1960786                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1961737                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          951                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1960786                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1961737                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  69332440500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  69332440500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     78240000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     78240000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106503228500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 106503228500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     78240000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 175835669000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 175913909000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     78240000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 175835669000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 175913909000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      3727748                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3727748                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879206                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1879206                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          951                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          951                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7332113                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7332113                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          951                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9211319                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9212270                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          951                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9211319                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9212270                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411033                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.411033                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162055                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162055                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162077                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162077                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.212827                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.212910                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.212867                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.212948                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.212827                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.212910                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89804.456260                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89804.456260                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83483.589744                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83483.589744                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89639.208580                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89639.208580                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83483.589744                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89704.293647                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89701.201860                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83483.589744                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89704.293647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89701.201860                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.212867                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.212948                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89760.492403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89760.492403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82271.293375                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82271.293375                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89621.269891                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89621.269891                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82271.293375                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89676.114069                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89672.524401                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82271.293375                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89676.114069                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89672.524401                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -973,116 +971,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1024254                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1024254                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1024306                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1024306                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          241                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          241                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772262                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       772262                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          975                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          975                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188472                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188472                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1960734                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1961709                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1960734                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1961709                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61629949000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61629949000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     71646500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     71646500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94648969500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94648969500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71646500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156278918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 156350565000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71646500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156278918500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 156350565000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772416                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       772416                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          951                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          951                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188370                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188370                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          951                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1960786                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1961737                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          951                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1960786                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961737                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61608280500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61608280500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68730000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68730000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94619528500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94619528500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68730000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156227809000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 156296539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68730000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156227809000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 156296539000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.410986                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.410986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411033                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411033                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162055                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162055                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162077                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162077                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212827                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.212910                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212867                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.212948                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212827                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.212910                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79804.456260                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79804.456260                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73483.589744                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79639.208580                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79639.208580                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79704.293647                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79701.201860                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73483.589744                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79704.293647                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79701.201860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212867                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.212948                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79760.492403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79760.492403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72271.293375                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79621.269891                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79621.269891                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79676.114069                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79672.524401                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       7334745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4752776                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6384952                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1879048                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1879048                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          975                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7333770                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1951                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27634358                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27636309                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        62400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828245760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          828308160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1929005                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20351521                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.094784                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.292917                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7333064                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4752054                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6384201                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879206                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879206                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          951                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332113                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1903                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629861                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27631764                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        60864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828100288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          828161152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1929031                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20348525                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.094800                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.292938                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           18422516     90.52%     90.52% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            1929005      9.48%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18419494     90.52%     90.52% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            1929031      9.48%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20351521                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12939780000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       20348525                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12937495000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1462500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1426500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13819227000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13816978500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1189447                       # Transaction distribution
-system.membus.trans_dist::Writeback           1024254                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1189321                       # Transaction distribution
+system.membus.trans_dist::Writeback           1024306                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           903687                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            772262                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           772262                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1189447                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851359                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5851359                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191101632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               191101632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            772416                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           772416                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1189321                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851467                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5851467                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191106752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               191106752                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3889650                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3889730                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3889650    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3889730    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3889650                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8475841500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3889730                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8475633500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10684260000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10684578250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index a70b71696..97b7b2c5a 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -118,7 +118,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -167,7 +167,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
index ca8e0ac4e..cb09befab 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -759,7 +759,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
index b4e05a41a..1664fb28c 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 02:59:16
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x2c50960
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
 Loading Input Data
@@ -25,4 +27,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1121241432500 because target called exit()
+Exiting @ tick 1116876142500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 27ca4a2ca..bd1131ae5 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.117365                       # Number of seconds simulated
-sim_ticks                                1117365374500                       # Number of ticks simulated
-final_tick                               1117365374500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.116876                       # Number of seconds simulated
+sim_ticks                                1116876142500                       # Number of ticks simulated
+final_tick                               1116876142500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 236504                       # Simulator instruction rate (inst/s)
-host_op_rate                                   254797                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              171091237                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314716                       # Number of bytes of host memory used
-host_seconds                                  6530.82                       # Real time elapsed on the host
+host_inst_rate                                 161785                       # Simulator instruction rate (inst/s)
+host_op_rate                                   174299                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              116987267                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309392                       # Number of bytes of host memory used
+host_seconds                                  9546.99                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             50752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         130973248                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131024000                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67225152                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67225152                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2046457                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2047250                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1050393                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1050393                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                45421                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            117216133                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               117261554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           45421                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              45421                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          60163984                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               60163984                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          60163984                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               45421                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           117216133                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177425537                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2047250                       # Number of read requests accepted
-system.physmem.writeReqs                      1050393                       # Number of write requests accepted
-system.physmem.readBursts                     2047250                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1050393                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                130939136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     84864                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67223488                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131024000                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67225152                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1326                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             50368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         130931520                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            130981888                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67207936                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          67207936                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                787                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2045805                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2046592                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1050124                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1050124                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                45097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            117230116                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               117275213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           45097                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              45097                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          60174923                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               60174923                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          60174923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               45097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           117230116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177450137                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2046592                       # Number of read requests accepted
+system.physmem.writeReqs                      1050124                       # Number of write requests accepted
+system.physmem.readBursts                     2046592                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1050124                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                130897216                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     84672                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  67206464                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 130981888                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               67207936                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1323                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              127156                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              124552                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              121687                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              123679                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              122821                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              122785                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              123231                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              123758                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131446                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              133531                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132174                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133285                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             133312                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133367                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129415                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             129725                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               66071                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64336                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               62582                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               63010                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               63074                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63174                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64441                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65447                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67324                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67820                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67591                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67884                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67359                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67795                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66531                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              65928                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              127284                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              124662                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              121597                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              123658                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              122617                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              122675                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              123246                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              123759                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131397                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              133511                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132080                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133309                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             133252                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133368                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129308                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             129546                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               66136                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               64410                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               62576                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               63006                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               63000                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63100                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64443                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65435                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67311                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67795                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67548                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67883                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67328                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67793                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66483                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              65854                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1117365281000                       # Total gap between requests
+system.physmem.totGap                    1116876049000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2047250                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2046592                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1050393                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1917221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    128684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1050124                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1916546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    128705                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    61237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    32789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    34054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    61212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61641                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                    61693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61770                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61700                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61641                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61718                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62548                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62535                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
@@ -193,106 +193,106 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1911200                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.683951                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.827915                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.443095                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1486351     77.77%     77.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305207     15.97%     93.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52508      2.75%     96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21149      1.11%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13340      0.70%     98.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7581      0.40%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5505      0.29%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5122      0.27%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        14437      0.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1911200                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61162                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.403649                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      159.275472                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          61115     99.92%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           22      0.04%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            5      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1910492                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.692259                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.833601                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.494474                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1485528     77.76%     77.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       305524     15.99%     93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52470      2.75%     96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20903      1.09%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13406      0.70%     98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7575      0.40%     98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5481      0.29%     98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5100      0.27%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        14505      0.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1910492                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61132                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.413630                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      160.636391                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          61087     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           20      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61162                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61162                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.173523                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.138356                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.100510                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27168     44.42%     44.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1036      1.69%     46.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28675     46.88%     93.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3829      6.26%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                390      0.64%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 50      0.08%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  9      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61132                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61132                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.177599                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.142637                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.096979                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              26963     44.11%     44.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1122      1.84%     45.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28754     47.04%     92.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3885      6.36%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                352      0.58%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 46      0.08%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  8      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61162                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38200049000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76561124000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10229620000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18671.29                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::26                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61132                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38139021250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76487815000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10226345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18647.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37421.29                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         117.19                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          60.16                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      117.26                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       60.16                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37397.44                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         117.20                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          60.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      117.28                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       60.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.39                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.71                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     773325                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    411756                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.80                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                       360714.67                       # Average gap between requests
-system.physmem.pageHitRate                      38.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7043954400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3843427500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7719106200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3318634800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            72980394240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           421878506670                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           300346094250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             817130118060                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              731.305386                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   496942671500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     37311040000                       # Time in different power states
+system.physmem.avgWrQLen                        24.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     773003                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    411872                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.79                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       360664.67                       # Average gap between requests
+system.physmem.pageHitRate                      38.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 7041119400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3841880625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7718053200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3318446880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            72948863520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           420554384415                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           301217964750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             816640712790                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              731.183278                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   498392390000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     37294920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    583108431500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    581188236250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7404702480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4040264250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8238734400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3487743360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            72980394240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           429447905460                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           293706270750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             819306014940                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.252744                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   485853174500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     37311040000                       # Time in different power states
+system.physmem_1.actEnergy                 7402200120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 4038898875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                8234990400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3486207600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            72948863520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           429475728015                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           293392224750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             818979113280                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              733.276976                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   485326311500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     37294920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    594197830000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    594254742500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               239770012                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186474623                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14592511                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            129773424                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122091028                       # Number of BTB hits
+system.cpu.branchPred.lookups               239639069                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186342280                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14526140                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            130646098                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122079384                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.080147                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15653619                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             93.442809                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15657029                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -412,68 +412,68 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2234730749                       # number of cpu cycles simulated
+system.cpu.numCycles                       2233752285                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41613452                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41470092                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.446837                       # CPI: cycles per instruction
-system.cpu.ipc                               0.691163                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1834912752                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       399817997                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9221614                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.621118                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624237491                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9225710                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.662813                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.446203                       # CPI: cycles per instruction
+system.cpu.ipc                               0.691466                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1834122948                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       399629337                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9221039                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.616333                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624218905                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9225135                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.665016                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        9804990500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.621118                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997466                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997466                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616333                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997465                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          256                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1229                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2550                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          245                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1237                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2553                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276880692                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276880692                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    453906230                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453906230                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170331138                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170331138                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1276841915                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276841915                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    453887721                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453887721                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170331061                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170331061                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624237368                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624237368                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624237369                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624237369                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7335089                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7335089                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2254909                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2254909                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     624218782                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624218782                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624218783                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624218783                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7334497                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7334497                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2254986                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2254986                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9589998                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9589998                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9590000                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9590000                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 191000565000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 191000565000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109144177000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109144177000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 300144742000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 300144742000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 300144742000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 300144742000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461241319                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461241319                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9589483                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9589483                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9589485                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9589485                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 190949826000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109060330000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 300010156000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 300010156000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 300010156000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 300010156000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461222218                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461222218                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -482,28 +482,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    633827366                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633827366                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    633827369                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633827369                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015903                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.015903                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013065                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013065                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    633808265                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633808265                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    633808268                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633808268                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015902                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.015902                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013066                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013066                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.666667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.666667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015130                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26039.297546                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26039.297546                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48402.918699                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48402.918699                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31297.685568                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31297.685568                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31297.679041                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31297.679041                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31285.331649                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31285.325124                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -512,109 +512,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3684549                       # number of writebacks
-system.cpu.dcache.writebacks::total           3684549                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          211                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364078                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       364078                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       364289                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       364289                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       364289                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       364289                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334878                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7334878                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890831                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890831                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3684564                       # number of writebacks
+system.cpu.dcache.writebacks::total           3684564                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          215                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364134                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       364134                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       364349                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       364349                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       364349                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       364349                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334282                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7334282                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890852                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890852                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9225709                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9225709                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9225710                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9225710                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183660145000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 183660145000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84822237000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84822237000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9225134                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9225134                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9225135                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9225135                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84766639000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84766639000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        74000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        74000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268482382000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 268482382000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268482456000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 268482456000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 268376457500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 268376531500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010956                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014556                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014556                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014556                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014556                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25039.291042                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25039.291042                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44859.766420                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44859.766420                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014555                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014555                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014555                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014555                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        74000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        74000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29101.544608                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29101.544608                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29101.549474                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29101.549474                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                32                       # number of replacements
-system.cpu.icache.tags.tagsinuse           663.200919                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           465452181                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               826                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          563501.429782                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                29                       # number of replacements
+system.cpu.icache.tags.tagsinuse           661.386126                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           465281345                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          567416.274390                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   663.200919                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.323829                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.323829                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          794                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   661.386126                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.322942                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.322942                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          756                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.387695                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         930906840                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        930906840                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    465452181                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       465452181                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     465452181                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        465452181                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    465452181                       # number of overall hits
-system.cpu.icache.overall_hits::total       465452181                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          826                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           826                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          826                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            826                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          826                       # number of overall misses
-system.cpu.icache.overall_misses::total           826                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62820500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62820500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62820500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62820500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62820500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62820500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    465453007                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    465453007                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    465453007                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    465453007                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    465453007                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    465453007                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         930565150                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        930565150                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    465281345                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       465281345                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     465281345                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        465281345                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    465281345                       # number of overall hits
+system.cpu.icache.overall_hits::total       465281345                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
+system.cpu.icache.overall_misses::total           820                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62363500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62363500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62363500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62363500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62363500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62363500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    465282165                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    465282165                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    465282165                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    465282165                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    465282165                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    465282165                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.874092                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76053.874092                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.874092                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76053.874092                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.874092                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76053.874092                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76053.048780                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76053.048780                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -623,129 +623,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          826                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          826                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          826                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          826                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          826                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61994500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     61994500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61994500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     61994500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61994500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     61994500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61543500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     61543500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61543500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     61543500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61543500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     61543500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.874092                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.874092                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.874092                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.874092                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.874092                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.874092                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2014550                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31258.830192                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14509707                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2044325                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.097554                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      59776132000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14827.946363                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.755718                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16404.128111                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.452513                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000817                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.500614                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.953944                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          2013891                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31258.308104                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14509189                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2043666                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.099589                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      59769702000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.588444                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.452649                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000811                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.500467                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.953928                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1248                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1247                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15556                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15557                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        151507860                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       151507860                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3684549                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3684549                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1089532                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1089532                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses        151497950                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       151497950                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      3684564                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3684564                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1089696                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1089696                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           32                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total           32                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6089717                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6089717                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6089630                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6089630                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           32                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7179249                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7179281                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7179326                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7179358                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           32                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7179249                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7179281                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       801299                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       801299                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          794                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          794                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1245162                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1245162                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          794                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2046461                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2047255                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          794                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2046461                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2047255                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70488254000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  70488254000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     60418000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     60418000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108710111500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 108710111500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     60418000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 179198365500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 179258783500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     60418000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 179198365500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 179258783500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3684549                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3684549                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890831                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1890831                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          826                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          826                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7334879                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7334879                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          826                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9225710                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9226536                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          826                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9225710                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9226536                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423781                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.423781                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.961259                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.961259                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.169759                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.169759                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.961259                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.221822                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.221888                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.961259                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.221822                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.221888                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87967.480304                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87967.480304                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76093.198992                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76093.198992                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87305.998336                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87305.998336                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76093.198992                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87565.003926                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87560.554743                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76093.198992                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87565.003926                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87560.554743                       # average overall miss latency
+system.cpu.l2cache.overall_hits::cpu.data      7179326                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7179358                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       801156                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       801156                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          788                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          788                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1244653                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1244653                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          788                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2045809                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2046597                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          788                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2045809                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2046597                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70430633500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  70430633500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     59976000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     59976000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     59976000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 179152246500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     59976000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 179152246500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      3684564                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3684564                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890852                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1890852                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          820                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          820                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7334283                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7334283                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          820                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9225135                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9225955                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          820                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9225135                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9225955                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423701                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.423701                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.960976                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.960976                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.169703                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.169703                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.960976                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.221765                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.221830                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.960976                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.221765                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.221830                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -754,8 +754,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1050393                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1050393                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1050124                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1050124                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
@@ -766,114 +766,114 @@ system.cpu.l2cache.demand_mshr_hits::total            5                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          246                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          246                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       801299                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       801299                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          793                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          793                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1245158                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1245158                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          793                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2046457                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2047250                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          793                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2046457                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2047250                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62475264000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62475264000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     52472500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     52472500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  96258268000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  96258268000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     52472500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158733532000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 158786004500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     52472500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158733532000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 158786004500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          243                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          243                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       801156                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       801156                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          787                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          787                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1244649                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1244649                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          787                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2045805                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2046592                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          787                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2045805                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2046592                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62419073500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62419073500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     52090500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     52090500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  96214883500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  96214883500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     52090500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     52090500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423781                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423781                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.960048                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.960048                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.169758                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.169758                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960048                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221821                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.221887                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960048                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221821                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.221887                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77967.480304                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77967.480304                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66169.609079                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66169.609079                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77306.067182                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77306.067182                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66169.609079                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77565.046322                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77560.632312                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66169.609079                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77565.046322                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77560.632312                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423701                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423701                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.959756                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.169703                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.169703                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221764                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.221830                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221764                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.221830                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       7335705                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4734942                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6499660                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890831                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890831                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          826                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334879                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1684                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27671440                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27673124                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826256576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          826309440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2014550                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20462732                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.098450                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.297922                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7335103                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      4734688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6498677                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890852                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890852                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          820                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334283                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1669                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27669715                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27671384                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826220736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          826273216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2013891                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     20460914                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.098426                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.297890                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1           18448182     90.16%     90.16% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2            2014550      9.84%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1           18447023     90.16%     90.16% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2            2013891      9.84%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20462732                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12908640000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       20460914                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12908075500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1239499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1230499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13838566996                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13837704496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1245951                       # Transaction distribution
-system.membus.trans_dist::Writeback           1050393                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           963109                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            801299                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           801299                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1245951                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6108002                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6108002                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198249152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198249152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1245436                       # Transaction distribution
+system.membus.trans_dist::Writeback           1050124                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           962723                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            801156                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           801156                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1245436                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106031                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6106031                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189824                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198189824                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4060752                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4059439                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 4060752    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4059439    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             4060752                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8665729500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4059439                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8663029500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11195509250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11191724000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index eea4d6225..578352db1 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index bc5565f58..8ed495e8c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -156,7 +156,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -266,7 +266,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index b2f63d5fa..1497b3733 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -134,7 +134,7 @@ system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -200,7 +200,7 @@ system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
index 459f492af..5ec95ce79 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
index de77515a1..f0a9a7c93 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
index 4d57fab87..606ce3744 100644..100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout
@@ -3,12 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  7 2014 10:41:53
-gem5 started May  7 2014 15:05:33
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 20:55:41
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -25,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 51810251500 because target called exit()
+122 123 124 Exiting @ tick 51910606500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index f4338fb5a..5fb393485 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,57 +1,57 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.052057                       # Number of seconds simulated
-sim_ticks                                 52057006500                       # Number of ticks simulated
-final_tick                                52057006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.051911                       # Number of seconds simulated
+sim_ticks                                 51910606500                       # Number of ticks simulated
+final_tick                                51910606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 338250                       # Simulator instruction rate (inst/s)
-host_op_rate                                   338250                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              191596351                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300296                       # Number of bytes of host memory used
-host_seconds                                   271.70                       # Real time elapsed on the host
+host_inst_rate                                 229005                       # Simulator instruction rate (inst/s)
+host_op_rate                                   229005                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              129351336                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295204                       # Number of bytes of host memory used
+host_seconds                                   401.31                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            202816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            202752                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137664                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               340480                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       202816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202816                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3169                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               340416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202752                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2151                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5320                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3896037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2644486                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6540522                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3896037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3896037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3896037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2644486                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6540522                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5320                       # Number of read requests accepted
+system.physmem.num_reads::total                  5319                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3905791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2651944                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6557735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3905791                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3905791                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3905791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2651944                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6557735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5319                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5320                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5319                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   340480                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   340416                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    340480                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    340416                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 469                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 295                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 307                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 308                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 524                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 224                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 238                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 222                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 289                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 251                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                255                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                254                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                261                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                410                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                344                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     52056919000                       # Total gap between requests
+system.physmem.totGap                     51910519000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5320                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5319                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4923                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       378                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       379                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          973                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      348.809866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.712248                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.458818                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            301     30.94%     30.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          209     21.48%     52.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           98     10.07%     62.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           92      9.46%     71.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           72      7.40%     79.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           45      4.62%     83.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           24      2.47%     86.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           19      1.95%     88.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          113     11.61%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            973                       # Bytes accessed per row activation
-system.physmem.totQLat                       31528250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 131278250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26600000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5926.36                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          979                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      346.541369                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     213.036393                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.369108                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            309     31.56%     31.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          207     21.14%     52.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          105     10.73%     63.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           89      9.09%     72.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           71      7.25%     79.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           31      3.17%     82.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           27      2.76%     85.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           27      2.76%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          113     11.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            979                       # Bytes accessed per row activation
+system.physmem.totQLat                       35331250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 135062500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26595000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6642.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24676.36                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.54                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25392.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.56                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.56                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
@@ -216,70 +216,70 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4340                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4332                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.58                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9785135.15                       # Average gap between requests
-system.physmem.pageHitRate                      81.58                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3492720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1905750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19843200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      9759450.84                       # Average gap between requests
+system.physmem.pageHitRate                      81.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3507840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1914000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19835400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3399723600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1761174315                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            29685915000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              34872054585                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.954967                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    49382007750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1738100000                       # Time in different power states
+system.physmem_0.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1735578180                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            29619604500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              34770500880                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.907929                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    49271576750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       931384250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       898679500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3825360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2087250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  21231600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3848040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2099625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  21216000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3399723600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1805818995                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            29646744750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              34879431555                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.096868                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    49317281000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1738100000                       # Time in different power states
+system.physmem_1.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1825261695                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            29540934750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              34783421070                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.156857                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    49142723000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       996955000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1030068000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                11466165                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8229222                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            788767                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6698071                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5372970                       # Number of BTB hits
+system.cpu.branchPred.lookups                11441088                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8207826                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            765853                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6077536                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5340604                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.216677                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1174312                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             87.874494                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1173808                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20431374                       # DTB read hits
-system.cpu.dtb.read_misses                      46957                       # DTB read misses
+system.cpu.dtb.read_hits                     20417089                       # DTB read hits
+system.cpu.dtb.read_misses                      43350                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20478331                       # DTB read accesses
-system.cpu.dtb.write_hits                     6580300                       # DTB write hits
-system.cpu.dtb.write_misses                       270                       # DTB write misses
+system.cpu.dtb.read_accesses                 20460439                       # DTB read accesses
+system.cpu.dtb.write_hits                     6579898                       # DTB write hits
+system.cpu.dtb.write_misses                       278                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6580570                       # DTB write accesses
-system.cpu.dtb.data_hits                     27011674                       # DTB hits
-system.cpu.dtb.data_misses                      47227                       # DTB misses
+system.cpu.dtb.write_accesses                 6580176                       # DTB write accesses
+system.cpu.dtb.data_hits                     26996987                       # DTB hits
+system.cpu.dtb.data_misses                      43628                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 27058901                       # DTB accesses
-system.cpu.itb.fetch_hits                    23067346                       # ITB hits
-system.cpu.itb.fetch_misses                        89                       # ITB misses
+system.cpu.dtb.data_accesses                 27040615                       # DTB accesses
+system.cpu.itb.fetch_hits                    22953519                       # ITB hits
+system.cpu.itb.fetch_misses                        90                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                23067435                       # ITB accesses
+system.cpu.itb.fetch_accesses                22953609                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,67 +293,67 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        104114013                       # number of cpu cycles simulated
+system.cpu.numCycles                        103821213                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2234090                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2183676                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.132867                       # CPI: cycles per instruction
-system.cpu.ipc                               0.882716                       # IPC: instructions per cycle
-system.cpu.tickCycles                       102384742                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         1729271                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.129681                       # CPI: cycles per instruction
+system.cpu.ipc                               0.885205                       # IPC: instructions per cycle
+system.cpu.tickCycles                       102104321                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         1716892                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1448.483845                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26587292                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1447.424804                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26573200                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11922.552466                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11916.233184                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1448.483845                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353634                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353634                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1447.424804                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353375                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353375                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          227                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53183674                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53183674                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20089099                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20089099                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          53155492                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53155492                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20075007                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20075007                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6498193                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        6498193                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26587292                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26587292                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26587292                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26587292                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          520                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           520                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      26573200                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26573200                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26573200                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26573200                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          521                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           521                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         2910                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         2910                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         3430                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3430                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         3430                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     40189000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     40189000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    213917000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    213917000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    254106000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    254106000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    254106000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    254106000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20089619                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20089619                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         3431                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3431                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3431                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3431                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     40212500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     40212500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    214035000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    214035000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    254247500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    254247500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    254247500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    254247500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20075528                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20075528                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     26590722                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26590722                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     26590722                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26590722                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     26576631                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26576631                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26576631                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26576631                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000448                       # miss rate for WriteReq accesses
@@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000129
 system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74083.381924                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74083.381924                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 74103.031186                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 74103.031186                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -380,14 +380,14 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           35                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           35                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           36                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           36                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1165                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1200                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1200                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1200                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1200                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1201                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1201                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1201                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1201                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1745                       # number of WriteReq MSHR misses
@@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2230
 system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2230                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36729500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36729500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    130660500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    130660500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    167390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    167390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    167390000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    167390000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     37107000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     37107000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131707500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    131707500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168814500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    168814500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168814500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    168814500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000268                       # mshr miss rate for WriteReq accesses
@@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             13848                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1641.495432                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            23051532                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15813                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1457.758300                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13850                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1640.456656                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22937703                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15815                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1450.376415                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1641.495432                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801511                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801511                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.456656                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801004                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801004                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          668                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          950                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          671                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          946                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          46150505                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         46150505                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     23051532                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        23051532                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      23051532                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         23051532                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     23051532                       # number of overall hits
-system.cpu.icache.overall_hits::total        23051532                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        15814                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         15814                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        15814                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          15814                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        15814                       # number of overall misses
-system.cpu.icache.overall_misses::total         15814                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    406574500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    406574500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    406574500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    406574500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    406574500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    406574500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     23067346                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     23067346                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     23067346                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     23067346                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     23067346                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     23067346                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000686                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000686                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000686                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000686                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000686                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000686                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25709.782471                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25709.782471                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25709.782471                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25709.782471                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25709.782471                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25709.782471                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          45922853                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45922853                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22937703                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22937703                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22937703                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22937703                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22937703                       # number of overall hits
+system.cpu.icache.overall_hits::total        22937703                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15816                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15816                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        15816                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          15816                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15816                       # number of overall misses
+system.cpu.icache.overall_misses::total         15816                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    408931500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    408931500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    408931500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    408931500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    408931500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    408931500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22953519                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22953519                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22953519                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22953519                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22953519                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22953519                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000689                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000689                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000689                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000689                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000689                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000689                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25855.557663                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25855.557663                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,129 +483,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15814                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15814                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15814                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15814                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15814                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15814                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    390761500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    390761500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    390761500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    390761500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    390761500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    390761500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000686                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000686                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24709.845706                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24709.845706                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24709.845706                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24709.845706                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24709.845706                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24709.845706                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15816                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15816                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15816                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15816                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15816                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15816                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    393116500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    393116500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    393116500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    393116500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    393116500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    393116500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000689                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000689                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000689                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24855.620890                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2480.527759                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              26609                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3667                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.256340                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2477.794194                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              26614                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3666                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.259684                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.782066                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.767657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   360.978036                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.781001                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2100.046720                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   359.966473                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064141                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.011016                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.075700                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3667                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064088                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.010985                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.075616                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3666                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          769                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2507                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111908                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           261796                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          261796                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          770                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          183                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2505                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111877                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           261827                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          261827                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12644                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        12644                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12647                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        12647                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           53                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           53                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12644                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        12647                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           12723                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12644                       # number of overall hits
+system.cpu.l2cache.demand_hits::total           12726                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12647                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          12723                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          12726                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1719                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1719                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3169                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3169                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3168                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3168                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          432                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          432                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3169                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3168                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         2151                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5320                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3169                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          5319                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3168                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2151                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5320                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    127770000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    127770000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    234279500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    234279500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35439500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     35439500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    234279500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    163209500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    397489000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    234279500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    163209500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    397489000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total         5319                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128817000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    128817000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    236600000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    236600000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35817000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     35817000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    236600000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    164634000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    401234000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    236600000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    164634000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    401234000                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1745                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15813                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        15813                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15815                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        15815                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          485                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          485                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        15813                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        15815                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2230                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        18043                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        15813                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        18045                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15815                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2230                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        18043                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        18045                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985100                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.985100                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.200405                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.200405                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.200316                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.200316                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.890722                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.890722                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200405                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200316                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964574                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.294851                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200405                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.294763                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200316                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964574                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.294851                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74328.097731                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74328.097731                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73928.526349                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73928.526349                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82035.879630                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82035.879630                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73928.526349                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75876.104138                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74715.977444                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73928.526349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75876.104138                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74715.977444                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.294763                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -616,106 +616,106 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3169                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3169                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3168                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3168                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          432                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          432                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3169                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3168                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         2151                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5320                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3169                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5319                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2151                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5320                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    110580000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    110580000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    202589500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    202589500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31119500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31119500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    202589500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    141699500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    344289000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    202589500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    141699500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    344289000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         5319                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111627000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111627000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    204920000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    204920000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31497000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31497000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    204920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    143124000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    348044000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    204920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    143124000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    348044000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985100                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200405                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200405                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200316                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.890722                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.890722                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200405                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.294851                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200405                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.294763                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.294851                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.294763                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp         16298                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         16300                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        13898                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        13900                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        15813                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        15815                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          485                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45474                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45480                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4617                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             50091                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             50097                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012160                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1161600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1161728                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        32048                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        32052                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              32048    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              32052    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          32048                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       16131000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          32052                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       16133000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      23719500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      23722500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3345000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3601                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3600                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3601                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10640                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10640                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  340480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3600                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10638                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10638                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  340416                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5320                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5319                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5320    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5319    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5320                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6410500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5319                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6413000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28166750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           28165750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 4e01cb733..1d39a1715 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -497,7 +497,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -546,7 +546,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 462b428af..a140d0429 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,13 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:19:48
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:18:12
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
 
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -24,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 22228749500 because target called exit()
+122 123 124 Exiting @ tick 21919473500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 2afb0af07..f7c0c31d6 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022173                       # Number of seconds simulated
-sim_ticks                                 22172615500                       # Number of ticks simulated
-final_tick                                22172615500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.021919                       # Number of seconds simulated
+sim_ticks                                 21919473500                       # Number of ticks simulated
+final_tick                                21919473500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 207826                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207826                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54740698                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301824                       # Number of bytes of host memory used
-host_seconds                                   405.05                       # Real time elapsed on the host
+host_inst_rate                                 134628                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134628                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               35055621                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296224                       # Number of bytes of host memory used
+host_seconds                                   625.28                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            196224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138432                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334656                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       196224                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          196224                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3066                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2163                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5229                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8849836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6243377                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15093213                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8849836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8849836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8849836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6243377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15093213                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5229                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            195776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138496                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               334272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       195776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          195776                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3059                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5223                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8931601                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6318400                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15250001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8931601                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8931601                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8931601                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6318400                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15250001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5223                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5229                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5223                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334272                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334656                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334272                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 472                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 470                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 217                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 224                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 217                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 285                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 223                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                248                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                253                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                398                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                251                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                396                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                493                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                489                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                449                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22172520500                       # Total gap between requests
+system.physmem.totGap                     21919378500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5229                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5223                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       514                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       227                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3272                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          863                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      385.112399                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     228.773233                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     362.004147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            257     29.78%     29.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          196     22.71%     52.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           76      8.81%     61.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           57      6.60%     67.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           37      4.29%     72.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           34      3.94%     76.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           29      3.36%     79.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           50      5.79%     85.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          127     14.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            863                       # Bytes accessed per row activation
-system.physmem.totQLat                       43111750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 141155500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26145000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8244.74                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          860                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      387.497674                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     231.928894                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     358.454487                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            254     29.53%     29.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          187     21.74%     51.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           83      9.65%     60.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           58      6.74%     67.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           36      4.19%     71.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           34      3.95%     75.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           40      4.65%     80.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           50      5.81%     86.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          118     13.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            860                       # Bytes accessed per row activation
+system.physmem.totQLat                       44538500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 142469750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26115000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8527.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26994.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.09                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27277.38                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.09                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.25                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4356                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4358                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.30                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4240298.43                       # Average gap between requests
-system.physmem.pageHitRate                      83.30                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                      4196702.76                       # Average gap between requests
+system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                    3160080                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                    1724250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19492200                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                  19741800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1447870320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              926205255                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            12488167500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              14886619605                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.545103                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    20772765250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       740220000                       # Time in different power states
+system.physmem_0.refreshEnergy             1431596400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              935708580                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            12330335250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              14722266360                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.680556                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    20510216250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       731900000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       654868750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       676644750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3311280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1806750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20810400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3341520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1823250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20872800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1447870320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              909735390                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            12502614750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              14886148890                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.523868                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    20796420250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       740220000                       # Time in different power states
+system.physmem_1.refreshEnergy             1431596400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              913464900                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            12349847250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              14720946120                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.620322                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    20542312250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       731900000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       631087250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       644355250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16296711                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11841199                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            977322                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9230824                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7630427                       # Number of BTB hits
+system.cpu.branchPred.lookups                16112018                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11701868                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            926184                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8628002                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7529875                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.662469                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1605836                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                456                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             87.272523                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1595504                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                407                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     24148862                       # DTB read hits
-system.cpu.dtb.read_misses                     238971                       # DTB read misses
+system.cpu.dtb.read_hits                     24062707                       # DTB read hits
+system.cpu.dtb.read_misses                     205786                       # DTB read misses
 system.cpu.dtb.read_acv                             2                       # DTB read access violations
-system.cpu.dtb.read_accesses                 24387833                       # DTB read accesses
-system.cpu.dtb.write_hits                     7164238                       # DTB write hits
-system.cpu.dtb.write_misses                      1251                       # DTB write misses
-system.cpu.dtb.write_acv                            1                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7165489                       # DTB write accesses
-system.cpu.dtb.data_hits                     31313100                       # DTB hits
-system.cpu.dtb.data_misses                     240222                       # DTB misses
-system.cpu.dtb.data_acv                             3                       # DTB access violations
-system.cpu.dtb.data_accesses                 31553322                       # DTB accesses
-system.cpu.itb.fetch_hits                    16134293                       # ITB hits
-system.cpu.itb.fetch_misses                        87                       # ITB misses
+system.cpu.dtb.read_accesses                 24268493                       # DTB read accesses
+system.cpu.dtb.write_hits                     7162407                       # DTB write hits
+system.cpu.dtb.write_misses                      1203                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7163610                       # DTB write accesses
+system.cpu.dtb.data_hits                     31225114                       # DTB hits
+system.cpu.dtb.data_misses                     206989                       # DTB misses
+system.cpu.dtb.data_acv                             2                       # DTB access violations
+system.cpu.dtb.data_accesses                 31432103                       # DTB accesses
+system.cpu.itb.fetch_hits                    15925407                       # ITB hits
+system.cpu.itb.fetch_misses                        77                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                16134380                       # ITB accesses
+system.cpu.itb.fetch_accesses                15925484                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,239 +293,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         44345232                       # number of cpu cycles simulated
+system.cpu.numCycles                         43838948                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16871286                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      139358892                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16296711                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9236263                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      26208155                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2034698                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                          2                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  152                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2379                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles            9                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  16134293                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                382507                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           44099332                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.160113                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.432013                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           16632320                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      137954260                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16112018                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9125379                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      25989721                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1930958                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2266                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  15925407                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                365179                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           43589931                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.164819                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.433135                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19660436     44.58%     44.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2660444      6.03%     50.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1334517      3.03%     53.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1958294      4.44%     58.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3041312      6.90%     64.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1304304      2.96%     67.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1378179      3.13%     71.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   896078      2.03%     73.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11865768     26.91%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19407451     44.52%     44.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2621129      6.01%     50.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1337584      3.07%     53.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1925835      4.42%     58.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3007413      6.90%     64.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1288266      2.96%     67.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1362128      3.12%     71.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   884292      2.03%     73.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11755833     26.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44099332                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367496                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.142590                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13096074                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8205573                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19698619                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2093424                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1005642                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2679978                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12191                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              133453867                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 48806                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1005642                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 14231650                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4726220                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9532                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20537255                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3589033                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              129931841                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 72505                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1962504                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1321371                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  55153                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            95440121                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             168856219                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        161261081                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7595137                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43589931                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367527                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.146842                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12848398                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8248987                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19437203                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2101434                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 953909                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2651089                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11974                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              132128383                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 49953                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 953909                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13970899                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4649700                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          10898                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20300581                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3703944                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              128750721                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 69632                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2039237                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1388591                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  55010                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            94550726                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             167277672                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        159796203                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7481468                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27012760                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                775                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            786                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8114171                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             27101259                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8744711                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3477099                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1649521                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  112647261                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1499                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 100144647                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            120164                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        28469050                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     21866284                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1110                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44099332                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.270888                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.097444                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 26123365                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                949                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            946                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8314647                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26912240                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8709829                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3514186                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1623457                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111857121                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1283                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  99743085                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            115820                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27678694                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21106490                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            894                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43589931                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.288214                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.099779                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11543505     26.18%     26.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7764590     17.61%     43.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7534716     17.09%     60.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5714671     12.96%     73.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4493321     10.19%     84.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2994712      6.79%     90.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2021459      4.58%     95.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1167850      2.65%     98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              864508      1.96%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11253194     25.82%     25.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7641118     17.53%     43.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7479948     17.16%     60.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5719610     13.12%     73.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4459621     10.23%     83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2975044      6.83%     90.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2026173      4.65%     95.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1169285      2.68%     98.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              865938      1.99%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44099332                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43589931                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  476525     19.98%     19.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     19.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   437      0.02%     20.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 34852      1.46%     21.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                11487      0.48%     21.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1008602     42.30%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 692685     29.05%     93.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                159938      6.71%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  482162     20.24%     20.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     20.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   537      0.02%     20.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 34275      1.44%     21.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                12320      0.52%     22.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1010506     42.41%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 685066     28.75%     93.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                157661      6.62%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60907964     60.82%     60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               491070      0.49%     61.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2843610      2.84%     64.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115460      0.12%     64.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2441189      2.44%     66.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             314170      0.31%     67.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              765827      0.76%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24997693     24.96%     92.74% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7267338      7.26%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60678292     60.83%     60.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               490564      0.49%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2838989      2.85%     64.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115355      0.12%     64.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2438911      2.45%     66.73% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             313691      0.31%     67.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              766049      0.77%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24838081     24.90%     92.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7262827      7.28%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              100144647                       # Type of FU issued
-system.cpu.iq.rate                           2.258296                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2384526                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023811                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          231229628                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         131456710                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     90023404                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15663688                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9702849                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7180664                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               94162135                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8367031                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1912696                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               99743085                       # Type of FU issued
+system.cpu.iq.rate                           2.275216                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2382527                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023887                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          229948900                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         130065304                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     89786778                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15625548                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9512793                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7169302                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               93776538                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8349067                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1917366                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      7105061                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11423                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        42083                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2243608                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6916042                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11056                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        41363                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2208726                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        42789                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42784                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1527                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1005642                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3713444                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                450339                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           123646937                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            273080                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              27101259                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8744711                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1499                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  41770                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                401874                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          42083                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         559712                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       524057                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1083769                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              98766968                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24388350                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1377679                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 953909                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3616734                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                464700                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           122788755                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            239982                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              26912240                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8709829                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1283                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  38454                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                420547                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          41363                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         525246                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       502956                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1028202                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98432500                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24268972                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1310585                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10998177                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31553871                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12528994                       # Number of branches executed
-system.cpu.iew.exec_stores                    7165521                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.227229                       # Inst execution rate
-system.cpu.iew.wb_sent                       97952857                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      97204068                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  67107593                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95129025                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10930351                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31432616                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12487704                       # Number of branches executed
+system.cpu.iew.exec_stores                    7163644                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.245321                       # Inst execution rate
+system.cpu.iew.wb_sent                       97645732                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      96956080                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  66985594                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95002941                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.191985                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.705438                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.211642                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705090                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        31745312                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        30887581                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            965615                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39467684                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.328565                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.908680                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            914614                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39095972                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.350704                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.921132                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14970260     37.93%     37.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8589907     21.76%     59.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3909988      9.91%     69.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1952996      4.95%     74.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1374473      3.48%     78.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1034336      2.62%     80.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       694993      1.76%     82.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       731194      1.85%     84.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6209537     15.73%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14698430     37.60%     37.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8547015     21.86%     59.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3864183      9.88%     69.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1929221      4.93%     74.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1372371      3.51%     77.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1004316      2.57%     80.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       690404      1.77%     82.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       733733      1.88%     84.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6256299     16.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39467684                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39095972                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,350 +570,350 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6209537                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    156905474                       # The number of ROB reads
-system.cpu.rob.rob_writes                   251988235                       # The number of ROB writes
-system.cpu.timesIdled                            4640                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          245900                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6256299                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    155629269                       # The number of ROB reads
+system.cpu.rob.rob_writes                   250130763                       # The number of ROB writes
+system.cpu.timesIdled                            4629                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          249017                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.526792                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.526792                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.898281                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.898281                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                133413106                       # number of integer regfile reads
-system.cpu.int_regfile_writes                73139309                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6258544                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6168597                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  718994                       # number of misc regfile reads
+system.cpu.cpi                               0.520778                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.520778                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.920204                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.920204                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                132982273                       # number of integer regfile reads
+system.cpu.int_regfile_writes                72919705                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6252521                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6155462                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  719143                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements               159                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1454.905467                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28683797                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.replacements               158                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1457.350779                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28592916                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12782.440731                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12741.941176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1454.905467                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355202                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355202                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2085                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1386                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509033                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57388820                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57388820                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22190893                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22190893                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492625                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492625                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          279                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          279                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28683518                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28683518                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28683518                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28683518                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1012                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1012                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8478                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8478                       # number of WriteReq misses
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.350779                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355799                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355799                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2086                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509277                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          57207152                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57207152                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22099846                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22099846                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492613                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492613                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          457                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          457                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28592459                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28592459                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28592459                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28592459                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1047                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1047                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8490                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8490                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9490                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9490                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9490                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9490                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     67994000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     67994000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    547632747                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    547632747                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9537                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9537                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9537                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9537                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     69532500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     69532500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    543709251                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    543709251                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        85000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    615626747                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    615626747                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    615626747                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    615626747                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22191905                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22191905                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    613241751                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    613241751                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    613241751                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    613241751                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22100893                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22100893                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          280                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          280                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28693008                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28693008                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28693008                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28693008                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001304                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001304                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003571                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003571                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000331                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000331                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000331                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000331                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67187.747036                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67187.747036                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64594.567941                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64594.567941                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          458                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          458                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28601996                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28601996                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28601996                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28601996                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001306                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001306                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002183                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002183                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000333                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000333                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000333                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000333                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64871.100843                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64871.100843                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64871.100843                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64871.100843                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33428                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               398                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.989950                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64301.326518                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64301.326518                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32746                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          127                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               389                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    84.179949                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          109                       # number of writebacks
-system.cpu.dcache.writebacks::total               109                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          503                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          503                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6744                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6744                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7247                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7247                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7247                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7247                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          509                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          509                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1734                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1734                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
+system.cpu.dcache.writebacks::total               108                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          540                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6754                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6754                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7294                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7294                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7294                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7294                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          507                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          507                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1736                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1736                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39245500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     39245500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    137397495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    137397495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39700000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     39700000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135151495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    135151495                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    176642995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    176642995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    176642995                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    176642995                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    174851495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    174851495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    174851495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    174851495                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003571                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003571                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002183                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002183                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77103.143418                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77103.143418                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79237.309689                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79237.309689                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84000                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78753.007133                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78753.007133                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78753.007133                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78753.007133                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              9772                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1599.606485                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            16119452                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11709                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1376.671962                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9477                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1601.339074                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            15910864                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11414                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1393.977922                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1599.606485                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.781058                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.781058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1601.339074                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781904                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781904                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          770                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          934                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          944                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          32280293                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         32280293                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     16119452                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        16119452                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      16119452                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         16119452                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     16119452                       # number of overall hits
-system.cpu.icache.overall_hits::total        16119452                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14840                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14840                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14840                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14840                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14840                       # number of overall misses
-system.cpu.icache.overall_misses::total         14840                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    447595000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    447595000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    447595000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    447595000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    447595000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    447595000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     16134292                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     16134292                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     16134292                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     16134292                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     16134292                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     16134292                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000920                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000920                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000920                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000920                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000920                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000920                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30161.388140                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 30161.388140                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 30161.388140                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 30161.388140                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 30161.388140                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 30161.388140                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          223                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          31862226                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         31862226                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     15910864                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        15910864                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      15910864                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         15910864                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     15910864                       # number of overall hits
+system.cpu.icache.overall_hits::total        15910864                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14542                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14542                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14542                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14542                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14542                       # number of overall misses
+system.cpu.icache.overall_misses::total         14542                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    447928500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    447928500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    447928500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    447928500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    447928500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    447928500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     15925406                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     15925406                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     15925406                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     15925406                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     15925406                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     15925406                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000913                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000913                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000913                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000913                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000913                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000913                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30802.399945                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30802.399945                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          837                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    55.750000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   209.250000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3131                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3131                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3131                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3131                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3131                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3131                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11709                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11709                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11709                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11709                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11709                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11709                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    339198000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    339198000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    339198000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    339198000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    339198000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    339198000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000726                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000726                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000726                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000726                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000726                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000726                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28968.998207                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28968.998207                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28968.998207                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28968.998207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28968.998207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28968.998207                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3128                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3128                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3128                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3128                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3128                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3128                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11414                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11414                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11414                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        11414                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        11414                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11414                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    338490500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    338490500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    338490500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    338490500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    338490500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    338490500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000717                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000717                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000717                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29655.729806                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 29655.729806                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 29655.729806                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2400.828541                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              18535                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3588                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.165831                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2397.609271                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              17951                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3579                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             5.015647                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.705545                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2008.692656                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   374.430341                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.690606                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2004.677718                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   375.240947                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061300                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.011427                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.073267                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3588                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061178                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.011451                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.073169                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3579                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          914                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          908                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2424                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109497                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           196394                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          196394                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          109                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          109                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2421                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109222                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           191659                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          191659                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks          108                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          108                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8643                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         8643                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           55                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           55                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8643                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           81                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            8724                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8643                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           81                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           8724                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1708                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1708                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3066                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3066                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          455                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          455                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3066                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2163                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5229                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3066                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2163                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5229                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    134381000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    134381000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    230878000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    230878000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     37969000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     37969000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    230878000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    172350000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    403228000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    230878000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    172350000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    403228000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          109                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          109                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1734                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1734                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11709                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        11709                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          510                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          510                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        11709                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8355                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8355                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           54                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           54                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8355                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            8435                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8355                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           8435                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1710                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1710                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3059                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3059                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          454                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          454                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3059                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2164                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5223                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3059                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2164                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5223                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    132132500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    132132500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    233633500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    233633500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     38438500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     38438500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    233633500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    170571000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    404204500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    233633500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    170571000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    404204500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks          108                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          108                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1736                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1736                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11414                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        11414                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          508                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          508                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        11414                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2244                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13953                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        11709                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        13658                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11414                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2244                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13953                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985006                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.985006                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.261850                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.261850                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.892157                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.892157                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.261850                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.963904                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.374758                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.261850                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.963904                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.374758                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78677.400468                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78677.400468                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75302.674494                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75302.674494                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83448.351648                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83448.351648                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75302.674494                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79680.998613                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77113.788487                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75302.674494                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79680.998613                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77113.788487                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::total        13658                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985023                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.985023                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.268004                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.268004                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.893701                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.893701                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.268004                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964349                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.382413                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.268004                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964349                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.382413                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77270.467836                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77270.467836                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76375.776398                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -923,108 +922,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1708                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1708                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3066                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3066                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          455                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          455                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3066                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2163                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5229                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3066                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2163                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5229                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    117301000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    117301000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200218000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200218000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33419000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33419000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200218000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    150720000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    350938000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200218000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    150720000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    350938000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985006                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985006                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.261850                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.261850                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.892157                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.892157                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.261850                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963904                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.374758                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.261850                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963904                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.374758                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68677.400468                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68677.400468                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65302.674494                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65302.674494                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73448.351648                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73448.351648                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65302.674494                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69680.998613                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67113.788487                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65302.674494                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69680.998613                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67113.788487                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1710                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1710                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3059                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3059                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          454                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          454                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3059                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2164                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5223                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3059                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2164                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5223                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115032500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115032500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    203043500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    203043500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33898500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33898500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    203043500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    148931000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    351974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    203043500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    148931000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    351974500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985023                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985023                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.268004                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.893701                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.893701                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.382413                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.382413                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp         12219                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          109                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         9822                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1734                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1734                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        11709                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          510                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33190                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4647                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             37837                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       749376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             899968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp         11922                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          108                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         9527                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1736                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1736                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11414                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          508                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32305                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4646                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             36951                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       730496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             881024                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        23884                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        23293                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              23884    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              23293    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          23884                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       12051000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          23293                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       11754500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17563500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17121000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3366000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3521                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1708                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1708                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3521                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10458                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10458                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               3513                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1710                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1710                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3513                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334272                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5229                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5223                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5229    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5223    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5229                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6267000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5223                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6235500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           27480000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           27428750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
index 29e916711..5611a7dae 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -759,7 +759,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
index c2579128c..87bca4e9e 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
@@ -1,14 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
-Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
-Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 04:10:24
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x3623b60
 info: Entering event queue @ 0.  Starting simulation...
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
@@ -24,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 131756455500 because target called exit()
+122 123 124 Exiting @ tick 130772636500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index f9aa76ee3..396e2f8dd 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.131585                       # Number of seconds simulated
-sim_ticks                                131584694500                       # Number of ticks simulated
-final_tick                               131584694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.130773                       # Number of seconds simulated
+sim_ticks                                130772636500                       # Number of ticks simulated
+final_tick                               130772636500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 242795                       # Simulator instruction rate (inst/s)
-host_op_rate                                   255945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              185402255                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318276                       # Number of bytes of host memory used
-host_seconds                                   709.73                       # Real time elapsed on the host
+host_inst_rate                                 167747                       # Simulator instruction rate (inst/s)
+host_op_rate                                   176832                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              127303889                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312696                       # Number of bytes of host memory used
+host_seconds                                  1027.25                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            138368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            138112                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            109312                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               247680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       138368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          138368                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2162                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               247424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       138112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          138112                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2158                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3870                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1051551                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               830735                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1882286                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1051551                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1051551                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1051551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              830735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1882286                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3870                       # Number of read requests accepted
+system.physmem.num_reads::total                  3866                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1056123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               835894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1892017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1056123                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1056123                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1056123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              835894                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1892017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3866                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3870                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3866                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   247680                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   247424                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    247680                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    247424                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -45,14 +45,14 @@ system.physmem.perBankRdBursts::0                 305                       # Pe
 system.physmem.perBankRdBursts::1                 217                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 135                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 313                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 308                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 306                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 305                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 273                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 222                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 249                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 248                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                201                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                200                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    131584601000                       # Total gap between requests
+system.physmem.totGap                    130772543000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3870                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3866                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3621                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       236                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3616                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          912                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      269.614035                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.051598                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     274.679496                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            270     29.61%     29.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          347     38.05%     67.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           87      9.54%     77.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           54      5.92%     83.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           40      4.39%     87.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           20      2.19%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           18      1.97%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           19      2.08%     93.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           57      6.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            912                       # Bytes accessed per row activation
-system.physmem.totQLat                       27229750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  99792250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7036.11                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          905                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      271.628729                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.806384                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     277.022098                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            259     28.62%     28.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          352     38.90%     67.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           86      9.50%     77.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           59      6.52%     83.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           34      3.76%     87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           21      2.32%     89.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           17      1.88%     91.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           17      1.88%     93.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           60      6.63%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            905                       # Bytes accessed per row activation
+system.physmem.totQLat                       28055750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 100543250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     19330000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7257.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25786.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26007.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
@@ -216,49 +216,49 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2952                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2957                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.28                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.49                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     34001188.89                       # Average gap between requests
-system.physmem.pageHitRate                      76.28                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3129840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1707750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16177200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     33826317.38                       # Average gap between requests
+system.physmem.pageHitRate                      76.49                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3099600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1691250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16161600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             8594155440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3579629355                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            75808025250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              88002824835                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.815686                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   126113612750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      4393740000                       # Time in different power states
+system.physmem_0.refreshEnergy             8541265200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3568801635                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            75331661250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              87462680535                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.826718                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   125318913500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4366700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1075043250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1084715250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3749760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2046000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13774800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3727080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2033625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13782600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             8594155440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3571830900                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75814874250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              88000431150                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.797424                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   126123074750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      4393740000                       # Time in different power states
+system.physmem_1.refreshEnergy             8541265200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3564422325                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75335511000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              87460741830                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.811822                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   125325774500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      4366700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1063297750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1078159500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                49889701                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39633557                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           5745356                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24337782                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23279998                       # Number of BTB hits
+system.cpu.branchPred.lookups                49732170                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39495980                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5592247                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24154061                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23128262                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.653737                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1903300                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                140                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             95.753099                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1888632                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                142                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,26 +377,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        263169389                       # number of cpu cycles simulated
+system.cpu.numCycles                        261545273                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317810                       # Number of instructions committed
 system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11983759                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      11660914                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.527233                       # CPI: cycles per instruction
-system.cpu.ipc                               0.654779                       # IPC: instructions per cycle
-system.cpu.tickCycles                       256740818                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         6428571                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.517808                       # CPI: cycles per instruction
+system.cpu.ipc                               0.658845                       # IPC: instructions per cycle
+system.cpu.tickCycles                       255251954                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         6293319                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1377.711326                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40793911                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1377.707601                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40756382                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22538.072376                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22517.338122                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1377.711326                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.336355                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.336355                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1377.707601                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.336354                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336354                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
@@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           83
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          81594514                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         81594514                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28385993                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28385993                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12362640                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12362640                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          464                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           464                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          81519460                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81519460                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28348467                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28348467                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12362639                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12362639                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40748633                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40748633                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40749097                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40749097                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          793                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           793                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1647                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1647                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      40711106                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40711106                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40711568                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40711568                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          794                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           794                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1648                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1648                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         2440                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2440                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2441                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2441                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     57382000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     57382000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    126740000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    126740000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    184122000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    184122000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    184122000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    184122000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28386786                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28386786                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         2442                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2442                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2443                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2443                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     58025500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     58025500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    126322500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    126322500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    184348000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    184348000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    184348000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    184348000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28349261                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28349261                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          465                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          465                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40751073                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40751073                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40751538                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40751538                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     40713548                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40713548                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40714011                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40714011                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000133                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000133                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002151                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.002151                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72360.655738                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72360.655738                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76952.034001                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76952.034001                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75459.836066                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75459.836066                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75428.922573                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75428.922573                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75490.581491                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75459.680720                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           82                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           82                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          549                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          549                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          631                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          631                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          631                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          631                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          550                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          550                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          633                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          633                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          633                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          633                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
@@ -498,91 +498,91 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1809
 system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51034000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     51034000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85245500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     85245500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51768000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     51768000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85075000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85075000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        70000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        70000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136279500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    136279500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136349500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    136349500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    136843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136913000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    136913000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002151                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002151                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71777.777778                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71777.777778                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77637.067395                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77637.067395                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        70000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        70000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75334.162521                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75334.162521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75331.215470                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75331.215470                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2889                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1425.919952                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71538505                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4687                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15263.175805                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2888                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1423.991727                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            71011798                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4684                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15160.503416                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1425.919952                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.696250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.696250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1798                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1423.991727                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.695308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.695308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1796                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          493                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          125                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.877930                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         143091073                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        143091073                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     71538505                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71538505                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      71538505                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71538505                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     71538505                       # number of overall hits
-system.cpu.icache.overall_hits::total        71538505                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4688                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4688                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4688                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4688                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4688                       # number of overall misses
-system.cpu.icache.overall_misses::total          4688                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    199914000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    199914000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    199914000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    199914000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    199914000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    199914000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     71543193                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71543193                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     71543193                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71543193                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     71543193                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71543193                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1068                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.876953                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         142037650                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        142037650                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     71011798                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        71011798                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      71011798                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         71011798                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     71011798                       # number of overall hits
+system.cpu.icache.overall_hits::total        71011798                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4685                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4685                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4685                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4685                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4685                       # number of overall misses
+system.cpu.icache.overall_misses::total          4685                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    199910500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    199910500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    199910500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    199910500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    199910500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    199910500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     71016483                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     71016483                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     71016483                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     71016483                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     71016483                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     71016483                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.771331                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42643.771331                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.771331                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42643.771331                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.771331                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42643.771331                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42670.330843                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42670.330843                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,129 +591,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4688                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4688                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4688                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4688                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4688                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4688                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    195227000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    195227000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    195227000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    195227000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    195227000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    195227000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4685                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4685                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4685                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4685                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4685                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4685                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    195226500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    195226500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    195226500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    195226500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    195226500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    195226500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.984642                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41643.984642                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41643.984642                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41643.984642                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41643.984642                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41643.984642                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2002.545063                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               5192                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2788                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.862267                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2000.604150                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               5191                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2784                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.864583                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.029187                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1508.695895                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   490.819981                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.029284                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1506.756657                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   490.818208                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046042                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045983                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.014979                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.061113                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2788                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.061054                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2784                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          523                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2006                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.085083                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            76702                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           76702                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          524                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          151                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2004                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084961                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            76658                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           76658                       # Number of data accesses
 system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2523                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         2523                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2524                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         2524                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           80                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           80                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2523                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         2524                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           88                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2611                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2523                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            2612                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2524                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2611                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2612                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1090                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2165                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2165                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2161                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2161                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          632                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          632                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2165                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         2161                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         1722                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3887                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2165                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          3883                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2161                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1722                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3887                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     83513000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     83513000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    161704000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    161704000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     49184000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     49184000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    161704000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    132697000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    294401000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    161704000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    132697000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    294401000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total         3883                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     83342500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     83342500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    161697500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    161697500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     49918000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     49918000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    161697500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    133260500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    294958000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    161697500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    133260500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    294958000                       # number of overall miss cycles
 system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4688                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4688                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4685                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4685                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          712                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          712                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4688                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         4685                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         1810                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6498                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4688                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         6495                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4685                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         1810                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6498                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         6495                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992714                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.461817                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461817                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.461259                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461259                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.887640                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461817                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461259                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.951381                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.598184                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461817                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.597844                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461259                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.951381                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.598184                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76617.431193                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76617.431193                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74690.069284                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74690.069284                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.784810                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.784810                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74690.069284                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77059.814170                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75739.902238                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74690.069284                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77059.814170                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75739.902238                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.597844                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -734,106 +734,106 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           14
 system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1090                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2163                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2163                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2159                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2159                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          618                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          618                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2163                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2159                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3871                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2163                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3867                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2159                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3871                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72613000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72613000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    139936000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    139936000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     42042000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     42042000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    139936000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    114655000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    254591000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    139936000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    114655000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    254591000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         3867                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72442500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72442500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    139969500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    139969500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     42776000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     42776000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    139969500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    115218500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    255188000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    139969500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    115218500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    255188000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.461391                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.460832                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.867978                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.595722                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461391                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.595381                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.595722                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66617.431193                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66617.431193                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64695.330559                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64695.330559                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68029.126214                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68029.126214                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64695.330559                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.220141                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65768.793593                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64695.330559                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.220141                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65768.793593                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.595381                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp          5399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         2588                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2586                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4685                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          712                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11943                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11935                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3656                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             15599                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       299968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             15591                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       299776                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             416832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             416640                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9429                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9425                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               9429    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               9425    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9429                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        4730500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9425                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        4728500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7031498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7026998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2721986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               2780                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2776                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          2780                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7740                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7740                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247680                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  247680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          2776                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7732                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7732                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  247424                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3870                       # Request fanout histogram
+system.membus.snoop_fanout::samples              3866                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3870    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3866    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3870                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4532500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                3866                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             4535000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20566750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20543000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 962fb9596..cec07c5fb 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -490,7 +490,7 @@ opLat=4
 pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -600,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -688,7 +688,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 081b32451..1647d5712 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -156,7 +156,7 @@ localPredictorSize=2048
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -513,7 +513,7 @@ opLat=3
 pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -579,7 +579,7 @@ system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 7449e222c..61db655d7 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 08:10:29
-gem5 started Apr 22 2015 10:10:22
-gem5 executing on phenom
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+gem5 compiled Sep 14 2015 22:13:36
+gem5 started Sep 14 2015 23:11:50
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
@@ -19,397 +21,11 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
- 31  32  33  34  35  36  37  38  39  40  41  42 info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
- 43  44  45 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 148668850500 because target called exit()
+122 123 124 info: Increasing stack size by one page.
+Exiting @ tick 79147317000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 8e968af2a..cd6ba3bb4 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.081371                       # Number of seconds simulated
-sim_ticks                                 81371461000                       # Number of ticks simulated
-final_tick                                81371461000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.079147                       # Number of seconds simulated
+sim_ticks                                 79147317000                       # Number of ticks simulated
+final_tick                                79147317000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90424                       # Simulator instruction rate (inst/s)
-host_op_rate                                   151559                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55711800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 348672                       # Number of bytes of host memory used
-host_seconds                                  1460.58                       # Real time elapsed on the host
+host_inst_rate                                  70947                       # Simulator instruction rate (inst/s)
+host_op_rate                                   118914                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42517019                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343896                       # Number of bytes of host memory used
+host_seconds                                  1861.54                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            224128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               349632                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       224128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          224128                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3502                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1961                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5463                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2754381                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1542359                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4296740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2754381                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2754381                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2754381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1542359                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4296740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5463                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            221376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            124928                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               346304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221376                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3459                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1952                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5411                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2797012                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1578424                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4375436                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2797012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2797012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2797012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1578424                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4375436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5413                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5463                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5413                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   349632                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   346304                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    349632                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    346432                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            312                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 292                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 354                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 456                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 360                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 330                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 342                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 399                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 387                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 324                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                240                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                270                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                487                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                392                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                328                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            303                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 299                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 344                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 461                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 354                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 343                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 326                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 401                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 385                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 338                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 281                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                237                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                285                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                221                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                466                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                386                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                284                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     81371407000                       # Total gap between requests
+system.physmem.totGap                     79147284500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5463                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5413                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4363                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       914                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       164                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4288                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       911                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       178                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,313 +186,313 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1133                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      307.177405                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.606569                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.434363                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            453     39.98%     39.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          241     21.27%     61.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          107      9.44%     70.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           66      5.83%     76.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           42      3.71%     80.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           53      4.68%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           30      2.65%     87.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      1.59%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          123     10.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1133                       # Bytes accessed per row activation
-system.physmem.totQLat                       39364000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 141795250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     27315000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7205.56                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25955.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.30                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.bytesPerActivate::samples         1109                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      312.266907                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.102740                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.449427                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            425     38.32%     38.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          245     22.09%     60.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          103      9.29%     69.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           58      5.23%     74.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           62      5.59%     80.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           52      4.69%     85.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           24      2.16%     87.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           18      1.62%     89.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          122     11.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1109                       # Bytes accessed per row activation
+system.physmem.totQLat                       39588000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 141044250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     27055000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7313.50                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      4998.15                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  26056.58                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.38                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.30                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.32                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4322                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4302                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.11                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.48                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14895004.03                       # Average gap between requests
-system.physmem.pageHitRate                      79.11                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4898880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2673000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  22627800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     14621704.14                       # Average gap between requests
+system.physmem.pageHitRate                      79.48                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4951800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2701875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  22721400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5314452000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2576418525                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            46559935500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              54481005705                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.574677                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    77452365250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2717000000                       # Time in different power states
+system.physmem_0.refreshEnergy             5169512400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2476092825                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            45316483500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              52992463800                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.540663                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    75384383500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2642640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1197234500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1120221500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3643920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1988250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  19640400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3432240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1872750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  19484400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5314452000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2400589485                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            46714163250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              54454477305                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.248755                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    77713281250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2717000000                       # Time in different power states
+system.physmem_1.refreshEnergy             5169512400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2281510215                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            45487170000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              52962982005                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.168172                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    75669637750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2642640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       939125250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       834967250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                21769917                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          21769917                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1549122                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             13731962                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                12878566                       # Number of BTB hits
+system.cpu.branchPred.lookups                20588400                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          20588400                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1327971                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12696525                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12013993                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.785331                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1523299                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21478                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.624261                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1440282                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              16776                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        162742923                       # number of cpu cycles simulated
+system.cpu.numCycles                        158294635                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27183337                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      241535825                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    21769917                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           14401865                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     133481172                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3672135                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                          7                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 3449                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         35973                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           25247816                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      227405263                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    20588400                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13454275                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     131222766                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3194613                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 1919                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         20727                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          110                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  26033005                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                318152                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          162540128                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.445335                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.347989                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles           47                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  24255799                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                267811                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          158090598                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.379045                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.324681                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 96819226     59.57%     59.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4970692      3.06%     62.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3926504      2.42%     65.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4600449      2.83%     67.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4436163      2.73%     70.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5045508      3.10%     73.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5083113      3.13%     76.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3898601      2.40%     79.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 33759872     20.77%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 95773120     60.58%     60.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4766421      3.01%     63.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3796193      2.40%     66.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4366321      2.76%     68.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4228924      2.68%     71.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4813507      3.04%     74.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4702194      2.97%     77.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3700875      2.34%     79.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 31943043     20.21%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            162540128                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.133769                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.484156                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16504764                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96892991                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  25874540                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              21431766                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1836067                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              352818767                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                1836067                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24444805                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                33422530                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          30828                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  38315708                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              64490190                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              343379412                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1374                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               57139077                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7429063                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 172376                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           397453727                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             950141626                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        627304694                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4642412                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            158090598                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.130064                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.436595                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15405711                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              96196393                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  23270128                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              21621060                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1597306                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              336557336                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1597306                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 23296942                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                31816084                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          30705                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35988234                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              65361327                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              328199746                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1272                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               57739687                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7687780                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 164697                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           380395487                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             909798638                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        600491080                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           4191135                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                138024277                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2171                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2092                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 120106098                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             87123680                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            31143046                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          62089518                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         21014033                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  331702995                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4700                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 264529155                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             75427                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       110344311                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    226235086                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           3455                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     162540128                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.627470                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.538199                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                120966037                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1948                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1925                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 121028118                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             82726275                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            29782185                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          59498195                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         20364114                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  317775977                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4062                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 259339716                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             70716                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        96416655                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    197093622                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2817                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     158090598                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.640450                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.524161                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            42962851     26.43%     26.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            47766675     29.39%     55.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            33381943     20.54%     76.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18299706     11.26%     87.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11254917      6.92%     94.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4928041      3.03%     97.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2601211      1.60%     99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              925935      0.57%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              418849      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            40031018     25.32%     25.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            47550925     30.08%     55.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            33058238     20.91%     76.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17999758     11.39%     87.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10966409      6.94%     94.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4755401      3.01%     97.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2459487      1.56%     99.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              881418      0.56%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              387944      0.25%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       162540128                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       158090598                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  228422      7.18%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2563241     80.56%     87.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                390075     12.26%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  232409      7.35%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2543467     80.43%     87.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                386453     12.22%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1211775      0.46%      0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             165335672     62.50%     62.96% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               786316      0.30%     63.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7038827      2.66%     65.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1212035      0.46%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             66231753     25.04%     91.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22712777      8.59%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1213129      0.47%      0.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             161789317     62.39%     62.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               789379      0.30%     63.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7038032      2.71%     65.87% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1187047      0.46%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             64866508     25.01%     91.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22456304      8.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              264529155                       # Type of FU issued
-system.cpu.iq.rate                           1.625442                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3181738                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012028                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          689869496                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         438078029                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    258256761                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4986107                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4289171                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2392105                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              263990006                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2509112                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18745493                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              259339716                       # Type of FU issued
+system.cpu.iq.rate                           1.638335                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3162329                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012194                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          675146049                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         410783686                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    253609186                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4857026                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            3709843                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2340813                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              258843472                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2445444                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18733712                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     30474102                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13683                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       322031                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     10627329                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     26076688                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        12661                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       303068                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      9266468                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        52743                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            15                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        50753                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            39                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1836067                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                14124717                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                495168                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           331707695                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            107609                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              87123689                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             31143046                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2075                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 394182                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 62934                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         322031                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         682027                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       925981                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1608008                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             262198462                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              65303975                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2330693                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1597306                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12475143                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                492608                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           317780039                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             92128                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              82726275                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             29782185                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1904                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 385254                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 64210                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         303068                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         551876                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       825683                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1377559                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             257278299                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              64049933                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2061417                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     87811155                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14511685                       # Number of branches executed
-system.cpu.iew.exec_stores                   22507180                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.611121                       # Inst execution rate
-system.cpu.iew.wb_sent                      261483321                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     260648866                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 208559295                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 374938421                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     86328991                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14325599                       # Number of branches executed
+system.cpu.iew.exec_stores                   22279058                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.625313                       # Inst execution rate
+system.cpu.iew.wb_sent                      256636877                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     255949999                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 204329368                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 369642243                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.601599                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.556249                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.616922                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.552776                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       110351288                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        96424533                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1552443                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    147477365                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.500999                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.940236                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1329745                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    144946815                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.527204                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.957309                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     47558134     32.25%     32.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57784481     39.18%     71.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14247523      9.66%     81.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11907169      8.07%     89.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4233466      2.87%     92.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2889588      1.96%     93.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       908406      0.62%     94.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1058674      0.72%     95.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6889924      4.67%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     45502245     31.39%     31.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57364882     39.58%     70.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14168547      9.77%     80.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11990061      8.27%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4061557      2.80%     91.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2847156      1.96%     93.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       903972      0.62%     94.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1081775      0.75%     95.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7026620      4.85%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    147477365                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    144946815                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -538,124 +538,125 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6889924                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    472302113                       # The number of ROB reads
-system.cpu.rob.rob_writes                   678534776                       # The number of ROB writes
-system.cpu.timesIdled                            2601                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          202795                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               7026620                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    455708112                       # The number of ROB reads
+system.cpu.rob.rob_writes                   648756933                       # The number of ROB writes
+system.cpu.timesIdled                            2654                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          204037                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.232236                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.232236                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.811533                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.811533                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                453858264                       # number of integer regfile reads
-system.cpu.int_regfile_writes               236894069                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3268800                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2052370                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102728686                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 60021475                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               135450288                       # number of misc regfile reads
+system.cpu.cpi                               1.198555                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.198555                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.834338                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.834338                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                448462774                       # number of integer regfile reads
+system.cpu.int_regfile_writes               232558570                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3214394                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  1998880                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 102524460                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 59518831                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               132416718                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements                22                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1449.922463                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            66913357                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1999                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          33473.415208                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                53                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1431.895248                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            65702088                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1996                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          32916.877756                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1449.922463                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353985                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353985                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1977                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          483                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1444                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.482666                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         133833717                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        133833717                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     46399026                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        46399026                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513875                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513875                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      66912901                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         66912901                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     66912901                       # number of overall hits
-system.cpu.dcache.overall_hits::total        66912901                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1102                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1856                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1856                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2958                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2958                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2958                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2958                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     70369000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     70369000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    128824000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    128824000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    199193000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    199193000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    199193000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    199193000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     46400128                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     46400128                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  1431.895248                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.349584                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.349584                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1943                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1395                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.474365                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         131411014                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        131411014                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     45187780                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        45187780                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513887                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513887                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      65701667                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         65701667                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     65701667                       # number of overall hits
+system.cpu.dcache.overall_hits::total        65701667                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          998                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           998                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1844                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1844                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2842                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2842                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2842                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2842                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     65947500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     65947500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    129226000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    129226000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    195173500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    195173500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    195173500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    195173500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     45188778                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     45188778                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     66915859                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     66915859                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     66915859                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     66915859                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     65704509                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     65704509                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     65704509                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     65704509                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000090                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000090                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000044                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000044                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000044                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000044                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63855.716878                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63855.716878                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69409.482759                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69409.482759                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67340.432725                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67340.432725                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67340.432725                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67340.432725                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          318                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           52                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 68674.700915                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68674.700915                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          656                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           70                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 7                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.600000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           52                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    93.714286                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           70                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           11                       # number of writebacks
-system.cpu.dcache.writebacks::total                11                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          641                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          641                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks           12                       # number of writebacks
+system.cpu.dcache.writebacks::total                12                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          541                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          541                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          643                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          643                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          643                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          643                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          461                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          461                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1854                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1854                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2315                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2315                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2315                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2315                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36642000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36642000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    126830000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    126830000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    163472000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    163472000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    163472000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    163472000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data          543                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          543                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          543                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          543                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          457                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          457                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1842                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1842                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2299                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2299                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2299                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2299                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36552500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36552500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    127238000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    127238000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    163790500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    163790500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    163790500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    163790500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000090                       # mshr miss rate for WriteReq accesses
@@ -664,214 +665,212 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000035
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000035                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79483.731020                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79483.731020                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68408.845739                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68408.845739                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70614.254860                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 70614.254860                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70614.254860                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 70614.254860                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              5619                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1637.148267                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            26022644                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              7593                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3427.188726                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              5044                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1638.951309                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24246301                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              7022                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3452.905298                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1637.148267                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.799389                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.799389                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1974                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1638.951309                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.800269                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.800269                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          882                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          786                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.963867                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          52073916                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         52073916                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     26022649                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        26022649                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      26022649                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         26022649                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     26022649                       # number of overall hits
-system.cpu.icache.overall_hits::total        26022649                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        10355                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         10355                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        10355                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          10355                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        10355                       # number of overall misses
-system.cpu.icache.overall_misses::total         10355                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    419159499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    419159499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    419159499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    419159499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    419159499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    419159499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     26033004                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     26033004                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     26033004                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     26033004                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     26033004                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     26033004                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000398                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000398                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000398                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000398                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000398                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000398                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40478.947272                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 40478.947272                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 40478.947272                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 40478.947272                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 40478.947272                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 40478.947272                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1340                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::1          191                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          874                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          48518920                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         48518920                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     24246303                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        24246303                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      24246303                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         24246303                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     24246303                       # number of overall hits
+system.cpu.icache.overall_hits::total        24246303                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9495                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9495                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9495                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9495                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9495                       # number of overall misses
+system.cpu.icache.overall_misses::total          9495                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    408233999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    408233999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    408233999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    408233999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    408233999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    408233999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24255798                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24255798                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     24255798                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     24255798                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24255798                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24255798                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000391                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000391                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000391                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000391                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000391                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000391                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42994.628647                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42994.628647                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42994.628647                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42994.628647                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42994.628647                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42994.628647                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          791                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    51.538462                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    60.846154                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2445                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2445                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2445                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2445                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2445                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2445                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7910                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7910                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7910                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7910                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    320594000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    320594000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    320594000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    320594000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    320594000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    320594000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000304                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000304                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000304                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000304                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000304                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000304                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40530.214918                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40530.214918                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40530.214918                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40530.214918                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40530.214918                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40530.214918                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2168                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2168                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2168                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2168                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2168                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2168                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7327                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7327                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7327                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7327                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7327                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7327                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    310311499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    310311499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    310311499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    310311499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    310311499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    310311499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000302                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000302                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000302                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000302                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000302                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000302                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42351.780947                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42351.780947                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42351.780947                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 42351.780947                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42351.780947                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 42351.780947                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2621.537078                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               9541                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3929                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.428353                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2588.297524                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               8549                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3882                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.202215                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     0.832574                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2306.260557                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   314.443947                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     0.823385                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2282.748954                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   304.725185                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000025                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.070381                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009596                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.080003                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3929                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1003                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           50                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2650                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.119904                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           128128                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          128128                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks           11                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           11                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            6                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            6                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4091                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         4091                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           32                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           32                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4091                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           38                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            4129                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4091                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           38                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           4129                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          312                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          312                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1533                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1533                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3503                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3503                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          428                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          428                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3503                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1961                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5464                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3503                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1961                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5464                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    114429000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    114429000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    265295500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    265295500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35535500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     35535500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    265295500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    149964500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    415260000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    265295500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    149964500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    415260000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks           11                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           11                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          316                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          316                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069664                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.009299                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.078989                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3882                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          994                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           40                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2615                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118469                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           119661                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          119661                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks           12                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           12                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            5                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            5                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3560                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         3560                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           39                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           39                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3560                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           44                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            3604                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3560                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           44                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           3604                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          303                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          303                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1534                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1534                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3462                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3462                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          418                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          418                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3462                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1952                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5414                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3462                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1952                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5414                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    115109000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    115109000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261483000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    261483000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35445000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     35445000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    261483000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    150554000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    412037000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    261483000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    150554000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    412037000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks           12                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           12                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          303                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          303                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1539                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1539                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         7594                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         7594                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          460                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          460                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7594                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1999                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9593                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7594                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1999                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9593                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.987342                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.987342                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996101                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.996101                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.461285                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461285                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.930435                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.930435                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461285                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.980990                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.569582                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461285                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.980990                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.569582                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74643.835616                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74643.835616                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75733.799600                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75733.799600                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83026.869159                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83026.869159                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75733.799600                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76473.482917                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75999.267936                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75733.799600                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76473.482917                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75999.267936                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         7022                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         7022                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          457                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          457                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         7022                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1996                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9018                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7022                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1996                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9018                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.996751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.493022                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.493022                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.914661                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.914661                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.493022                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.977956                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.600355                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.493022                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.977956                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.600355                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75038.461538                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75038.461538                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75529.462738                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75529.462738                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84796.650718                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84796.650718                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75529.462738                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77128.073770                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76105.836720                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75529.462738                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77128.073770                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76105.836720                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -880,122 +879,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          312                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          312                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1533                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1533                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3503                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3503                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          428                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          428                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3503                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1961                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5464                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3503                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1961                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5464                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      6464000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      6464000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     99099000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     99099000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    230285500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    230285500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31255500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31255500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    230285500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    130354500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    360640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    230285500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    130354500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    360640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987342                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987342                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996101                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996101                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.461285                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.461285                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.930435                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.930435                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461285                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980990                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.569582                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461285                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980990                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.569582                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20717.948718                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20717.948718                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64643.835616                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64643.835616                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65739.508992                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65739.508992                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73026.869159                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73026.869159                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65739.508992                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66473.482917                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66002.928258                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65739.508992                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66473.482917                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66002.928258                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          303                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          303                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3462                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3462                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          418                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          418                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3462                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1952                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5414                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3462                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1952                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5414                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      6283500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      6283500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     99769000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     99769000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    226893000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    226893000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31265000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31265000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    226893000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131034000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    357927000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    226893000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131034000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    357927000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.493022                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.493022                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.914661                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.914661                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.493022                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.977956                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.600355                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.493022                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.977956                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.600355                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20737.623762                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20737.623762                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65038.461538                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65038.461538                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65538.128250                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65538.128250                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74796.650718                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74796.650718                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.128250                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.073770                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66111.377909                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.128250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.073770                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66111.377909                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp          8368                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         5412                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          316                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          316                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          7781                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           12                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         4947                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          303                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          303                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1539                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1539                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         7910                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          460                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20904                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4651                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             25555                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       485888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             614528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         316                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        15866                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         7327                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          457                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19253                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4650                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             23903                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       449216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             577728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         305                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        14723                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              15866    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              14723    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          15866                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7944000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          14723                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7373500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      11862000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      10986000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3157498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3145500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3929                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              312                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             312                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1533                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1533                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3930                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11549                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11549                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11549                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       349568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       349568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  349568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               3877                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              303                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             303                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1534                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1534                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3879                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11430                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11430                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11430                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       346304                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total       346304                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  346304                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5775                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5716                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5775    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5716    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5775                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7111000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5716                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             7099000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           29581688                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           29276697                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 78cb13dcc..b567a20c2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -98,7 +98,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -107,7 +107,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -118,7 +118,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -139,7 +138,7 @@ eventq_index=0
 size=64
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -148,7 +147,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -159,7 +158,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -230,7 +228,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -239,7 +237,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -250,7 +248,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -271,7 +268,7 @@ eventq_index=0
 size=64
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -280,7 +277,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -291,7 +288,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -405,7 +401,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -414,7 +410,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -425,7 +421,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -441,7 +436,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -450,7 +445,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -461,7 +456,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 0b689db35..8a8f59ba6 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -98,7 +98,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -107,7 +107,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -118,7 +118,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -139,7 +138,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -148,7 +147,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -159,7 +158,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -189,7 +187,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -198,7 +196,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -209,7 +207,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -324,7 +321,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -333,7 +330,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -344,7 +341,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 6dd8362e8..e1d35dff5 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -94,7 +94,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -103,7 +103,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -114,7 +114,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -135,7 +134,7 @@ eventq_index=0
 size=64
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -144,7 +143,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -155,7 +154,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -222,7 +220,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -231,7 +229,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -242,7 +240,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -263,7 +260,7 @@ eventq_index=0
 size=64
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -272,7 +269,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -283,7 +280,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -397,7 +393,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -406,7 +402,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -417,7 +413,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -433,7 +428,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -442,7 +437,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -453,7 +448,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index 9e87f65da..8176c3d31 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 38 cycles, load miss latency 148 cycles
+
4096K Bcache detected; load hit latency 38 cycles, load miss latency 160 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 586901b21..191ca5cbb 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -94,7 +94,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -103,7 +103,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -114,7 +114,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -135,7 +134,7 @@ eventq_index=0
 size=64
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -144,7 +143,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -155,7 +154,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -185,7 +183,7 @@ eventq_index=0
 size=48
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -194,7 +192,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -205,7 +203,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -320,7 +317,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
@@ -329,7 +326,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -340,7 +337,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index d6ca9b555..64d8e02a2 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 38 cycles, load miss latency 148 cycles
+
4096K Bcache detected; load hit latency 38 cycles, load miss latency 160 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
index 92530cc80..5d89a381f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -322,7 +322,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -761,9 +761,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
index 72353edee..47529e9ec 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
@@ -6,7 +6,7 @@
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "highest_el_is_64": false, 
-        "kernel": "/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5", 
+        "kernel": "/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5", 
         "iobus": {
             "slave": {
                 "peer": [
@@ -68,7 +68,7 @@
             "frontend_latency": 2
         }, 
         "symbolfile": "", 
-        "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", 
+        "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", 
         "have_large_asid_64": false, 
         "phys_addr_range_64": 40, 
         "have_lpae": false, 
@@ -87,7 +87,7 @@
         "multi_proc": true, 
         "early_kernel_symbols": false, 
         "panic_on_oops": true, 
-        "dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb", 
+        "dtb_filename": "/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb", 
         "enable_context_switch_stats_dump": false, 
         "work_begin_ckpt_count": 0, 
         "clk_domain": {
@@ -108,30 +108,33 @@
         ], 
         "realview": {
             "hdlcd": {
-                "dma": {
-                    "peer": "system.membus.slave[0]", 
-                    "role": "MASTER"
-                }, 
-                "pixel_clock": 7299, 
                 "vnc": "system.vncserver", 
+                "pxl_clk": "system.realview.realview_io.osc_pxl", 
                 "name": "hdlcd", 
+                "workaround_dma_line_count": true, 
+                "amba_id": 1314816, 
                 "pio": {
                     "peer": "system.iobus.master[5]", 
                     "role": "SLAVE"
                 }, 
-                "amba_id": 1314816, 
                 "pio_latency": 10000, 
                 "clk_domain": "system.clk_domain", 
                 "system": "system", 
                 "gic": "system.realview.gic", 
                 "int_num": 117, 
                 "eventq_index": 0, 
+                "pixel_buffer_size": 2048, 
                 "cxx_class": "HDLcd", 
                 "enable_capture": true, 
                 "path": "system.realview.hdlcd", 
                 "pio_addr": 721420288, 
                 "workaround_swap_rb": true, 
-                "type": "HDLcd"
+                "type": "HDLcd", 
+                "pixel_chunk": 32, 
+                "dma": {
+                    "peer": "system.membus.slave[0]", 
+                    "role": "MASTER"
+                }
             }, 
             "mmc_fake": {
                 "name": "mmc_fake", 
@@ -893,7 +896,7 @@
                 "MSIXCAPNextCapability": 0, 
                 "PXCAPLinkCtrl": 0, 
                 "Revision": 0, 
-                "hardware_address": "<m5.params.EthernetAddr object at 0x7f90678a01d0>", 
+                "hardware_address": "<m5.params.EthernetAddr object at 0x488d6d0>", 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
                 "platform": "system.realview", 
@@ -1176,7 +1179,7 @@
             "clk_domain": "system.clk_domain", 
             "write_buffers": 8, 
             "response_latency": 50, 
-            "cxx_class": "BaseCache", 
+            "cxx_class": "Cache", 
             "size": 1024, 
             "tags": {
                 "name": "tags", 
@@ -1210,7 +1213,7 @@
             "prefetch_on_access": false, 
             "path": "system.iocache", 
             "name": "iocache", 
-            "type": "BaseCache", 
+            "type": "Cache", 
             "sequential_access": false, 
             "assoc": 8
         }, 
@@ -1416,7 +1419,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 32768, 
                     "tags": {
                         "name": "tags", 
@@ -1450,7 +1453,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu.icache", 
                     "name": "icache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 1
                 }, 
@@ -1505,7 +1508,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 20, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 4194304, 
                     "tags": {
                         "name": "tags", 
@@ -1539,7 +1542,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu.l2cache", 
                     "name": "l2cache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 8
                 }, 
@@ -1586,7 +1589,7 @@
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
                     "response_latency": 2, 
-                    "cxx_class": "BaseCache", 
+                    "cxx_class": "Cache", 
                     "size": 32768, 
                     "tags": {
                         "name": "tags", 
@@ -1620,7 +1623,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu.dcache", 
                     "name": "dcache", 
-                    "type": "BaseCache", 
+                    "type": "Cache", 
                     "sequential_access": false, 
                     "assoc": 4
                 }, 
@@ -1701,7 +1704,7 @@
                     "eventq_index": 0, 
                     "cxx_class": "RawDiskImage", 
                     "path": "system.cf0.image.child", 
-                    "image_file": "/work/gem5/dist/disks/linux-aarch32-ael.img", 
+                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img", 
                     "type": "RawDiskImage"
                 }, 
                 "path": "system.cf0.image", 
@@ -1741,7 +1744,7 @@
             "system.realview.vram"
         ], 
         "work_begin_cpu_id_exit": -1, 
-        "boot_loader": "/work/gem5/dist/binaries/boot_emm.arm", 
+        "boot_loader": "/scratch/nilay/GEM5/system/binaries/boot_emm.arm", 
         "num_work_ids": 16
     }, 
     "time_sync_period": 100000000000, 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index bf070ce25..87bce23ee 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -212,7 +212,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -322,7 +322,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -440,7 +440,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -516,7 +516,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[3]
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -626,7 +626,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -739,7 +739,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -774,7 +774,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1125,9 +1125,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 92530cc80..5d89a381f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -322,7 +322,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -410,7 +410,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -761,9 +761,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 8cc96dcc1..c265e688a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -208,7 +208,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -318,7 +318,7 @@ sys=system
 port=system.cpu0.toL2Bus.slave[2]
 
 [system.cpu0.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -432,7 +432,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -508,7 +508,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[3]
 
 [system.cpu1.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -618,7 +618,7 @@ sys=system
 port=system.cpu1.toL2Bus.slave[2]
 
 [system.cpu1.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -731,7 +731,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -766,7 +766,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -1181,9 +1181,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 8b289555b..97c6a61d0 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -208,7 +208,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -318,7 +318,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -406,7 +406,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -821,9 +821,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index d3065f7a2..48de3cce2 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -212,7 +212,7 @@ sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -511,7 +511,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -546,7 +546,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -897,9 +897,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index c837f36d0..57e7a28ac 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -132,7 +132,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -208,7 +208,7 @@ sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -503,7 +503,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview.
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
@@ -538,7 +538,7 @@ sequential_access=false
 size=1024
 
 [system.l2c]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -953,9 +953,12 @@ gic=system.realview.gic
 int_num=117
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+pxl_clk=system.realview.realview_io.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index be7901250..84c6f9a49 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -134,7 +134,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -184,7 +184,7 @@ system=system
 port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -219,7 +219,7 @@ sequential_access=false
 size=1024
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -285,7 +285,7 @@ system=system
 port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -320,7 +320,7 @@ sequential_access=false
 size=1024
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -827,7 +827,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 1ddef3c2e..f5be22536 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -130,7 +130,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
@@ -180,7 +180,7 @@ system=system
 port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -215,7 +215,7 @@ sequential_access=false
 size=1024
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
@@ -281,7 +281,7 @@ system=system
 port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -316,7 +316,7 @@ sequential_access=false
 size=1024
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -823,7 +823,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:134217727
 assoc=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index b5554ceae..1a6e00d22 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000038                       # Number of seconds simulated
-sim_ticks                                    37623000                       # Number of ticks simulated
-final_tick                                   37623000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    37552000                       # Number of ticks simulated
+final_tick                                   37552000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152308                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152258                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              894784408                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293572                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  72134                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72118                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              423067865                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288748                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           23296                       # Nu
 system.physmem.num_reads::cpu.inst                364                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            619195705                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            287483720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               906679425                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       619195705                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          619195705                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           619195705                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           287483720                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              906679425                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            620366425                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            288027269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               908393694                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       620366425                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          620366425                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           620366425                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           288027269                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              908393694                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           533                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        37518500                       # Total gap between requests
+system.physmem.totGap                        37447500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples           84                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean             384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     247.494057                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.812732                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     247.290862                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.108272                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127             20     23.81%     23.81% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::128-255           19     22.62%     46.43% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383           10     11.90%     58.33% # Bytes accessed per row activation
@@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895            3      3.57%     83.33% # By
 system.physmem.bytesPerActivate::896-1023            6      7.14%     90.48% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            8      9.52%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             84                       # Bytes accessed per row activation
-system.physmem.totQLat                        3336750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13330500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3307750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13301500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6260.32                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6205.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25010.32                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         906.68                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24955.91                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         908.39                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      906.68                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      908.39                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.08                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.08                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.10                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,7 +220,7 @@ system.physmem.readRowHits                        437                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        70391.18                       # Average gap between requests
+system.physmem.avgGap                        70257.97                       # Average gap between requests
 system.physmem.pageHitRate                      81.99                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     226800                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     123750                       # Energy for precharge commands per rank (pJ)
@@ -231,32 +231,32 @@ system.physmem_0.actBackEnergy               21178350                       # En
 system.physmem_0.preBackEnergy                 265500                       # Energy for precharge background per rank (pJ)
 system.physmem_0.totalEnergy                 25872240                       # Total energy per rank (pJ)
 system.physmem_0.averagePower              823.825505                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         435750                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE         346000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        30032750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     347760                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     189750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1544400                       # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy                   1552200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               20558475                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 809250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 25483875                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              811.459163                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        1209750                       # Time in different power states
+system.physmem_1.actBackEnergy               20535390                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 831750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 25491090                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              811.591993                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        1333500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        29169000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        29134000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    1965                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1205                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1556                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     382                       # Number of BTB hits
+system.cpu.branchPred.lookups                    1929                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1187                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               360                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1557                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     398                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             24.550129                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             25.561978                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     224                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1371                       # DTB read hits
+system.cpu.dtb.read_hits                         1369                       # DTB read hits
 system.cpu.dtb.read_misses                         11                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1382                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1380                       # DTB read accesses
 system.cpu.dtb.write_hits                         884                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     887                       # DTB write accesses
-system.cpu.dtb.data_hits                         2255                       # DTB hits
+system.cpu.dtb.data_hits                         2253                       # DTB hits
 system.cpu.dtb.data_misses                         14                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2269                       # DTB accesses
-system.cpu.itb.fetch_hits                        2639                       # ITB hits
+system.cpu.dtb.data_accesses                     2267                       # DTB accesses
+system.cpu.itb.fetch_hits                        2651                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2656                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2668                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,40 +293,40 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            75246                       # number of cpu cycles simulated
+system.cpu.numCycles                            75104                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6400                       # Number of instructions committed
 system.cpu.committedOps                          6400                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1115                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1085                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              11.757188                       # CPI: cycles per instruction
-system.cpu.ipc                               0.085054                       # IPC: instructions per cycle
-system.cpu.tickCycles                           12577                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           62669                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              11.735000                       # CPI: cycles per instruction
+system.cpu.ipc                               0.085215                       # IPC: instructions per cycle
+system.cpu.tickCycles                           12517                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           62587                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.998872                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1975                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           103.919220                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1972                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.686391                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.668639                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.998872                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025390                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025390                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.919220                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025371                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025371                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4573                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4573                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1235                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1235                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4567                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4567                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1232                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1232                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1975                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1975                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1975                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1975                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1972                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1972                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1972                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1972                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
@@ -335,38 +335,38 @@ system.cpu.dcache.demand_misses::cpu.data          227                       # n
 system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          227                       # number of overall misses
 system.cpu.dcache.overall_misses::total           227                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8109500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8109500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      9137500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      9137500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     17247000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     17247000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     17247000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     17247000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1337                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1337                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8311500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8311500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      9136500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      9136500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     17448000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     17448000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     17448000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     17448000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1334                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2202                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2202                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2202                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2202                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076290                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076290                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2199                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2199                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2199                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2199                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076462                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076462                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.103088                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.103088                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.103088                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.103088                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        73100                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        73100                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75977.973568                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75977.973568                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.103229                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.103229                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.103229                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.103229                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        73092                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        73092                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76863.436123                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76863.436123                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          169
 system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7616500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7616500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5372000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5372000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12988500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12988500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12988500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12988500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071803                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071803                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7818500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7818500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5371500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5371500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13190000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13190000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13190000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13190000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071964                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071964                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076748                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076748                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076748                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076748                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73589.041096                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73589.041096                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76855.029586                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76855.029586                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76855.029586                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76855.029586                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076853                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.076853                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076853                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076853                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           175.991805                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2274                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           175.811080                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2286                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.230137                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.263014                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   175.991805                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085933                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085933                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   175.811080                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085845                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085845                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5643                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5643                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         2274                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2274                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2274                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2274                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2274                       # number of overall hits
-system.cpu.icache.overall_hits::total            2274                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5667                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5667                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         2286                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2286                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2286                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2286                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2286                       # number of overall hits
+system.cpu.icache.overall_hits::total            2286                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
 system.cpu.icache.overall_misses::total           365                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     28165000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     28165000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     28165000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     28165000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     28165000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     28165000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2639                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2639                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2639                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2639                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2639                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2639                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138310                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.138310                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.138310                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.138310                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.138310                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.138310                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77164.383562                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77164.383562                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77164.383562                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77164.383562                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77164.383562                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77164.383562                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     27931500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     27931500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     27931500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     27931500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     27931500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     27931500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2651                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2651                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2651                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2651                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2651                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2651                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.137684                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.137684                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.137684                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.137684                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.137684                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.137684                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76524.657534                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76524.657534                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          365
 system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27800000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27800000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27800000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27800000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138310                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138310                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138310                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138310                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138310                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138310                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76164.383562                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76164.383562                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76164.383562                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76164.383562                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76164.383562                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76164.383562                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27566500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     27566500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27566500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     27566500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27566500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     27566500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.137684                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.137684                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.137684                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.137684                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.137684                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.137684                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          233.662872                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          233.447652                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   176.005347                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    57.657524                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005371                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001760                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007131                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.824515                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.623137                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005366                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001759                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007124                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014038                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4805                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4805                       # Number of data accesses
@@ -535,18 +535,18 @@ system.cpu.l2cache.demand_misses::total           533                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          364                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5261500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5261500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27241500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     27241500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7471000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      7471000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     27241500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     12732500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     39974000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     27241500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     12732500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     39974000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5261000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5261000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27008000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     27008000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7673000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7673000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27008000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12934000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     39942000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27008000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12934000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     39942000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          365                       # number of ReadCleanReq accesses(hits+misses)
@@ -571,18 +571,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.998127                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997260                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72075.342466                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72075.342466                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74839.285714                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74839.285714                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.916667                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.916667                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74839.285714                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75340.236686                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74998.123827                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74839.285714                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75340.236686                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74998.123827                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -603,18 +603,18 @@ system.cpu.l2cache.demand_mshr_misses::total          533
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4531500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4531500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23601500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23601500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6511000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6511000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23601500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11042500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     34644000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23601500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11042500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     34644000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4531000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4531000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23368000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23368000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6713000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6713000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23368000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11244000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     34612000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23368000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11244000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     34612000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for ReadCleanReq accesses
@@ -627,18 +627,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
@@ -688,7 +688,7 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 533                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              605000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              602500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            2833000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 5a166e70e..7f87c40d6 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:11:59
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:14:59
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 22074000 because target called exit()
+Exiting @ tick 21900500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 96f652b92..85a8b430a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,51 +1,51 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21947000                       # Number of ticks simulated
-final_tick                                   21947000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21900500                       # Number of ticks simulated
+final_tick                                   21900500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95577                       # Simulator instruction rate (inst/s)
-host_op_rate                                    95558                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              329070081                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294868                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  43231                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              148545474                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 289772                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11072                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                31104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        20032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           20032                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                173                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   486                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            912744339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            504488085                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1417232424                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       912744339                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          912744339                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           912744339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           504488085                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1417232424                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           486                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             19840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             10944                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                30784                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19840                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                310                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   481                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            905915390                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            499714618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1405630008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       905915390                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          905915390                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           905915390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           499714618                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1405630008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           481                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         486                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         481                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    31104                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    30784                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     31104                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     30784                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  69                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  33                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  68                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  47                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  42                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  41                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  20                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                   3                       # Per bank write bursts
@@ -54,7 +54,7 @@ system.physmem.perBankRdBursts::9                   1                       # Pe
 system.physmem.perBankRdBursts::10                 22                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 25                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 14                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                118                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 45                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 12                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21815000                       # Total gap between requests
+system.physmem.totGap                        21763000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     486                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     481                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       138                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       270                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,99 +186,99 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           81                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      332.641975                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     207.725130                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     321.981029                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             25     30.86%     30.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           18     22.22%     53.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     11.11%     64.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            9     11.11%     75.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6      7.41%     82.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            1      1.23%     83.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      3.70%     87.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     12.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             81                       # Bytes accessed per row activation
-system.physmem.totQLat                        4379250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13491750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2430000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9010.80                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           79                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      337.822785                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     215.071445                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.417518                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             21     26.58%     26.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           22     27.85%     54.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            9     11.39%     65.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9     11.39%     77.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      5.06%     82.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.27%     83.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      3.80%     87.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     12.66%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             79                       # Bytes accessed per row activation
+system.physmem.totQLat                        3965000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12983750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2405000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8243.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27760.80                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1417.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26993.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1405.63                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1417.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1405.63                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.07                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.07                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.98                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.98                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        390                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        387                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.25                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.46                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        44886.83                       # Average gap between requests
-system.physmem.pageHitRate                      80.25                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     219240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     119625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   1653600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        45245.32                       # Average gap between requests
+system.physmem.pageHitRate                      80.46                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     196560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     107250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   1630200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
 system.physmem_0.actBackEnergy               10785825                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  38250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 13833660                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              873.750829                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
+system.physmem_0.totalEnergy                 13775205                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              870.058740                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         209750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        15303750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     325080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     177375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1271400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     317520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     173250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1287000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10129185                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 614250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13534410                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              854.849834                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         953500                       # Time in different power states
+system.physmem_1.actBackEnergy               10183905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 566250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 13545045                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              855.521554                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         873500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14372750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14452750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2810                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1662                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               478                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2116                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     679                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2551                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1518                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               429                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1991                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     726                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.088847                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     396                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             36.464088                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     383                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 29                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         2105                       # DTB read hits
-system.cpu.dtb.read_misses                         55                       # DTB read misses
+system.cpu.dtb.read_hits                         2033                       # DTB read hits
+system.cpu.dtb.read_misses                         43                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2160                       # DTB read accesses
-system.cpu.dtb.write_hits                        1074                       # DTB write hits
-system.cpu.dtb.write_misses                        30                       # DTB write misses
+system.cpu.dtb.read_accesses                     2076                       # DTB read accesses
+system.cpu.dtb.write_hits                        1052                       # DTB write hits
+system.cpu.dtb.write_misses                        28                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1104                       # DTB write accesses
-system.cpu.dtb.data_hits                         3179                       # DTB hits
-system.cpu.dtb.data_misses                         85                       # DTB misses
+system.cpu.dtb.write_accesses                    1080                       # DTB write accesses
+system.cpu.dtb.data_hits                         3085                       # DTB hits
+system.cpu.dtb.data_misses                         71                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3264                       # DTB accesses
-system.cpu.itb.fetch_hits                        2194                       # ITB hits
-system.cpu.itb.fetch_misses                        34                       # ITB misses
+system.cpu.dtb.data_accesses                     3156                       # DTB accesses
+system.cpu.itb.fetch_hits                        2086                       # ITB hits
+system.cpu.itb.fetch_misses                        32                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2228                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2118                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -292,237 +292,237 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            43895                       # number of cpu cycles simulated
+system.cpu.numCycles                            43802                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8597                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16278                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2810                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1075                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4298                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1038                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           740                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2194                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   338                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14179                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.148036                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.557344                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               8360                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14953                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2551                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1109                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4527                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     940                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   24                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           730                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2086                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   308                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14111                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.059670                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.447373                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11320     79.84%     79.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      289      2.04%     81.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      216      1.52%     83.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      204      1.44%     84.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      243      1.71%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      208      1.47%     88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      242      1.71%     89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      175      1.23%     90.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1282      9.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11381     80.65%     80.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      309      2.19%     82.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      232      1.64%     84.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      210      1.49%     85.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      257      1.82%     87.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      204      1.45%     89.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      249      1.76%     91.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      144      1.02%     92.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1125      7.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14179                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.064016                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.370840                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8623                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2500                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2414                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   200                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    442                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  227                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    81                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14886                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   224                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    442                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8796                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1074                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            427                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2425                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1015                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14276                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     19                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                     33                       # Number of times rename has blocked due to LQ full
+system.cpu.fetch.rateDist::total                14111                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.058239                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.341377                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8350                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2903                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2283                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   178                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    397                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  199                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    74                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  13658                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   213                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    397                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8499                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1362                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            551                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2297                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1005                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  13185                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     29                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                      9                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                    937                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               10794                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17927                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17918                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                9916                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 16517                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            16508                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6224                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                     5346                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       538                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2680                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1315                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       571                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2513                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1264                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      12940                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      12094                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10735                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                20                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6595                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3561                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     10150                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                 8                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            5749                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3122                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14179                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.757106                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.490778                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14111                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.719297                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.444291                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10173     71.75%     71.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1278      9.01%     80.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 898      6.33%     87.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 679      4.79%     91.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 528      3.72%     95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 333      2.35%     97.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 209      1.47%     99.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  55      0.39%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  26      0.18%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10252     72.65%     72.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1258      8.92%     81.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 873      6.19%     87.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 669      4.74%     92.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 489      3.47%     95.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 327      2.32%     98.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 176      1.25%     99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  44      0.31%     99.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  23      0.16%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14179                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14111                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      29     20.14%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     20.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     73     50.69%     70.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    42     29.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      18     13.64%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     13.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     73     55.30%     68.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    41     31.06%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7243     67.47%     67.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2356     21.95%     89.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1131     10.54%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  6822     67.21%     67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2214     21.81%     89.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1109     10.93%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10735                       # Type of FU issued
-system.cpu.iq.rate                           0.244561                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         144                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013414                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              35792                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19571                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9784                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  10150                       # Type of FU issued
+system.cpu.iq.rate                           0.231725                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         132                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013005                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              34530                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             17879                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9316                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10866                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10269                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               71                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               64                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1497                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1330                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          450                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          399                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            65                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            71                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    442                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1033                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    23                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13054                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               109                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2680                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1315                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    397                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1267                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    27                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               12206                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               103                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2513                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1264                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      1                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                    20                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             81                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          395                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  476                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10242                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2163                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               493                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             85                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          341                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  426                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  9752                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2076                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               398                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            86                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3269                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1598                       # Number of branches executed
-system.cpu.iew.exec_stores                       1106                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.233330                       # Inst execution rate
-system.cpu.iew.wb_sent                           9957                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9794                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5300                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7297                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            84                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3158                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1540                       # Number of branches executed
+system.cpu.iew.exec_stores                       1082                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.222638                       # Inst execution rate
+system.cpu.iew.wb_sent                           9474                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9326                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4992                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6833                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.223123                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.726326                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.212913                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.730572                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            6664                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5821                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               401                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12978                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.492295                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.405132                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               356                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13063                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.489091                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.409393                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10520     81.06%     81.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1167      8.99%     90.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          504      3.88%     93.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          209      1.61%     95.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          136      1.05%     96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           76      0.59%     97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           89      0.69%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           87      0.67%     98.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          190      1.46%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10626     81.34%     81.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1163      8.90%     90.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          487      3.73%     93.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          202      1.55%     95.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          127      0.97%     96.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           82      0.63%     97.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           98      0.75%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           84      0.64%     98.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          194      1.49%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13063                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
 system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -568,186 +568,186 @@ system.cpu.commit.op_class_0::MemWrite            865     13.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   190                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        25490                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27321                       # The number of ROB writes
-system.cpu.timesIdled                             258                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29716                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   194                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        24728                       # The number of ROB reads
+system.cpu.rob.rob_writes                       25475                       # The number of ROB writes
+system.cpu.timesIdled                             260                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           29691                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
 system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.888732                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.888732                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.145165                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.145165                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13013                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7460                       # number of integer regfile writes
+system.cpu.cpi                               6.874137                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.874137                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.145473                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.145473                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12362                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7056                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           107.548347                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2343                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               173                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.543353                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           107.516544                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2276                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               171                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.309942                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   107.548347                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026257                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026257                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          173                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data   107.516544                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026249                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026249                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          171                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.042236                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5891                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5891                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1835                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1835                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          508                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            508                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2343                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2343                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2343                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2343                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          159                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           159                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          357                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          357                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          516                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            516                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          516                       # number of overall misses
-system.cpu.dcache.overall_misses::total           516                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11993500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11993500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24175975                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24175975                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36169475                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36169475                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36169475                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36169475                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1994                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1994                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.041748                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5747                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5747                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1770                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1770                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2276                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2276                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2276                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2276                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          153                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           153                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          512                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            512                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          512                       # number of overall misses
+system.cpu.dcache.overall_misses::total           512                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11315000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11315000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     23651475                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     23651475                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     34966475                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     34966475                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     34966475                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     34966475                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1923                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1923                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2859                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2859                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2859                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2859                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079739                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.079739                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.412717                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.412717                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.180483                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.180483                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.180483                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.180483                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70095.881783                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70095.881783                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2284                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2788                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2788                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2788                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2788                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079563                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.079563                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.183644                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.183644                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.183644                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.183644                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 68293.896484                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68293.896484                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         2328                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                41                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                42                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.707317                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.428571                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           58                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          285                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          285                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          343                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          343                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          343                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          343                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          101                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           54                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          287                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          287                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          341                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          341                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          341                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          341                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           99                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           99                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8588000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8588000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5911000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5911000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14499000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     14499000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14499000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     14499000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050652                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050652                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          171                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          171                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          171                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          171                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8341000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8341000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5669500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5669500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14010500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     14010500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14010500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     14010500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051482                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051482                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.060511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.060511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.060511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.060511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.061334                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.061334                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.061334                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.061334                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           158.228991                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1714                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.458599                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           157.774053                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1627                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               311                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.231511                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   158.228991                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077260                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077260                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   157.774053                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077038                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077038                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4702                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4702                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1714                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1714                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1714                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1714                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1714                       # number of overall hits
-system.cpu.icache.overall_hits::total            1714                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          480                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           480                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          480                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            480                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          480                       # number of overall misses
-system.cpu.icache.overall_misses::total           480                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     33574500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     33574500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     33574500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     33574500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     33574500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     33574500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2194                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2194                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2194                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2194                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2194                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2194                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.218778                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.218778                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.218778                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.218778                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.218778                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.218778                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69946.875000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69946.875000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69946.875000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69946.875000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69946.875000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69946.875000                       # average overall miss latency
+system.cpu.icache.tags.occ_task_id_percent::1024     0.151855                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4483                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4483                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1627                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1627                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1627                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1627                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1627                       # number of overall hits
+system.cpu.icache.overall_hits::total            1627                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          459                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           459                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          459                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            459                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          459                       # number of overall misses
+system.cpu.icache.overall_misses::total           459                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32352500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32352500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32352500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32352500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32352500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32352500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2086                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2086                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2086                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2086                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2086                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2086                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.220038                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.220038                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.220038                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.220038                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.220038                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.220038                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70484.749455                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70484.749455                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -756,54 +756,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          166                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          166                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          166                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          166                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          166                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          166                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          314                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          314                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          314                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24137500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24137500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24137500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24137500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24137500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24137500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143118                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143118                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143118                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.143118                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143118                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.143118                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76871.019108                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76871.019108                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76871.019108                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76871.019108                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76871.019108                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76871.019108                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          148                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          148                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          148                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          148                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          148                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          148                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          311                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          311                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          311                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          311                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          311                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          311                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23859500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23859500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23859500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23859500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23859500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23859500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.149089                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.149089                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.149089                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.149089                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.149089                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.149089                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          218.935718                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          218.211579                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              414                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              409                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002445                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   158.272937                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    60.662780                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004830                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001851                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006681                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          414                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   157.816586                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    60.394993                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004816                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001843                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006659                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012634                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4382                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4382                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012482                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4337                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4337                       # Number of data accesses
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -812,64 +812,64 @@ system.cpu.l2cache.overall_hits::cpu.inst            1                       # n
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data           72                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           72                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          313                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          313                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          101                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          101                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          313                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          173                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           486                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          313                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          173                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          486                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5800000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5800000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     23655000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     23655000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8428500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      8428500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     23655000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     14228500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     37883500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     23655000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     14228500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     37883500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          310                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          310                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           99                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           99                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          310                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          171                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           481                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          310                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          171                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          481                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5558500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5558500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     23380000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     23380000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8185000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      8185000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     23380000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     13743500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     37123500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23380000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     13743500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     37123500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           72                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           72                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          314                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          314                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          314                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          173                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          487                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          314                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          173                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          487                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          311                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          311                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           99                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           99                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          311                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          171                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          482                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          311                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          171                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          482                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996815                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996815                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996785                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996785                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996815                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996785                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997947                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996815                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997925                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996785                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997947                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80555.555556                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80555.555556                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75575.079872                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75575.079872                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83450.495050                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83450.495050                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75575.079872                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82245.664740                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77949.588477                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75575.079872                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82245.664740                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77949.588477                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997925                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77179.833680                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77179.833680                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -880,104 +880,104 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           72                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           72                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          313                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          313                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          101                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          101                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          173                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          486                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          486                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     20525000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     20525000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7418500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7418500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20525000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12498500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     33023500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20525000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12498500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     33023500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          310                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          310                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           99                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           99                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          310                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          171                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          481                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          310                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          171                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          481                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4838500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4838500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     20280000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     20280000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7195000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7195000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     12033500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     32313500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     12033500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     32313500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996815                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996785                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996785                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996785                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997947                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997925                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996785                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997947                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997925                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp           415                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           410                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          314                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          346                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               974                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              31168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          311                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           99                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          622                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          342                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               964                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30848                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          487                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          482                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                487    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                482    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            487                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         243500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            482                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         241000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        471000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        466500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        259500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        256500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                414                       # Transaction distribution
+system.membus.trans_dist::ReadResp                409                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           414                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          972                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    972                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   31104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq           409                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          962                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    962                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   30784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               486                       # Request fanout histogram
+system.membus.snoop_fanout::samples               481                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     486    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     481    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 486                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              594500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 481                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              586000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2585500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2558250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index e07ba072a..5b279bd35 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 011f7e597..bf628f608 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3ff859531..7d246ed9e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 7c57b2554..2f7c0906a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20091000                       # Number of ticks simulated
-final_tick                                   20091000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20075000                       # Number of ticks simulated
+final_tick                                   20075000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125803                       # Simulator instruction rate (inst/s)
-host_op_rate                                   125723                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              976523768                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293292                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                  42420                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42407                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              329231154                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 287436                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           14272                       # Nu
 system.physmem.num_reads::cpu.inst                223                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   308                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            710367826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            270768006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               981135832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       710367826                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          710367826                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           710367826                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           270768006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              981135832                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            710933998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            270983811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               981917808                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       710933998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          710933998                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           710933998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           270983811                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              981917808                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           308                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         308                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20003000                       # Total gap between requests
+system.physmem.totGap                        19987000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895            3      7.32%     85.37% # By
 system.physmem.bytesPerActivate::896-1023            3      7.32%     92.68% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            3      7.32%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
-system.physmem.totQLat                        1567250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7342250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1568250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7343250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5088.47                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5091.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23838.47                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         981.14                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23841.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         981.92                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      981.14                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      981.92                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           7.67                       # Data bus utilization in percentage
@@ -220,7 +220,7 @@ system.physmem.readRowHits                        258                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.77                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        64944.81                       # Average gap between requests
+system.physmem.avgGap                        64892.86                       # Average gap between requests
 system.physmem.pageHitRate                      83.77                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                      83160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      45375                       # Energy for precharge commands per rank (pJ)
@@ -231,7 +231,7 @@ system.physmem_0.actBackEnergy               10605420                       # En
 system.physmem_0.preBackEnergy                 196500                       # Energy for precharge background per rank (pJ)
 system.physmem_0.totalEnergy                 12727575                       # Total energy per rank (pJ)
 system.physmem_0.averagePower              803.889152                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         536250                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE         534250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        15041250                       # Time in different power states
@@ -241,22 +241,22 @@ system.physmem_1.preEnergy                     103125                       # En
 system.physmem_1.readEnergy                   1201200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10489995                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy               10488285                       # Energy for active background per rank (pJ)
 system.physmem_1.preBackEnergy                 299250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13299690                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              839.892011                       # Core power per rank (mW)
+system.physmem_1.totalEnergy                 13297980                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              839.916627                       # Core power per rank (mW)
 system.physmem_1.memoryStateTime::IDLE         457000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14871250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14869250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                     793                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               397                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               168                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  563                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                      58                       # Number of BTB hits
+system.cpu.branchPred.lookups                     787                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               394                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               164                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  560                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                      60                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             10.301954                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             10.714286                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     138                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  2                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          509                       # DTB read hits
+system.cpu.dtb.read_hits                          506                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      516                       # DTB read accesses
+system.cpu.dtb.read_accesses                      513                       # DTB read accesses
 system.cpu.dtb.write_hits                         307                       # DTB write hits
 system.cpu.dtb.write_misses                         6                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     313                       # DTB write accesses
-system.cpu.dtb.data_hits                          816                       # DTB hits
+system.cpu.dtb.data_hits                          813                       # DTB hits
 system.cpu.dtb.data_misses                         13                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                      829                       # DTB accesses
-system.cpu.itb.fetch_hits                         971                       # ITB hits
+system.cpu.dtb.data_accesses                      826                       # DTB accesses
+system.cpu.itb.fetch_hits                         965                       # ITB hits
 system.cpu.itb.fetch_misses                        13                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     984                       # ITB accesses
+system.cpu.itb.fetch_accesses                     978                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,40 +293,40 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            40182                       # number of cpu cycles simulated
+system.cpu.numCycles                            40150                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2585                       # Number of instructions committed
 system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                           594                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                           581                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              15.544294                       # CPI: cycles per instruction
-system.cpu.ipc                               0.064332                       # IPC: instructions per cycle
-system.cpu.tickCycles                            5392                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           34790                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              15.531915                       # CPI: cycles per instruction
+system.cpu.ipc                               0.064384                       # IPC: instructions per cycle
+system.cpu.tickCycles                            5369                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           34781                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            48.329975                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            48.313800                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 689                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.105882                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    48.329975                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011799                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011799                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    48.313800                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011795                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011795                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1677                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1677                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          441                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             441                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              1671                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1671                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          438                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             438                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          251                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           692                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              692                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          692                       # number of overall hits
-system.cpu.dcache.overall_hits::total             692                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data           689                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              689                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          689                       # number of overall hits
+system.cpu.dcache.overall_hits::total             689                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
@@ -343,22 +343,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7981500
 system.cpu.dcache.demand_miss_latency::total      7981500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7981500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7981500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          502                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          502                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data          499                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          499                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          796                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          796                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          796                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          796                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.121514                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.121514                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data          793                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          793                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          793                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          793                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.122244                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.122244                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.146259                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.130653                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.130653                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.130653                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.130653                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.131148                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.131148                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.131148                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.131148                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767                       # average WriteReq miss latency
@@ -399,14 +399,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6459500
 system.cpu.dcache.demand_mshr_miss_latency::total      6459500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6459500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      6459500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.115538                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.115538                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.116232                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116232                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.106784                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.106784                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.106784                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.106784                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.107188                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.107188                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.107188                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.107188                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222                       # average WriteReq mshr miss latency
@@ -417,56 +417,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           117.935175                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 748                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           117.873256                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 742                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               223                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.354260                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.327354                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   117.935175                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.057586                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.057586                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   117.873256                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.057555                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.057555                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          223                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2165                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2165                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          748                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             748                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           748                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              748                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          748                       # number of overall hits
-system.cpu.icache.overall_hits::total             748                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              2153                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2153                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst          742                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             742                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           742                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              742                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          742                       # number of overall hits
+system.cpu.icache.overall_hits::total             742                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          223                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           223                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          223                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            223                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          223                       # number of overall misses
 system.cpu.icache.overall_misses::total           223                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16978500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16978500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16978500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16978500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16978500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16978500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          971                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          971                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          971                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          971                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          971                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          971                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229660                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.229660                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.229660                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.229660                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.229660                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.229660                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76136.771300                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76136.771300                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76136.771300                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76136.771300                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76136.771300                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76136.771300                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16979500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16979500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16979500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16979500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16979500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16979500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          965                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          965                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          965                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          965                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          965                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          965                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.231088                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.231088                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.231088                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.231088                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.231088                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.231088                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76141.255605                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76141.255605                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76141.255605                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76141.255605                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76141.255605                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76141.255605                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          223
 system.cpu.icache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16755500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16755500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16755500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16755500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16755500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16755500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.229660                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.229660                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.229660                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.229660                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.229660                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.229660                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75136.771300                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75136.771300                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75136.771300                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75136.771300                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75136.771300                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75136.771300                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16756500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16756500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16756500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16756500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16756500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16756500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231088                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231088                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231088                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.231088                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231088                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.231088                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75141.255605                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75141.255605                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75141.255605                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75141.255605                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75141.255605                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75141.255605                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          145.853573                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          145.780629                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              281                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   118.051720                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    27.801853                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003603                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   117.989893                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    27.790736                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003601                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000848                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004451                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004449                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
@@ -531,16 +531,16 @@ system.cpu.l2cache.overall_misses::cpu.data           85                       #
 system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1977000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      1977000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16421000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     16421000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16422000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     16422000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4354000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::total      4354000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16421000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     16422000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      6331000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     22752000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16421000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total     22753000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     16422000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      6331000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     22752000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22753000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          223                       # number of ReadCleanReq accesses(hits+misses)
@@ -567,16 +567,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data            1
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -599,16 +599,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data           85
 system.cpu.l2cache.overall_mshr_misses::total          308                       # number of overall MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1707000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1707000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14191000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14191000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14192000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14192000                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3774000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3774000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14191000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14192000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5481000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     19672000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14191000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19673000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14192000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5481000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     19672000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19673000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
@@ -623,16 +623,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index ee80959b5..6ee889334 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    12591500                       # Number of ticks simulated
-final_tick                                   12591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000012                       # Number of seconds simulated
+sim_ticks                                    12363500                       # Number of ticks simulated
+final_tick                                   12363500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  74456                       # Simulator instruction rate (inst/s)
-host_op_rate                                    74426                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              392441951                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293552                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  20992                       # Simulator instruction rate (inst/s)
+host_op_rate                                    20989                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              108692792                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288464                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           11968                       # Nu
 system.physmem.num_reads::cpu.inst                187                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   272                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            950482468                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            432037486                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1382519954                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       950482468                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          950482468                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           950482468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           432037486                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1382519954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            968010677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            440004853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1408015530                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       968010677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          968010677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           968010677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           440004853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1408015530                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           272                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         272                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        12495000                       # Total gap between requests
+system.physmem.totGap                        12267000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       156                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        82                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       152                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -200,27 +200,27 @@ system.physmem.bytesPerActivate::768-895            2      5.56%     83.33% # By
 system.physmem.bytesPerActivate::896-1023            1      2.78%     86.11% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            5     13.89%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             36                       # Bytes accessed per row activation
-system.physmem.totQLat                        1676750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   6776750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1685750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   6785750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1360000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6164.52                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6197.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24914.52                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1382.52                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24947.61                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1408.02                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1382.52                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1408.02                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.80                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.80                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.00                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.69                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
 system.physmem.readRowHits                        226                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.09                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45937.50                       # Average gap between requests
+system.physmem.avgGap                        45099.26                       # Average gap between requests
 system.physmem.pageHitRate                      83.09                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
@@ -250,36 +250,36 @@ system.physmem_1.memoryStateTime::REF          260000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT         7371500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    1086                       # Number of BP lookups
-system.cpu.branchPred.condPredicted               546                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               229                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                  723                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     206                       # Number of BTB hits
+system.cpu.branchPred.lookups                     890                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               443                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               195                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  616                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     164                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             28.492393                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     197                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             26.623377                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     186                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  9                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          688                       # DTB read hits
-system.cpu.dtb.read_misses                         18                       # DTB read misses
+system.cpu.dtb.read_hits                          719                       # DTB read hits
+system.cpu.dtb.read_misses                         10                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      706                       # DTB read accesses
-system.cpu.dtb.write_hits                         353                       # DTB write hits
-system.cpu.dtb.write_misses                        17                       # DTB write misses
+system.cpu.dtb.read_accesses                      729                       # DTB read accesses
+system.cpu.dtb.write_hits                         347                       # DTB write hits
+system.cpu.dtb.write_misses                        16                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     370                       # DTB write accesses
-system.cpu.dtb.data_hits                         1041                       # DTB hits
-system.cpu.dtb.data_misses                         35                       # DTB misses
+system.cpu.dtb.write_accesses                     363                       # DTB write accesses
+system.cpu.dtb.data_hits                         1066                       # DTB hits
+system.cpu.dtb.data_misses                         26                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1076                       # DTB accesses
-system.cpu.itb.fetch_hits                         931                       # ITB hits
-system.cpu.itb.fetch_misses                        26                       # ITB misses
+system.cpu.dtb.data_accesses                     1092                       # DTB accesses
+system.cpu.itb.fetch_hits                         802                       # ITB hits
+system.cpu.itb.fetch_misses                        35                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                     957                       # ITB accesses
+system.cpu.itb.fetch_accesses                     837                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,236 +293,235 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            25184                       # number of cpu cycles simulated
+system.cpu.numCycles                            24728                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               4404                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                           6508                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1086                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                403                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          1405                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     504                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               4265                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                           5512                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                         890                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                350                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          1015                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     436                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1109                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          1206                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                       931                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   153                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               7199                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.904014                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.325149                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                       802                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   146                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples               6733                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.818654                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.224131                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     6086     84.54%     84.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       49      0.68%     85.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      124      1.72%     86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       82      1.14%     88.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      134      1.86%     89.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       58      0.81%     90.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       66      0.92%     91.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       57      0.79%     92.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      543      7.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     5799     86.13%     86.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       30      0.45%     86.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                       91      1.35%     87.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                       76      1.13%     89.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      118      1.75%     90.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       72      1.07%     91.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       40      0.59%     92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       56      0.83%     93.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      451      6.70%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 7199                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.043123                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.258418                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5197                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   794                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                       972                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    58                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    178                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  158                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    76                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   5639                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   276                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    178                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     5280                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     486                       # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total                 6733                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.035992                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.222905                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5190                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   505                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                       865                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    28                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    145                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  132                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    75                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                   4839                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   268                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    145                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     5257                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     212                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            288                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                       942                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                    25                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5401                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     13                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RenamedOperands                3881                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  6093                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             6086                       # Number of integer rename lookups
+system.cpu.rename.RunCycles                       824                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                     7                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   4680                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenamedOperands                3347                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  5277                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             5270                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 6                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     2113                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     1579                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       109                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  882                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 453                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 2                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4674                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                        52                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                  795                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 418                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 0                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                       4078                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      3880                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                15                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2292                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1214                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      3608                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                32                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            1696                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined          859                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          7199                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.538964                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.280196                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          6733                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.535868                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.279819                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                5699     79.16%     79.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 500      6.95%     86.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 351      4.88%     90.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 251      3.49%     94.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 194      2.69%     97.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 116      1.61%     98.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  57      0.79%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  21      0.29%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  10      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                5352     79.49%     79.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 449      6.67%     86.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 318      4.72%     90.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 240      3.56%     94.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 185      2.75%     97.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 110      1.63%     98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  49      0.73%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  21      0.31%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   9      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            7199                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            6733                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       6     11.76%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     22     43.14%     54.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    23     45.10%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6      8.70%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     39     56.52%     65.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    24     34.78%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2765     71.26%     71.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.03%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  738     19.02%     90.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 376      9.69%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2482     68.79%     68.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.03%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  757     20.98%     89.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 368     10.20%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   3880                       # Type of FU issued
-system.cpu.iq.rate                           0.154066                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                          51                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013144                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              15012                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              6969                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3584                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   3608                       # Type of FU issued
+system.cpu.iq.rate                           0.145907                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                          69                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019124                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              14037                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              5777                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3273                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   3924                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   3670                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               28                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          467                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          380                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            4                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          159                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          124                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            24                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            91                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    178                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     422                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     4                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                5018                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                28                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   882                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  453                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    145                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     186                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     0                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts                4365                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                29                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                   795                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  418                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              4                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             21                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          168                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  189                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3751                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   707                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               129                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             20                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          120                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  140                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  3509                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   730                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts                99                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           338                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1077                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      639                       # Number of branches executed
-system.cpu.iew.exec_stores                        370                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.148944                       # Inst execution rate
-system.cpu.iew.wb_sent                           3648                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3590                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1708                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2182                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           281                       # number of nop insts executed
+system.cpu.iew.exec_refs                         1093                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      570                       # Number of branches executed
+system.cpu.iew.exec_stores                        363                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.141904                       # Inst execution rate
+system.cpu.iew.wb_sent                           3329                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3279                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1560                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      1998                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.142551                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.782768                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.132603                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.780781                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            2428                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            1787                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               155                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         6748                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.381743                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.245988                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               122                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples         6402                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.402374                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.273029                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         5894     87.34%     87.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          193      2.86%     90.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          303      4.49%     94.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          109      1.62%     96.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4           72      1.07%     97.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           56      0.83%     98.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           33      0.49%     98.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           20      0.30%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           68      1.01%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5545     86.61%     86.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          194      3.03%     89.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          304      4.75%     94.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          116      1.81%     96.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           62      0.97%     97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           60      0.94%     98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           35      0.55%     98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           20      0.31%     98.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           66      1.03%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         6748                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         6402                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -568,101 +567,101 @@ system.cpu.commit.op_class_0::MemWrite            294     11.41%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              2576                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                    68                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        11437                       # The number of ROB reads
-system.cpu.rob.rob_writes                       10476                       # The number of ROB writes
-system.cpu.timesIdled                             151                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           17985                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                    66                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        10452                       # The number of ROB reads
+system.cpu.rob.rob_writes                        9060                       # The number of ROB writes
+system.cpu.timesIdled                             153                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           17995                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                              10.550482                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        10.550482                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.094782                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.094782                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4532                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2777                       # number of integer regfile writes
+system.cpu.cpi                              10.359447                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                        10.359447                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.096530                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.096530                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4249                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2511                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            45.864197                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 731                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            45.334739                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 716                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.600000                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.423529                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    45.864197                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011197                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011197                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    45.334739                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011068                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011068                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1937                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1937                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          518                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             518                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              1873                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1873                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          503                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             503                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           731                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              731                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          731                       # number of overall hits
-system.cpu.dcache.overall_hits::total             731                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          114                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           114                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data           716                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              716                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          716                       # number of overall hits
+system.cpu.dcache.overall_hits::total             716                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          195                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            195                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          195                       # number of overall misses
-system.cpu.dcache.overall_misses::total           195                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7589500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7589500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5666500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5666500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13256000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13256000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13256000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13256000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          632                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          632                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          178                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            178                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          178                       # number of overall misses
+system.cpu.dcache.overall_misses::total           178                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6583000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6583000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5672000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5672000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     12255000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     12255000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     12255000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     12255000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          600                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          600                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          926                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          926                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          926                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          926                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180380                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180380                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data          894                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          894                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          894                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          894                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.161667                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.161667                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.210583                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.210583                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.210583                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.210583                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67979.487179                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67979.487179                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          139                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.199105                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.199105                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.199105                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.199105                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67865.979381                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67865.979381                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 68848.314607                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 68848.314607                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 68848.314607                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68848.314607                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          292                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 9                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    32.444444                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           53                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           53                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           36                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           36                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          110                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          110                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          110                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          110                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           93                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           93                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           93                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           93                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
@@ -671,82 +670,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4809500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4809500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4810000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4810000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1851000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      1851000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6660500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6660500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6660500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6660500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096519                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096519                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.101667                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.101667                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091793                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091793                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091793                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091793                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.095078                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.095078                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.095078                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.095078                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78852.459016                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78852.459016                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        77125                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        77125                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78364.705882                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78364.705882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78364.705882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78364.705882                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            91.507771                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 679                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse            90.143737                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 552                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               187                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.631016                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              2.951872                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    91.507771                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.044682                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.044682                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    90.143737                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.044015                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.044015                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          187                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.091309                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              2049                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             2049                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst          679                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             679                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           679                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              679                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          679                       # number of overall hits
-system.cpu.icache.overall_hits::total             679                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          252                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           252                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          252                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            252                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          252                       # number of overall misses
-system.cpu.icache.overall_misses::total           252                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     18724999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     18724999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     18724999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     18724999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     18724999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     18724999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          931                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          931                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          931                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          931                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          931                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          931                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.270677                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.270677                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.270677                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.270677                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.270677                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.270677                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74305.551587                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74305.551587                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74305.551587                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74305.551587                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74305.551587                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74305.551587                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses              1791                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             1791                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst          552                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             552                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           552                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              552                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          552                       # number of overall hits
+system.cpu.icache.overall_hits::total             552                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          250                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           250                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          250                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            250                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          250                       # number of overall misses
+system.cpu.icache.overall_misses::total           250                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     18739499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     18739499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     18739499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     18739499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     18739499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     18739499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          802                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          802                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          802                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          802                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.311721                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.311721                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.311721                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.311721                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.311721                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.311721                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74957.996000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 74957.996000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 74957.996000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 74957.996000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 74957.996000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 74957.996000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          125                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -755,51 +754,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    62.500000
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           65                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           65                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           65                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           65                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           65                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           63                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           63                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           63                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           63                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           63                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           63                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          187                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          187                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          187                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          187                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          187                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14173499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14173499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14173499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14173499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14173499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14173499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.200859                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.200859                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.200859                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.200859                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.200859                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.200859                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75794.112299                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75794.112299                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75794.112299                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75794.112299                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75794.112299                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75794.112299                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14179499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14179499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14179499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14179499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14179499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14179499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.233167                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.233167                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.233167                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.233167                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.233167                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.233167                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75826.197861                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75826.197861                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75826.197861                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75826.197861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75826.197861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75826.197861                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          120.686426                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          118.927175                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              248                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    91.663709                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    29.022716                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002797                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000886                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.003683                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.302552                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    28.624623                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002756                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000874                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003629                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          248                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           48                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          205                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.007568                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2448                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2448                       # Number of data accesses
@@ -817,16 +816,16 @@ system.cpu.l2cache.overall_misses::cpu.data           85                       #
 system.cpu.l2cache.overall_misses::total          272                       # number of overall misses
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1813500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      1813500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     13892000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     13892000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4718000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      4718000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     13892000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6531500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     20423500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     13892000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6531500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     20423500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     13898000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     13898000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4718500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4718500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     13898000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6532000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     20430000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     13898000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6532000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     20430000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          187                       # number of ReadCleanReq accesses(hits+misses)
@@ -853,16 +852,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data            1
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74288.770053                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74288.770053                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77344.262295                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77344.262295                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74288.770053                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76841.176471                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75086.397059                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74288.770053                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74320.855615                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74320.855615                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77352.459016                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77352.459016                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74320.855615                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76847.058824                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75110.294118                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74320.855615                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76847.058824                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75110.294118                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -885,16 +884,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data           85
 system.cpu.l2cache.overall_mshr_misses::total          272                       # number of overall MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1573500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1573500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     12022000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     12022000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4108000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4108000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12022000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5681500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17703500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12022000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5681500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17703500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     12028000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     12028000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4108500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4108500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12028000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5682000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17710000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12028000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5682000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17710000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
@@ -909,16 +908,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64320.855615                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64320.855615                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67352.459016                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67352.459016                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64320.855615                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66847.058824                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65110.294118                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
@@ -946,7 +945,7 @@ system.cpu.toL2Bus.snoop_fanout::total            272                       # Re
 system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        280500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                248                       # Transaction distribution
@@ -968,9 +967,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 272                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              337000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              335500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            1441250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            1441000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 32421c7b3..0c42ac84b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 0d1926cd4..f0b756165 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index ebc9b7aa1..a00344038 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index d78920aa6..6e0294d29 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 408894bb9..46fd0f447 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -228,7 +228,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index e5ff065c1..3e86bd3ac 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29934500                       # Number of ticks simulated
-final_tick                                   29934500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    29941500                       # Number of ticks simulated
+final_tick                                   29941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115469                       # Simulator instruction rate (inst/s)
-host_op_rate                                   135130                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              750106498                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310152                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  58660                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68656                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              381226078                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304332                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           19520                       # Nu
 system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            652090397                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            248008151                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               900098548                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       652090397                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          652090397                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           652090397                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           248008151                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              900098548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            651937946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            247950169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               899888115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       651937946                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          651937946                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           651937946                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           247950169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              899888115                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        29844000                       # Total gap between requests
+system.physmem.totGap                        29851000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895            3      4.84%     83.87% # By
 system.physmem.bytesPerActivate::896-1023            1      1.61%     85.48% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
-system.physmem.totQLat                        2214000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10107750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        2218000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10111750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5258.91                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5268.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24008.91                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         900.10                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24018.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         899.89                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      900.10                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      899.89                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           7.03                       # Data bus utilization in percentage
@@ -220,7 +220,7 @@ system.physmem.readRowHits                        350                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        70888.36                       # Average gap between requests
+system.physmem.avgGap                        70904.99                       # Average gap between requests
 system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     272160                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     148500                       # Energy for precharge commands per rank (pJ)
@@ -250,14 +250,14 @@ system.physmem_1.memoryStateTime::REF          780000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT        22328250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    1918                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1150                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               336                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1604                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     341                       # Number of BTB hits
+system.cpu.branchPred.lookups                    1912                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1153                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               338                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1608                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     347                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             21.259352                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     218                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             21.579602                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     219                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -377,44 +377,44 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            59869                       # number of cpu cycles simulated
+system.cpu.numCycles                            59883                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4605                       # Number of instructions committed
 system.cpu.committedOps                          5391                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1116                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1120                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              13.000869                       # CPI: cycles per instruction
-system.cpu.ipc                               0.076918                       # IPC: instructions per cycle
-system.cpu.tickCycles                           10574                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           49295                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              13.003909                       # CPI: cycles per instruction
+system.cpu.ipc                               0.076900                       # IPC: instructions per cycle
+system.cpu.tickCycles                           10593                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           49290                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            86.493580                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1918                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            86.506122                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1915                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.136986                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.116438                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    86.493580                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021117                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021117                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.506122                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021120                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021120                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4346                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4346                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1050                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1050                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              4340                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4340                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1047                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1047                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1896                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1896                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1896                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1896                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1893                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1893                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1893                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1893                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           67                       # number of WriteReq misses
@@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data          182                       # n
 system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
 system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6956000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6956000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6956500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6956500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data      5019500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total      5019500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     11975500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     11975500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     11975500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     11975500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1165                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1165                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data     11976000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     11976000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     11976000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     11976000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1162                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1162                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2078                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2078                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2078                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2078                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098712                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098712                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2075                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2075                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2075                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2075                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098967                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098967                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.073384                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.087584                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.087584                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.087584                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.087584                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.087711                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.087711                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.087711                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.087711                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65799.450549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65799.450549                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65802.197802                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65802.197802                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6353000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6353000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6353500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6353500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3198000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      3198000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9551000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9551000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9551000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9551000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088412                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088412                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9551500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9551500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9551500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9551500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088640                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088640                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070260                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.070260                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070260                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.070260                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070361                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.070361                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070361                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.070361                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.765243                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1909                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           161.800750                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1920                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               322                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.928571                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.962733                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.765243                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078987                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078987                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.800750                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.079004                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.079004                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4784                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4784                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1909                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1909                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1909                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1909                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1909                       # number of overall hits
-system.cpu.icache.overall_hits::total            1909                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              4806                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4806                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1920                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1920                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1920                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1920                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1920                       # number of overall hits
+system.cpu.icache.overall_hits::total            1920                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          322                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           322                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          322                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            322                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          322                       # number of overall misses
 system.cpu.icache.overall_misses::total           322                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23594000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23594000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23594000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23594000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23594000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23594000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2231                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2231                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2231                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2231                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2231                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2231                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.144330                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.144330                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.144330                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.144330                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.144330                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.144330                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73273.291925                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73273.291925                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     23597500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     23597500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     23597500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     23597500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     23597500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     23597500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2242                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2242                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2242                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2242                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2242                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2242                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143622                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.143622                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.143622                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.143622                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.143622                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.143622                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73284.161491                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73284.161491                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -573,36 +573,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          322
 system.cpu.icache.demand_mshr_misses::total          322                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          322                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          322                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23272000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23272000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23272000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23272000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23272000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23272000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.144330                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.144330                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.144330                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.144330                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23275500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23275500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23275500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143622                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143622                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143622                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.143622                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143622                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.143622                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          195.411120                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          195.452372                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 41                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.108466                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.281002                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    41.130118                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004708                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.314702                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    41.137670                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004709                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001255                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005963                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005965                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          253                       # Occupied blocks per task id
@@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data          124                       #
 system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3133500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      3133500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22610500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     22610500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5960500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5960500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22610500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9094000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31704500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22610500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9094000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31704500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22614000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     22614000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5961000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5961000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22614000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9094500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31708500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22614000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9094500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31708500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          322                       # number of ReadCleanReq accesses(hits+misses)
@@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315
 system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73586.419753                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74132.786885                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73338.709677                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73903.263403                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74132.786885                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73338.709677                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73903.263403                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data          116
 system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2703500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2703500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19560500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19560500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4700500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4700500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19560500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7404000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26964500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19560500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7404000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26964500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19564000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19564000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4701000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4701000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19564000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7404500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26968500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19564000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7404500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26968500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadCleanReq accesses
@@ -731,16 +731,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict            2                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index e4986f157..800acea54 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,14 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 14:33:28
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 14 2015 23:30:05
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.checker.isa: ISA system set to: 0 0x38f90a0
-      0: system.cpu.isa: ISA system set to: 0 0x38f90a0
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 17307500 because target called exit()
+Exiting @ tick 17163000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 80e232875..be50d79db 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    17226500                       # Number of ticks simulated
-final_tick                                   17226500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    17163000                       # Number of ticks simulated
+final_tick                                   17163000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55427                       # Simulator instruction rate (inst/s)
-host_op_rate                                    64904                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              207866253                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311436                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  25428                       # Simulator instruction rate (inst/s)
+host_op_rate                                    29777                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               95019968                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305352                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17600                       # Nu
 system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                121                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   396                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1021681711                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            449539953                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1471221664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1021681711                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1021681711                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1021681711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           449539953                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1471221664                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1025461749                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            451203170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1476664919                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1025461749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1025461749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1025461749                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           451203170                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1476664919                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           396                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         396                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        17159000                       # Total gap between requests
+system.physmem.totGap                        17090000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       207                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       206                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      395.354839                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     263.720067                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     338.958245                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             11     17.74%     17.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     30.65%     48.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            6      9.68%     58.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8     12.90%     70.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      4.84%     75.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      3.23%     79.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      3.23%     82.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      3.23%     85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
-system.physmem.totQLat                        3039250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10464250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      389.079365                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     252.523009                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     343.171701                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             13     20.63%     20.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           18     28.57%     49.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6      9.52%     58.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8     12.70%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.76%     76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.17%     79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      3.17%     82.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      3.17%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     14.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
+system.physmem.totQLat                        3055250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10480250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1980000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7674.87                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7715.28                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26424.87                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1471.22                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26465.28                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1476.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1471.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1476.66                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.49                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.49                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.54                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.54                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.85                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        331                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        330                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.59                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.33                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43330.81                       # Average gap between requests
-system.physmem.pageHitRate                      83.59                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     302400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     165000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2090400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        43156.57                       # Average gap between requests
+system.physmem.pageHitRate                      83.33                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     309960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     169125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2106000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10797795                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy               10794375                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 14404965                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              909.404356                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE          69250                       # Time in different power states
+system.physmem_0.totalEnergy                 14428830                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              911.198611                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          65750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        16109250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        16176750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     151200                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      82500                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                    748800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10359180                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 412500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 12771300                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              806.650876                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         820250                       # Time in different power states
+system.physmem_1.actBackEnergy               10407915                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 369750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 12777285                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              807.028896                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         665250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14680750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14752750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2576                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1602                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               469                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2087                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     781                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2533                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1576                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               452                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2102                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     812                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             37.422137                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     336                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             38.629876                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     321                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 70                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -496,237 +496,237 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                            34454                       # number of cpu cycles simulated
+system.cpu.numCycles                            34327                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7709                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12205                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2576                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1117                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4748                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     987                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               7647                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          11725                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2533                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1133                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4667                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     953                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           251                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           17                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      2016                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   303                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13219                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.088585                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.463952                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1968                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   290                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13059                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.059729                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.422792                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10589     80.10%     80.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      274      2.07%     82.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      212      1.60%     83.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      221      1.67%     85.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      236      1.79%     87.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      324      2.45%     89.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      139      1.05%     90.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      161      1.22%     91.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1063      8.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10498     80.39%     80.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      262      2.01%     82.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      215      1.65%     84.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      219      1.68%     85.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      263      2.01%     87.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      312      2.39%     90.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      142      1.09%     91.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      158      1.21%     92.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      990      7.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13219                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.074766                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.354240                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6369                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  4276                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2102                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   134                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    338                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  384                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                13059                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.073790                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.341568                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6338                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  4216                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2063                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   121                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    321                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  380                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11852                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   468                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    338                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6584                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     692                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2356                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2013                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1236                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11200                       # Number of instructions processed by rename
+system.cpu.decode.DecodedInsts                  11316                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   476                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    321                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6551                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     647                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           2328                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      1964                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1248                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  10673                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                    168                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                    130                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1064                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               11331                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 51672                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            12441                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
+system.cpu.rename.SQFullEvents                   1076                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               10857                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 48954                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            11788                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                74                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     5837                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 43                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                     5363                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 42                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       422                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2287                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1689                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                38                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               34                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10125                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                       428                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2126                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1537                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                32                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               28                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                       9711                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8202                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                55                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4793                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        12371                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      7972                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                45                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4379                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        10941                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              9                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13219                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.620471                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.365465                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13059                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.610460                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.342240                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10002     75.66%     75.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1166      8.82%     84.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 755      5.71%     90.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 451      3.41%     93.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 357      2.70%     96.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 278      2.10%     98.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 131      0.99%     99.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  63      0.48%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  16      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9876     75.63%     75.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1174      8.99%     84.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 762      5.84%     90.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 454      3.48%     93.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 326      2.50%     96.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 278      2.13%     98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 116      0.89%     99.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  62      0.47%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  11      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13219                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13059                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       9      5.26%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     84     49.12%     54.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    78     45.61%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      5.92%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     67     44.08%     50.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    76     50.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4937     60.19%     60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    6      0.07%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1959     23.88%     84.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1297     15.81%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4885     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    7      0.09%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1831     22.97%     84.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1246     15.63%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8202                       # Type of FU issued
-system.cpu.iq.rate                           0.238057                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         171                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.020849                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29750                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14855                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7430                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  99                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                128                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total                   7972                       # Type of FU issued
+system.cpu.iq.rate                           0.232237                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         152                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019067                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              29107                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14039                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7309                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  93                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                116                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           32                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8330                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8081                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      43                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               24                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               23                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1260                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1099                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          751                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          599                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           32                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads           34                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             4                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    338                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     660                       # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles                    321                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     613                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    15                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10180                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               127                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2287                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1689                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts                9766                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               119                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2126                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1537                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     10                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            111                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          234                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  345                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7868                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1843                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               334                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            112                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          215                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  327                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7697                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1736                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               275                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             9                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3072                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1434                       # Number of branches executed
-system.cpu.iew.exec_stores                       1229                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.228362                       # Inst execution rate
-system.cpu.iew.wb_sent                           7574                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7462                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3524                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6897                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         2930                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1433                       # Number of branches executed
+system.cpu.iew.exec_stores                       1194                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.224226                       # Inst execution rate
+system.cpu.iew.wb_sent                           7432                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7341                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3456                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6757                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.216579                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.510947                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.213855                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.511470                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4801                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4387                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               314                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12382                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.434340                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.281233                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               297                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12286                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.437734                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.284067                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10327     83.40%     83.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          891      7.20%     90.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          421      3.40%     94.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          214      1.73%     95.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          114      0.92%     96.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          212      1.71%     98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           49      0.40%     98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           39      0.31%     99.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          115      0.93%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10235     83.31%     83.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          882      7.18%     90.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          420      3.42%     93.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          222      1.81%     95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          111      0.90%     96.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          213      1.73%     98.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           51      0.42%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.33%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          111      0.90%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12382                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12286                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4592                       # Number of instructions committed
 system.cpu.commit.committedOps                   5378                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5378                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   115                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22289                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21210                       # The number of ROB writes
-system.cpu.timesIdled                             194                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           21235                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   111                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        21783                       # The number of ROB reads
+system.cpu.rob.rob_writes                       20313                       # The number of ROB writes
+system.cpu.timesIdled                             192                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           21268                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4592                       # Number of Instructions Simulated
 system.cpu.committedOps                          5378                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.503049                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.503049                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.133279                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.133279                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     7752                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    4259                       # number of integer regfile writes
+system.cpu.cpi                               7.475392                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.475392                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.133772                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.133772                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     7631                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4176                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        32                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                     28119                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     3280                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    3175                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                     27375                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     3204                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    3054                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.080084                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2156                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.767123                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            87.851603                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2054                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.972789                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.080084                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021260                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021260                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.851603                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021448                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021448                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5466                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5466                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1537                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1537                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          597                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            597                       # number of WriteReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5255                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5255                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1436                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1436                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          596                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            596                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2134                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2134                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2134                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2134                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          186                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           186                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          316                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          316                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data          2032                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2032                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2032                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2032                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          181                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           181                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          317                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          317                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          502                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            502                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          502                       # number of overall misses
-system.cpu.dcache.overall_misses::total           502                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10668000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10668000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22567500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22567500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data          498                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            498                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          498                       # number of overall misses
+system.cpu.dcache.overall_misses::total           498                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10572000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10572000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22577500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22577500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       142000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       142000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33235500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33235500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33235500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33235500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1723                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1723                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data     33149500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33149500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33149500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33149500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1617                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1617                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2636                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2636                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2636                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2636                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.107951                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.107951                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.346112                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.346112                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2530                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2530                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2530                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2530                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.111936                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.111936                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.347207                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.347207                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.190440                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.190440                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.190440                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.190440                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57354.838710                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 57354.838710                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71416.139241                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71416.139241                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.196838                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.196838                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.196838                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.196838                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66206.175299                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66206.175299                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66206.175299                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66206.175299                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          126                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66565.261044                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66565.261044                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          145                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           63                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.333333                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           81                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          274                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          274                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           76                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          275                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          275                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          355                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          355                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          355                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          355                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          351                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          351                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          351                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          351                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          105                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
@@ -895,135 +895,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6685000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6685000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3406500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3406500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10091500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10091500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10091500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10091500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.060940                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.060940                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6969000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6969000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3397000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3397000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10366000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10366000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10366000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10366000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.064935                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.064935                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055766                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.055766                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055766                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.055766                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63666.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63666.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81107.142857                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81107.142857                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68649.659864                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68649.659864                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68649.659864                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68649.659864                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058103                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.058103                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058103                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.058103                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           149.175552                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1623                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           149.741808                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1582                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               293                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              5.539249                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.399317                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   149.175552                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072840                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072840                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   149.741808                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073116                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073116                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          292                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.142578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4325                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4325                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1623                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1623                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1623                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1623                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1623                       # number of overall hits
-system.cpu.icache.overall_hits::total            1623                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          393                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           393                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          393                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            393                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          393                       # number of overall misses
-system.cpu.icache.overall_misses::total           393                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     27030000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     27030000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     27030000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     27030000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     27030000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     27030000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2016                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2016                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2016                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2016                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2016                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2016                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.194940                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.194940                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.194940                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.194940                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.194940                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.194940                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68778.625954                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68778.625954                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68778.625954                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68778.625954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68778.625954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68778.625954                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          456                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              4229                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4229                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1582                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1582                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1582                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1582                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1582                       # number of overall hits
+system.cpu.icache.overall_hits::total            1582                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          386                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           386                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          386                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            386                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          386                       # number of overall misses
+system.cpu.icache.overall_misses::total           386                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     26869500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     26869500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     26869500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     26869500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     26869500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     26869500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1968                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1968                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1968                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1968                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1968                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1968                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.196138                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.196138                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.196138                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.196138                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.196138                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.196138                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69610.103627                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69610.103627                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          432                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    91.200000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    86.400000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          100                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          100                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          100                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          100                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          100                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          100                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           93                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           93                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           93                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           93                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           93                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           93                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          293                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          293                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          293                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          293                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          293                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          293                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21572000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21572000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21572000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21572000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21572000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21572000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.145337                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.145337                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.145337                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.145337                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.145337                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.145337                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73624.573379                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73624.573379                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73624.573379                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73624.573379                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73624.573379                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73624.573379                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21385500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     21385500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21385500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     21385500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21385500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     21385500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148882                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148882                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148882                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.148882                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148882                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.148882                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          186.076752                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          187.228350                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              354                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.110169                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.018845                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    46.057907                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004273                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001406                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005679                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.551776                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    46.676574                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004289                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001424                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005714                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010803                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3916                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3916                       # Number of data accesses
@@ -1049,18 +1049,18 @@ system.cpu.l2cache.demand_misses::total           401                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          275                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          126                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          401                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3342500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3342500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     20942500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     20942500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6371000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      6371000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20942500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9713500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     30656000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20942500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9713500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     30656000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3333000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3333000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     20756000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     20756000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6584500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      6584500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20756000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9917500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     30673500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20756000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9917500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     30673500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           42                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           42                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          293                       # number of ReadCleanReq accesses(hits+misses)
@@ -1085,18 +1085,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.911364                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.938567                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.857143                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.911364                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79583.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79583.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76154.545455                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76154.545455                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75845.238095                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75845.238095                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76154.545455                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77091.269841                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76448.877805                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76154.545455                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77091.269841                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76448.877805                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1123,18 +1123,18 @@ system.cpu.l2cache.demand_mshr_misses::total          396
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          121                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          396                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2922500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2922500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     18192500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     18192500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5250500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5250500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18192500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8173000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26365500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18192500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8173000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26365500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2913000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2913000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     18006000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     18006000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5464000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5464000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18006000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8377000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26383000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18006000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8377000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26383000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.938567                       # mshr miss rate for ReadCleanReq accesses
@@ -1147,30 +1147,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.900000
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.938567                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.823129                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.900000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69583.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69583.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66154.545455                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66154.545455                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66462.025316                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66462.025316                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66154.545455                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67545.454545                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66579.545455                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66154.545455                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67545.454545                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66579.545455                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp           397                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          293                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          105                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          586                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               879                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          294                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               880                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              28160                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples          441                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
@@ -1187,7 +1187,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        439500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        221495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        222995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                354                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
@@ -1210,7 +1210,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 396                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              485500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2095750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2097000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 5213b7cc0..d3878acf4 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    22403000                       # Number of ticks simulated
-final_tick                                   22403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    22451000                       # Number of ticks simulated
+final_tick                                   22451000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79030                       # Simulator instruction rate (inst/s)
-host_op_rate                                    79012                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              354943993                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292784                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  41665                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41658                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              187549895                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 287968                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        4986                       # Number of instructions simulated
 sim_ops                                          4986                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             21120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             20992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21120                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                330                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                30016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        20992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           20992                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                328                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   471                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            942730884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            402803196                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1345534080                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       942730884                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          942730884                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           942730884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           402803196                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1345534080                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           471                       # Number of read requests accepted
+system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            935014031                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            401942007                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1336956038                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       935014031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          935014031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           935014031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           401942007                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1336956038                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           469                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         471                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         469                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    30144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    30016                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     30144                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     30016                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::10                 43                       # Pe
 system.physmem.perBankRdBursts::11                 20                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 51                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 29                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 80                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 78                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        22316000                       # Total gap between requests
+system.physmem.totGap                        22364000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     471                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     469                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       277                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       273                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        37                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        41                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          105                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      260.876190                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.828028                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     254.099908                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             30     28.57%     28.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           33     31.43%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           19     18.10%     78.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           10      9.52%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            3      2.86%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            2      1.90%     92.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      0.95%     93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      0.95%     94.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            6      5.71%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            105                       # Bytes accessed per row activation
-system.physmem.totQLat                        4348750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13180000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2355000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9233.01                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          104                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      262.153846                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.926322                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     251.694944                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             29     27.88%     27.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           32     30.77%     58.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           20     19.23%     77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            9      8.65%     86.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      3.85%     90.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      1.92%     92.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      0.96%     93.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      0.96%     94.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6      5.77%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            104                       # Bytes accessed per row activation
+system.physmem.totQLat                        4505500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13299250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9606.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27983.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1345.53                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28356.61                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1336.96                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1345.53                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1336.96                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.51                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.51                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.44                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.44                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.71                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        356                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        355                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.58                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   75.69                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        47380.04                       # Average gap between requests
-system.physmem.pageHitRate                      75.58                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        47684.43                       # Average gap between requests
+system.physmem.pageHitRate                      75.69                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    538200                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                    530400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy                9525555                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                1143750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 12423270                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              784.668877                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE        2113750                       # Time in different power states
+system.physmem_0.actBackEnergy                9542655                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                1130250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 12419070                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              784.279760                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE        1840500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        13462250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        13487750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     521640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     284625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2191800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     514080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     280500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2168400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10738800                       # Energy for active background per rank (pJ)
+system.physmem_1.actBackEnergy               10730250                       # Energy for active background per rank (pJ)
 system.physmem_1.preBackEnergy                  87000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 14840985                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              936.635216                       # Core power per rank (mW)
+system.physmem_1.totalEnergy                 14797350                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              934.618664                       # Core power per rank (mW)
 system.physmem_1.memoryStateTime::IDLE         103500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        15234500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        15222750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2126                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1379                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               429                       # Number of conditional branches incorrect
+system.cpu.branchPred.lookups                    2031                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1362                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               402                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups                 1641                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     514                       # Number of BTB hits
+system.cpu.branchPred.BTBHits                     605                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             31.322364                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     281                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 67                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             36.867764                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     242                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 66                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -279,236 +279,236 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.numCycles                            44807                       # number of cpu cycles simulated
+system.cpu.numCycles                            44903                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8961                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12993                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2126                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                795                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4908                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     876                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.PendingTrapStallCycles           194                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2040                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   269                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.896007                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.195594                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               8843                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12328                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2031                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                847                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4817                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     822                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.PendingTrapStallCycles           190                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      1979                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   255                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14261                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.864456                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.133927                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11177     77.08%     77.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1470     10.14%     87.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      121      0.83%     88.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      160      1.10%     89.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      283      1.95%     91.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       95      0.66%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      127      0.88%     92.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      112      0.77%     93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      956      6.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10999     77.13%     77.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1480     10.38%     87.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      118      0.83%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      169      1.19%     89.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      282      1.98%     91.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      102      0.72%     92.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      134      0.94%     93.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      153      1.07%     94.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      824      5.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.047448                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.289977                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8511                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  2687                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2777                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   129                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    397                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  172                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    43                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12008                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   170                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    397                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8669                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     506                       # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total                14261                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.045231                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.274547                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8380                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2677                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2707                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   126                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    371                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  167                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    41                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  11351                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   162                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    371                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8518                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     542                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            996                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2735                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1198                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11509                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      2675                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1159                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  10918                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    229                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    179                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                    954                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                6966                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13566                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13315                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                6512                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 12905                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            12683                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 3                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  3282                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3684                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3230                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 14                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       296                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2503                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1169                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       314                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2295                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1159                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       9007                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       8632                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8237                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                38                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4031                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1845                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      7937                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                20                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3656                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1608                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.568030                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.308332                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14261                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.556553                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.276985                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11165     76.99%     76.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1330      9.17%     86.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 739      5.10%     91.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 423      2.92%     94.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 353      2.43%     96.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 304      2.10%     98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 105      0.72%     99.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  58      0.40%     99.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  24      0.17%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10981     77.00%     77.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1321      9.26%     86.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 733      5.14%     91.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 439      3.08%     94.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 350      2.45%     96.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 277      1.94%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  91      0.64%     99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  50      0.35%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  19      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14261                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       7      3.57%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    131     66.84%     70.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    58     29.59%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6      3.41%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    112     63.64%     67.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    58     32.95%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4840     58.76%     58.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2319     28.15%     87.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1071     13.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4719     59.46%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.05%     59.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     59.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.03%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2143     27.00%     86.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1068     13.46%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8237                       # Type of FU issued
-system.cpu.iq.rate                           0.183833                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         196                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023795                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31205                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             13056                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7426                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   7937                       # Type of FU issued
+system.cpu.iq.rate                           0.176759                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         176                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.022175                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30327                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             12306                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7277                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8431                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8111                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               83                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               89                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1371                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1163                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          268                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          258                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            23                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            22                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    397                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     472                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     7                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10561                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               155                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2503                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1169                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    371                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     425                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    88                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10126                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               130                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2295                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1159                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 11                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     9                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    89                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             98                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          354                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  452                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7898                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2175                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               339                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          321                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  419                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7671                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2045                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               266                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1543                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3228                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1368                       # Number of branches executed
+system.cpu.iew.exec_nop                          1483                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3098                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1353                       # Number of branches executed
 system.cpu.iew.exec_stores                       1053                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.176267                       # Inst execution rate
-system.cpu.iew.wb_sent                           7529                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7428                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2859                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4251                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.170835                       # Inst execution rate
+system.cpu.iew.wb_sent                           7354                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7279                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2832                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      4198                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.165778                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.672548                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.162105                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.674607                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4937                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4505                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               9                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               388                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13632                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.412485                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.223639                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               362                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13468                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.417508                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.246465                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11448     83.98%     83.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          886      6.50%     90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          511      3.75%     94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          255      1.87%     96.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          161      1.18%     97.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          164      1.20%     98.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           65      0.48%     98.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           40      0.29%     99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          102      0.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11324     84.08%     84.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          857      6.36%     90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          503      3.73%     94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          247      1.83%     96.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          153      1.14%     97.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          168      1.25%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           61      0.45%     98.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           39      0.29%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          116      0.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13632                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13468                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5623                       # Number of instructions committed
 system.cpu.commit.committedOps                   5623                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -554,101 +554,101 @@ system.cpu.commit.op_class_0::MemWrite            901     16.02%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5623                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        24077                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22001                       # The number of ROB writes
-system.cpu.timesIdled                             266                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           30306                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   116                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        23467                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21056                       # The number of ROB writes
+system.cpu.timesIdled                             265                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           30642                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4986                       # Number of Instructions Simulated
 system.cpu.committedOps                          4986                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               8.986562                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         8.986562                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.111277                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.111277                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10682                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5223                       # number of integer regfile writes
+system.cpu.cpi                               9.005816                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         9.005816                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.111039                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.111039                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10418                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5064                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                     167                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                     158                       # number of misc regfile reads
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            91.242537                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2427                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            90.670819                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2302                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             17.212766                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.326241                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    91.242537                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022276                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022276                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    90.670819                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022136                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022136                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              6025                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             6025                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1871                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1871                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              5765                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5765                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1746                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1746                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          556                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            556                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2427                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2427                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2427                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2427                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          170                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           170                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2302                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2302                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2302                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2302                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          165                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           165                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          345                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          345                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          515                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            515                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          515                       # number of overall misses
-system.cpu.dcache.overall_misses::total           515                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11738500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11738500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24073999                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24073999                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     35812499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     35812499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     35812499                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     35812499                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2041                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2041                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          510                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            510                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          510                       # number of overall misses
+system.cpu.dcache.overall_misses::total           510                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11734000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11734000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     24014999                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     24014999                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     35748999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     35748999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     35748999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     35748999                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1911                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1911                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2942                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2942                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2942                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2942                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083293                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.083293                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2812                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2812                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2812                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2812                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086342                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.086342                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.382908                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.382908                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.175051                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.175051                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.175051                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.175051                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        69050                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        69050                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69779.707246                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69779.707246                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69538.833010                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69538.833010                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69538.833010                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69538.833010                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          615                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.181366                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.181366                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.181366                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.181366                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70096.076471                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70096.076471                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          587                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                10                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    55.909091                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    58.700000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           79                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           74                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          295                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          295                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          369                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          369                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          369                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          369                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
@@ -657,82 +657,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          141
 system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7586500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7586500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4094999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4094999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11681499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11681499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11681499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11681499                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044586                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044586                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7594500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7594500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4083499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4083499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11677999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11677999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11677999                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11677999                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.047619                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.047619                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.047927                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.047927                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.047927                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.047927                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83368.131868                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83368.131868                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81899.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81899.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82847.510638                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 82847.510638                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82847.510638                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 82847.510638                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.050142                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.050142                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.050142                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.050142                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           158.208729                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1588                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               333                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              4.768769                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           156.398029                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1547                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               331                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              4.673716                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   158.208729                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077250                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          316                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.154297                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4413                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4413                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1588                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1588                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1588                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1588                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1588                       # number of overall hits
-system.cpu.icache.overall_hits::total            1588                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          452                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           452                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          452                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            452                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          452                       # number of overall misses
-system.cpu.icache.overall_misses::total           452                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     33055000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     33055000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     33055000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     33055000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     33055000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     33055000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2040                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2040                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2040                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2040                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2040                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2040                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.221569                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.221569                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.221569                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.221569                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.221569                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.221569                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73130.530973                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73130.530973                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73130.530973                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73130.530973                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73130.530973                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73130.530973                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst   156.398029                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.076366                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.076366                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4289                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4289                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1547                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1547                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1547                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1547                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1547                       # number of overall hits
+system.cpu.icache.overall_hits::total            1547                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          432                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           432                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          432                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            432                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          432                       # number of overall misses
+system.cpu.icache.overall_misses::total           432                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32419500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32419500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32419500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32419500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32419500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32419500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1979                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1979                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1979                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1979                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1979                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1979                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.218292                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.218292                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.218292                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.218292                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.218292                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.218292                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75045.138889                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75045.138889                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -741,54 +741,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          119                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          119                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          119                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          119                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          119                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          119                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          333                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          333                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          333                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          333                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          333                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          333                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25884000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25884000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25884000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25884000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25884000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25884000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.163235                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.163235                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.163235                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.163235                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.163235                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.163235                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77729.729730                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77729.729730                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77729.729730                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77729.729730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77729.729730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77729.729730                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          101                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          101                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          101                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          101                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          101                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          101                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          331                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          331                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          331                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          331                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          331                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          331                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25901500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25901500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25901500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25901500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25901500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25901500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.167256                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.167256                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.167256                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.167256                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.167256                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.167256                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          218.239575                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          215.838012                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 20                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              421                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.047506                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              419                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.047733                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.142310                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    58.097265                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004887                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001773                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006660                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   158.321641                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.516370                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004832                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001755                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006587                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          419                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012848                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4399                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4399                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012787                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4381                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4381                       # Number of data accesses
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            3                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
@@ -797,64 +797,64 @@ system.cpu.l2cache.overall_hits::cpu.inst            3                       # n
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          330                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          330                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          328                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          328                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data           91                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total           91                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          330                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          328                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           471                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          330                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           469                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          328                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          141                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          471                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4019000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4019000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25353000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     25353000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7446500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      7446500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25353000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11465500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     36818500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25353000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11465500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     36818500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4007500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4007500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25373500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25373500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7455000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7455000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25373500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     11462500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     36836000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25373500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11462500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36836000                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          333                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          333                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          331                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          331                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           91                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total           91                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          333                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          331                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          474                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          333                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          472                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          331                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          474                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          472                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.990991                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.990991                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.990937                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.990937                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.990991                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.990937                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.993671                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990991                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.993644                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990937                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.993671                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        80380                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        80380                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76827.272727                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76827.272727                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81829.670330                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81829.670330                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.272727                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81315.602837                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78170.912951                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.272727                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81315.602837                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78170.912951                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.993644                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        80150                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        80150                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -865,105 +865,105 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          330                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          330                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          328                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          328                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           91                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total           91                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          330                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          328                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          471                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          330                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          469                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          328                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          471                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3519000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3519000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22053000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22053000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6536500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6536500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10055500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     32108500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22053000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10055500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     32108500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3507500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3507500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22093500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22093500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6545000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6545000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10052500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     32146000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22093500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10052500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     32146000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.990991                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.990937                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.990937                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.990937                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.993671                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.990991                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.993644                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.990937                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.993671                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        70380                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        70380                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66827.272727                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66827.272727                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71829.670330                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71829.670330                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66827.272727                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71315.602837                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68170.912951                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66827.272727                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71315.602837                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68170.912951                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.993644                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        70150                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        70150                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           422                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          333                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          331                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq           91                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          683                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          679                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               965                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               961                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21184                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              30336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30208                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          491                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          489                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                491    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                489    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            491                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         245500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            489                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         244500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        499500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        496500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                421                       # Transaction distribution
+system.membus.trans_dist::ReadResp                419                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           421                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   30144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq           419                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          938                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    938                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   30016                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               471                       # Request fanout histogram
+system.membus.snoop_fanout::samples               469                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     471    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     469    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 471                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              582000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 469                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              580000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2503500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2493500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 4915dc4bb..ff8cb9e3e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -230,7 +230,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 8f334ebb7..585054648 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    19998000                       # Number of ticks simulated
-final_tick                                   19998000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    19922000                       # Number of ticks simulated
+final_tick                                   19922000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99740                       # Simulator instruction rate (inst/s)
-host_op_rate                                    99716                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              344211505                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290580                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  38523                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38518                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              132470471                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 286104                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21952                       # Nu
 system.physmem.num_reads::cpu.inst                343                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   444                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1097709771                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            323232323                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1420942094                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1097709771                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1097709771                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1097709771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           323232323                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1420942094                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1101897400                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            324465415                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1426362815                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1101897400                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1101897400                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1101897400                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           324465415                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1426362815                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           444                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         444                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        19858500                       # Total gap between requests
+system.physmem.totGap                        19782500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       242                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       243                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       141                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        43                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           78                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      332.307692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.430832                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     340.544877                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             29     37.18%     37.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           17     21.79%     58.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            7      8.97%     67.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            4      5.13%     73.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      5.13%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            3      3.85%     82.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.56%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            3      3.85%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            9     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             78                       # Bytes accessed per row activation
-system.physmem.totQLat                        3950250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12275250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           76                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      340.210526                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     203.437950                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     338.690117                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             26     34.21%     34.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           17     22.37%     56.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     10.53%     67.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      5.26%     72.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      5.26%     77.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            4      5.26%     82.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      1.32%     84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      3.95%     88.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     11.84%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             76                       # Bytes accessed per row activation
+system.physmem.totQLat                        3750750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12075750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8896.96                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        8447.64                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27646.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1420.94                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27197.64                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1426.36                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1420.94                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1426.36                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.10                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.10                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.14                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.79                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        357                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        359                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.41                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.86                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        44726.35                       # Average gap between requests
-system.physmem.pageHitRate                      80.41                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     461160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     251625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2519400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        44555.18                       # Average gap between requests
+system.physmem.pageHitRate                      80.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     438480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     239250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2511600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               10796085                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 15077640                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              952.021468                       # Core power per rank (mW)
+system.physmem_0.actBackEnergy               10783260                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  40500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 15030210                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              949.326386                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          11500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        15318750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15314750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                    288600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy                7492365                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                2927250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 11830500                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              747.228802                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        6597250                       # Time in different power states
+system.physmem_1.actBackEnergy                7628310                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                2808000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 11847195                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              748.283278                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        6322250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        10517250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        10715250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    2331                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1883                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               415                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1931                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     661                       # Number of BTB hits
+system.cpu.branchPred.lookups                    2359                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1936                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               404                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1982                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     725                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             34.230968                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     218                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 31                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             36.579213                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     224                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 32                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -279,237 +279,237 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            39997                       # number of cpu cycles simulated
+system.cpu.numCycles                            39845                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7837                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13501                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2331                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                879                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4391                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     863                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               7679                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13188                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2359                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                949                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3750                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     839                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           153                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles           147                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      1828                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   299                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              12836                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.051807                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.461524                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1822                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   291                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              12019                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.097263                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.493815                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10473     81.59%     81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      190      1.48%     83.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      215      1.67%     84.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      153      1.19%     85.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      248      1.93%     87.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      135      1.05%     88.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      253      1.97%     90.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      115      0.90%     91.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1054      8.21%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9698     80.69%     80.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      176      1.46%     82.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      221      1.84%     83.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      153      1.27%     85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      238      1.98%     87.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      147      1.22%     88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      274      2.28%     90.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      116      0.97%     91.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      996      8.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                12836                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.058279                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.337550                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7233                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3240                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      1952                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   129                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    282                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  335                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   150                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11562                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   472                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    282                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7391                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     953                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            624                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1916                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1670                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11195                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total                12019                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.059204                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.330983                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7188                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2504                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      1924                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   132                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    271                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  317                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   149                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  11315                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   469                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    271                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7350                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     927                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            518                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      1884                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1069                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  10932                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                     25                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   1610                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands                9626                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18124                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18098                       # Number of integer rename lookups
+system.cpu.rename.LQFullEvents                      2                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   1028                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands                9574                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17720                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17694                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                26                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     4628                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     4576                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       362                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2015                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1832                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                52                       # Number of conflicting loads.
+system.cpu.memDep0.insertedLoads                 1935                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1629                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                53                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               29                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10320                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      10141                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  63                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9101                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                75                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4591                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqInstsIssued                      8840                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                52                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4412                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined         3358                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         12836                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.709022                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.537942                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         12019                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.735502                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.540494                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9696     75.54%     75.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 959      7.47%     83.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 638      4.97%     87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 461      3.59%     91.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 440      3.43%     95.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 291      2.27%     97.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 236      1.84%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  68      0.53%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  47      0.37%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8914     74.17%     74.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 959      7.98%     82.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 649      5.40%     87.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 465      3.87%     91.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 426      3.54%     94.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 281      2.34%     97.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 228      1.90%     99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  65      0.54%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  32      0.27%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           12836                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12019                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      11      4.38%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    121     48.21%     52.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   119     47.41%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      13      6.47%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     95     47.26%     53.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    93     46.27%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5531     60.77%     60.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     60.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1910     20.99%     81.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1658     18.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5519     62.43%     62.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1819     20.58%     83.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1500     16.97%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9101                       # Type of FU issued
-system.cpu.iq.rate                           0.227542                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         251                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.027579                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31302                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14945                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8267                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8840                       # Type of FU issued
+system.cpu.iq.rate                           0.221860                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         201                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.022738                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              29890                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14587                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8120                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9318                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9007                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               80                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1054                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          974                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          786                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          583                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             8                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked             7                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    282                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     869                       # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles                    271                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     843                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    77                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10383                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                18                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2015                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1832                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               10204                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                34                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  1935                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1629                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 54                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                    66                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          276                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  345                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8700                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1776                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               401                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             72                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          254                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  326                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8485                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1707                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               355                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3330                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1363                       # Number of branches executed
-system.cpu.iew.exec_stores                       1554                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.217516                       # Inst execution rate
-system.cpu.iew.wb_sent                           8425                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8294                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4459                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7044                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3121                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1355                       # Number of branches executed
+system.cpu.iew.exec_stores                       1414                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.212950                       # Inst execution rate
+system.cpu.iew.wb_sent                           8249                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8147                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4452                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7114                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.207366                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.633021                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.204467                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.625808                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4593                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4414                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               276                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12125                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.477691                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.335541                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               265                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        11324                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.511480                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.378975                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9949     82.05%     82.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          859      7.08%     89.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          524      4.32%     93.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          226      1.86%     95.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          182      1.50%     96.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          108      0.89%     97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          109      0.90%     98.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           59      0.49%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          109      0.90%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9160     80.89%     80.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          847      7.48%     88.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          528      4.66%     93.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          216      1.91%     94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          182      1.61%     96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          106      0.94%     97.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          122      1.08%     98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           53      0.47%     99.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          110      0.97%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12125                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11324                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -555,250 +555,250 @@ system.cpu.commit.op_class_0::MemWrite           1046     18.06%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   109                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        22401                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21482                       # The number of ROB writes
-system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           27161                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   110                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        21420                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21108                       # The number of ROB writes
+system.cpu.timesIdled                             228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           27826                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
 system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               6.905559                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.905559                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.144811                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.144811                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13740                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7170                       # number of integer regfile writes
+system.cpu.cpi                               6.879316                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.879316                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.145363                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.145363                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13451                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7138                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            63.810933                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2272                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             22.274510                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            64.587343                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2213                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               103                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             21.485437                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    63.810933                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.015579                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.015579                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.024902                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1553                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1553                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          719                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            719                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2272                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2272                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2272                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2272                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          114                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           114                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          327                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          327                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          441                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            441                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          441                       # number of overall misses
-system.cpu.dcache.overall_misses::total           441                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8777500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8777500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     32490996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     32490996                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     41268496                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     41268496                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     41268496                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     41268496                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1667                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1667                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data    64.587343                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.015768                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.015768                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          103                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.025146                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5395                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5395                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1492                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1492                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          721                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            721                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2213                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2213                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2213                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2213                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          108                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           108                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          325                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          325                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          433                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            433                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          433                       # number of overall misses
+system.cpu.dcache.overall_misses::total           433                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7902500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7902500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     23909996                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     23909996                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     31812496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     31812496                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     31812496                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     31812496                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1600                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1600                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1046                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2713                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2713                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2713                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2713                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068386                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.068386                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.312620                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.312620                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.162551                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.162551                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.162551                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.162551                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76995.614035                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76995.614035                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99360.844037                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 99360.844037                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 93579.356009                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 93579.356009                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 93579.356009                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 93579.356009                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          627                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2646                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2646                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2646                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2646                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.067500                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.067500                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.310707                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.310707                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.163643                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.163643                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.163643                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.163643                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73469.967667                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73469.967667                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          598                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   104.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    99.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           59                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          280                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          280                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          339                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          339                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          339                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          339                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           52                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           52                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          278                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          278                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          330                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          330                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          330                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          330                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           56                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           56                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           47                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          102                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          102                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          102                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          102                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4552000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4552000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4551498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4551498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9103498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9103498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9103498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9103498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032993                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032993                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          103                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          103                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          103                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          103                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4528500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4528500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4006498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4006498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8534998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8534998                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8534998                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8534998                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035000                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035000                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044933                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037597                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.037597                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037597                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.037597                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82763.636364                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82763.636364                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96840.382979                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96840.382979                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89249.980392                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 89249.980392                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89249.980392                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 89249.980392                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.038927                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.038927                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038927                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.038927                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           169.178952                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           168.966654                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1389                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               349                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              3.979943                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   169.178952                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082607                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082607                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   168.966654                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082503                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082503                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.170410                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4005                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4005                       # Number of data accesses
+system.cpu.icache.tags.tag_accesses              3993                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             3993                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1389                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1389                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1389                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total             1389                       # number of demand (read+write) hits
 system.cpu.icache.overall_hits::cpu.inst         1389                       # number of overall hits
 system.cpu.icache.overall_hits::total            1389                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          439                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           439                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          439                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            439                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          439                       # number of overall misses
-system.cpu.icache.overall_misses::total           439                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31700000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31700000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31700000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31700000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31700000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31700000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1828                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1828                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1828                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1828                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1828                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1828                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.240153                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.240153                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.240153                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.240153                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.240153                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.240153                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72209.567198                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72209.567198                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72209.567198                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72209.567198                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72209.567198                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72209.567198                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          485                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_misses::cpu.inst          433                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           433                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          433                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            433                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          433                       # number of overall misses
+system.cpu.icache.overall_misses::total           433                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32237500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32237500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32237500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32237500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32237500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32237500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1822                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1822                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1822                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1822                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1822                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1822                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.237651                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.237651                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.237651                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.237651                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.237651                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.237651                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 74451.501155                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 74451.501155                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          497                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           97                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    99.400000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           89                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           89                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           89                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           89                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           89                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           89                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           83                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           83                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           83                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           83                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           83                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          350                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          350                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          350                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          350                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          350                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26208500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26208500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26208500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26208500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.191466                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.191466                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.191466                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.191466                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.191466                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.191466                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74881.428571                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74881.428571                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74881.428571                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74881.428571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74881.428571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74881.428571                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26589500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26589500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     26589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26589500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     26589500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.192097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.192097                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.192097                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.192097                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.192097                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.192097                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        75970                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        75970                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        75970                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total        75970                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        75970                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total        75970                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.713481                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  7                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse          199.677803                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  8                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              397                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.017632                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.020151                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.994608                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.718873                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005127                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000968                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006095                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.770664                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.907139                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005120                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000974                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006094                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012115                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4060                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4060                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses             4068                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4068                       # Number of data accesses
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            6                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            6                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data            1                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total            1                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data            2                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total            2                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            6                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               7                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               8                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            6                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              7                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              8                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data           47                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           47                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          344                       # number of ReadCleanReq misses
@@ -811,54 +811,54 @@ system.cpu.l2cache.demand_misses::total           445                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          445                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4478000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4478000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25621500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     25621500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4458500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      4458500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25621500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      8936500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34558000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25621500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      8936500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34558000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3932500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3932500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     26002500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     26002500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4422500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      4422500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     26002500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      8355000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     34357500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     26002500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      8355000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     34357500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          350                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total          350                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           55                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           55                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           56                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           56                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          350                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          102                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          103                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          453                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          350                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          102                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          103                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          453                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.982857                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.982857                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.981818                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.981818                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.964286                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.964286                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.982857                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.990196                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.984513                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980583                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.982340                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982857                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.990196                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.984513                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980583                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.982340                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -879,71 +879,71 @@ system.cpu.l2cache.demand_mshr_misses::total          445
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          445                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4008000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4008000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22191500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22191500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3918500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3918500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22191500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7926500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30118000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22191500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7926500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30118000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3462500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3462500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22572500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22572500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3882500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3882500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7345000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     29917500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22572500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7345000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     29917500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.982857                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.981818                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.981818                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.964286                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.964286                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.984513                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980583                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.982340                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.984513                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980583                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.982340                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp           404                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           405                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           47                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          350                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           55                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           56                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          699                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          204                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               903                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          206                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               905                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         6528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         6592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              28928                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          452                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          453                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                452    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                453    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            452                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         226000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            453                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         226500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        523500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        153000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        154500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                397                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
@@ -964,9 +964,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 444                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              550500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              551000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2342500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             11.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2342750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index cf52ef870..d45cde2de 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -227,7 +227,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index ef02c087f..e476df038 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,58 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21012000                       # Number of ticks simulated
-final_tick                                   21012000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20817000                       # Number of ticks simulated
+final_tick                                   20817000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49067                       # Simulator instruction rate (inst/s)
-host_op_rate                                    88883                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              191585973                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310932                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  31285                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56673                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              121026192                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306568                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            837616600                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            429468875                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1267085475                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       837616600                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          837616600                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           837616600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           429468875                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1267085475                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           417                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8896                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26560                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                139                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   415                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            848537253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            427343037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1275880290                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       848537253                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          848537253                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           848537253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           427343037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1275880290                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           415                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         417                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         415                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    26688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    26560                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     26688                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     26560                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  34                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                   1                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                   6                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                   8                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  50                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  45                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  46                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  21                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  34                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  22                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  74                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  33                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  25                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  72                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 63                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 17                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 16                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                  2                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 17                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                  6                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20963500                       # Total gap between requests
+system.physmem.totGap                        20721000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     417                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     415                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       244                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       245                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,310 +186,310 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           99                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      239.838384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     160.844462                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     248.938264                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             34     34.34%     34.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           32     32.32%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           15     15.15%     81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            5      5.05%     86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            2      2.02%     88.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            4      4.04%     92.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      1.01%     93.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      2.02%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            4      4.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             99                       # Bytes accessed per row activation
-system.physmem.totQLat                        3956500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11775250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2085000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9488.01                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           96                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             252                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.484740                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     262.126687                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             35     36.46%     36.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           26     27.08%     63.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           15     15.62%     79.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            6      6.25%     85.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      3.12%     88.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      3.12%     91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.08%     93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.04%     94.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      5.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             96                       # Bytes accessed per row activation
+system.physmem.totQLat                        4745000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12526250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2075000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11433.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28238.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1270.13                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30183.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1275.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1270.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1275.88                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.92                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.92                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.97                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        308                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        309                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.86                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.46                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        50272.18                       # Average gap between requests
-system.physmem.pageHitRate                      73.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     189000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     103125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                    951600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        49930.12                       # Average gap between requests
+system.physmem.pageHitRate                      74.46                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     196560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     107250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    959400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
 system.physmem_0.actBackEnergy               10792665                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy                  32250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 13085760                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              826.512553                       # Core power per rank (mW)
+system.physmem_0.totalEnergy                 13105245                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              827.743250                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          11500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        15314750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     430920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     235125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   1521000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     423360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     231000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1536600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               10315575                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 450750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 13970490                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              882.393179                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         973750                       # Time in different power states
+system.physmem_1.actBackEnergy               10696905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 116250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 14021235                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              885.598295                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         271750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        14667250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        15224250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    3416                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3416                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               534                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2538                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     864                       # Number of BTB hits
+system.cpu.branchPred.lookups                    3234                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3234                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               514                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2557                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     881                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             34.042553                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     247                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 76                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             34.454439                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     280                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 86                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            42025                       # number of cpu cycles simulated
+system.cpu.numCycles                            41635                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              11194                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          15490                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3416                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1111                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9646                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1195                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles              11661                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14637                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3234                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1161                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          9674                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1159                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   51                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1127                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                      2165                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   282                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              22628                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.226003                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.725670                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           746                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.CacheLines                      2075                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   258                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              22725                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.149527                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.648759                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    18363     81.15%     81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      236      1.04%     82.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      174      0.77%     82.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      258      1.14%     84.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      208      0.92%     85.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      227      1.00%     86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      337      1.49%     87.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      205      0.91%     88.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2620     11.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    18699     82.28%     82.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      221      0.97%     83.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      146      0.64%     83.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      231      1.02%     84.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      214      0.94%     85.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      258      1.14%     86.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      336      1.48%     88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      205      0.90%     89.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2415     10.63%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                22628                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.081285                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.368590                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    10919                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  7328                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3329                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   455                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    597                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  25699                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                    597                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11189                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2276                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            782                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3470                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  4314                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  24173                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     93                       # Number of times rename has blocked due to IQ full
+system.cpu.fetch.rateDist::total                22725                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.077675                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.351555                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    11462                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  7072                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3206                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   406                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    579                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  24310                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                    579                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    11710                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    1815                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1004                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3327                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  4290                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  23005                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     71                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.SQFullEvents                   4163                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               27542                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 59265                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            33505                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               26169                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 57126                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            32219                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    16479                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 29                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             29                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1507                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2438                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1611                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                22                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    15106                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 28                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             28                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      1472                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2371                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1574                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                20                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21416                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17876                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                80                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           11694                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        16519                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         22628                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.789995                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.748596                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      20445                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  26                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     17161                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                65                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           10724                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        15317                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         22725                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.755160                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.702113                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               17504     77.36%     77.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1142      5.05%     82.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 891      3.94%     86.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 637      2.82%     89.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 831      3.67%     92.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 584      2.58%     95.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 600      2.65%     98.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 315      1.39%     99.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                 124      0.55%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               17737     78.05%     78.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1126      4.95%     83.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 880      3.87%     86.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 631      2.78%     89.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 810      3.56%     93.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 590      2.60%     95.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 568      2.50%     98.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 280      1.23%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                 103      0.45%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           22628                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           22725                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     174     77.68%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     77.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     31     13.84%     91.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    19      8.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     151     71.23%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     43     20.28%     91.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    18      8.49%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 14362     80.34%     80.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2121     11.87%     92.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1379      7.71%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13707     79.87%     79.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.02%     79.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     79.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2071     12.07%     92.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1369      7.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17876                       # Type of FU issued
-system.cpu.iq.rate                           0.425366                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012531                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              58676                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             33142                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        16350                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17161                       # Type of FU issued
+system.cpu.iq.rate                           0.412177                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         212                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012354                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              57316                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             31202                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15767                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  8                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  18093                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  17366                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              235                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              220                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1385                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1318                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses           11                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          676                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           15                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          639                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            12                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    597                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1916                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    66                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21441                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2438                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1611                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    58                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          565                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  690                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16903                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1966                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               973                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                    579                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1449                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    39                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               20471                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                46                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2371                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1574                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 26                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      5                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    34                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             15                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            136                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          524                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  660                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16265                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1913                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               896                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3248                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1659                       # Number of branches executed
-system.cpu.iew.exec_stores                       1282                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.402213                       # Inst execution rate
-system.cpu.iew.wb_sent                          16611                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         16354                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10992                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     17112                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3175                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1626                       # Number of branches executed
+system.cpu.iew.exec_stores                       1262                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.390657                       # Inst execution rate
+system.cpu.iew.wb_sent                          16001                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         15771                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10637                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     16589                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.389149                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.642356                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.378792                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.641208                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           11693                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10723                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               584                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        20667                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.471621                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.370778                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               565                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        20943                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465406                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.357230                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        17422     84.30%     84.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1008      4.88%     89.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          544      2.63%     91.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          740      3.58%     95.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          368      1.78%     97.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          141      0.68%     97.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          113      0.55%     98.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           72      0.35%     98.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          259      1.25%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        17686     84.45%     84.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          994      4.75%     89.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          561      2.68%     91.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          764      3.65%     95.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          370      1.77%     97.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          129      0.62%     97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          114      0.54%     98.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           70      0.33%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          255      1.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        20667                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        20943                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -535,185 +535,185 @@ system.cpu.commit.op_class_0::MemWrite            935      9.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   259                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        41848                       # The number of ROB reads
-system.cpu.rob.rob_writes                       44866                       # The number of ROB writes
-system.cpu.timesIdled                             151                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           19397                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   255                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        41158                       # The number of ROB reads
+system.cpu.rob.rob_writes                       42744                       # The number of ROB writes
+system.cpu.timesIdled                             153                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           18910                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               7.811338                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.811338                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.128019                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.128019                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    21318                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13103                       # number of integer regfile writes
+system.cpu.cpi                               7.738848                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.738848                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.129218                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.129218                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    20871                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   12651                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                      8054                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                     5036                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    7483                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                      8081                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                     4880                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                    7277                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            82.324603                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2390                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             16.950355                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            81.971685                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2383                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               139                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.143885                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    82.324603                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020099                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020099                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    81.971685                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020013                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020013                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          139                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5349                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5349                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1533                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1533                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          857                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            857                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2390                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2390                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2390                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2390                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          136                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           136                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           78                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           78                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          214                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            214                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          214                       # number of overall misses
-system.cpu.dcache.overall_misses::total           214                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10515500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10515500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      6241000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      6241000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16756500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16756500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16756500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16756500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1669                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1669                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033936                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5305                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5305                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1525                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1525                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2383                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2383                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2383                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2383                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          123                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           123                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           77                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           77                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          200                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            200                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          200                       # number of overall misses
+system.cpu.dcache.overall_misses::total           200                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9653500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9653500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      6433000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      6433000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16086500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16086500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16086500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16086500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1648                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1648                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2604                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2604                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2604                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2604                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081486                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.081486                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.083422                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.083422                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.082181                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.082181                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.082181                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.082181                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77319.852941                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 77319.852941                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80012.820513                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80012.820513                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 78301.401869                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 78301.401869                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 78301.401869                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 78301.401869                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          241                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2583                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2583                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2583                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2583                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074636                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.074636                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.082353                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.082353                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.077429                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.077429                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.077429                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.077429                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78483.739837                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 78483.739837                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83545.454545                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 83545.454545                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80432.500000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80432.500000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80432.500000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80432.500000                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          269                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    67.250000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           72                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           72                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           72                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           72                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           78                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           78                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5436500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5436500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6163000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6163000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11599500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11599500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.038346                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.038346                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083422                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083422                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.054531                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.054531                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.054531                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.054531                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84945.312500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84945.312500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79012.820513                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79012.820513                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81686.619718                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 81686.619718                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81686.619718                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 81686.619718                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           61                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           61                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           61                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           61                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           61                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           62                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           62                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           77                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           77                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          139                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          139                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          139                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          139                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5286500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5286500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6356000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6356000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11642500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11642500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.037621                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.037621                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.082353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.082353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.053813                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.053813                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.053813                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.053813                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85266.129032                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85266.129032                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82545.454545                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82545.454545                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83758.992806                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 83758.992806                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           131.388880                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1795                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               276                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.503623                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           130.298609                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1706                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               277                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.158845                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   131.388880                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.064155                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.064155                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          276                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.134766                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              4606                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             4606                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1795                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1795                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1795                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1795                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1795                       # number of overall hits
-system.cpu.icache.overall_hits::total            1795                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          370                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           370                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          370                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            370                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          370                       # number of overall misses
-system.cpu.icache.overall_misses::total           370                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     27513500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     27513500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     27513500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     27513500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     27513500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     27513500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2165                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2165                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2165                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2165                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2165                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2165                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.170901                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.170901                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.170901                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.170901                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.170901                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.170901                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74360.810811                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74360.810811                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74360.810811                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74360.810811                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74360.810811                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74360.810811                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst   130.298609                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063622                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063622                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          277                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.135254                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4427                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4427                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1706                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1706                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1706                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1706                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1706                       # number of overall hits
+system.cpu.icache.overall_hits::total            1706                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          369                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           369                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          369                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            369                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          369                       # number of overall misses
+system.cpu.icache.overall_misses::total           369                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     28131500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     28131500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     28131500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     28131500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     28131500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     28131500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2075                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2075                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2075                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2075                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2075                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2075                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.177831                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.177831                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.177831                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.177831                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.177831                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.177831                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76237.127371                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76237.127371                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76237.127371                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76237.127371                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76237.127371                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76237.127371                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -722,120 +722,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           94                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           94                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           94                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           94                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           94                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          276                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          276                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          276                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21617000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21617000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21617000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21617000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21617000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21617000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.127483                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.127483                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.127483                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.127483                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.127483                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.127483                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78322.463768                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78322.463768                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78322.463768                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 78322.463768                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78322.463768                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 78322.463768                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           92                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           92                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           92                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           92                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          277                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          277                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          277                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          277                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          277                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          277                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22318000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22318000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22318000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22318000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22318000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22318000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.133494                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.133494                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.133494                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.133494                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.133494                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.133494                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80570.397112                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80570.397112                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80570.397112                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 80570.397112                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80570.397112                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 80570.397112                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          162.995820                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          162.374270                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              338                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002959                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.424574                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.571246                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004011                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000963                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004974                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.338432                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    32.035838                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003978                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000978                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004955                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010315                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses             3743                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3743                       # Number of data accesses
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data           78                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           78                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          275                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          275                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           64                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           64                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          275                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           417                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          275                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          417                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6046000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6046000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     21192000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     21192000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5342000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5342000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21192000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11388000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32580000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21192000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11388000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32580000                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           78                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           78                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          276                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          276                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           64                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           64                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          276                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          142                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          276                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           77                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           77                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          276                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          276                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           62                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           62                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          276                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          139                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           415                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          276                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          139                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          415                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6240500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6240500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     21891500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     21891500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5193000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5193000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     21891500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     11433500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33325000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     21891500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11433500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33325000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           77                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           77                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          277                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          277                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           62                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           62                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          277                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          139                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          416                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          277                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          139                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          416                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996377                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996377                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996390                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996390                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996377                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996390                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997608                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996377                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997596                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996390                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997608                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77512.820513                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77512.820513                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77061.818182                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77061.818182                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83468.750000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83468.750000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77061.818182                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80197.183099                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78129.496403                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77061.818182                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80197.183099                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78129.496403                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997596                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81045.454545                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81045.454545                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79317.028986                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79317.028986                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83758.064516                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83758.064516                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79317.028986                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82255.395683                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80301.204819                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79317.028986                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82255.395683                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80301.204819                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -844,108 +844,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           78                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           78                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          275                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          275                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           64                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           64                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          417                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          417                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5266000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5266000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     18442000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     18442000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4712000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4712000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18442000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9978000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28420000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18442000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9978000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28420000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          276                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          276                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           62                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           62                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          139                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          415                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          139                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          415                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5470500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5470500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19131500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19131500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4573000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4573000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19131500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10043500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     29175000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19131500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10043500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     29175000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996377                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996390                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996390                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996390                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997608                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997596                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996390                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997608                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67512.820513                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67512.820513                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67061.818182                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67061.818182                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        73625                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        73625                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67061.818182                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70267.605634                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68153.477218                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67061.818182                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70267.605634                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68153.477218                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997596                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           78                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           78                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          276                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           64                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          552                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          283                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               835                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              26688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq           77                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           77                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          277                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           62                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          554                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          278                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               832                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              26624                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          418                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          416                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                418    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                416    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            418                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            416                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         208000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        414000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        415500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        208500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp                338                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                78                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               78                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           339                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total          833                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    833                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total        26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq                77                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               77                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           338                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total          830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total        26560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   26560                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               417                       # Request fanout histogram
+system.membus.snoop_fanout::samples               415                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     417    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     415    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 417                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              505000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 415                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              500000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2222250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2216750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             10.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index c1f4aa57f..56411f6d5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -261,7 +261,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 95258693a..3cf449dc8 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    24760000                       # Number of ticks simulated
-final_tick                                   24760000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    24832500                       # Number of ticks simulated
+final_tick                                   24832500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  82189                       # Simulator instruction rate (inst/s)
-host_op_rate                                    82182                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              159657472                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295960                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  45282                       # Simulator instruction rate (inst/s)
+host_op_rate                                    45279                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               88223588                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290360                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
 sim_insts                                       12744                       # Number of instructions simulated
 sim_ops                                         12744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             40576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             22144                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62720                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        40576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           40576                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                634                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                346                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   980                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1638772213                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            894345719                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2533117932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1638772213                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1638772213                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1638772213                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           894345719                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2533117932                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           980                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             40448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             22016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        40448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           40448                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                632                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                344                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   976                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1628833182                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            886580087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2515413269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1628833182                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1628833182                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1628833182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           886580087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2515413269                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           976                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         980                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         976                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    62720                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    62464                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     62720                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     62464                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  83                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 155                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  77                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  84                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 152                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  78                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  88                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  49                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  48                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  33                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                  42                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                  39                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 30                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                 29                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 34                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 69                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 68                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 37                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24609000                       # Total gap between requests
+system.physmem.totGap                        24688000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     980                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     976                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        80                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       340                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       321                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        78                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        21                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          211                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      289.971564                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.051447                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     289.757171                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             69     32.70%     32.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           60     28.44%     61.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           22     10.43%     71.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           12      5.69%     77.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           14      6.64%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           12      5.69%     89.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      1.42%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            8      3.79%     94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           11      5.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            211                       # Bytes accessed per row activation
-system.physmem.totQLat                       12705250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  31080250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      4900000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12964.54                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          217                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      280.184332                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     175.894103                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     284.655938                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             78     35.94%     35.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           61     28.11%     64.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           19      8.76%     72.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           11      5.07%     77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           14      6.45%     84.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           13      5.99%     90.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      1.84%     92.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            6      2.76%     94.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11      5.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            217                       # Bytes accessed per row activation
+system.physmem.totQLat                       12728500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  31028500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      4880000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13041.50                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31714.54                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2533.12                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31791.50                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        2515.41                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2533.12                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     2515.41                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          19.79                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      19.79                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          19.65                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      19.65                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.43                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.42                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        761                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        749                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.65                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.74                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        25111.22                       # Average gap between requests
-system.physmem.pageHitRate                      77.65                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     861840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     470250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   4539600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                        25295.08                       # Average gap between requests
+system.physmem.pageHitRate                      76.74                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     892080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     486750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   4516200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               16083405                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                  63000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 23543775                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              996.825615                       # Core power per rank (mW)
+system.physmem_0.actBackEnergy               16092810                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  54750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 23568270                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              997.862715                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE          22500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT        22830000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     703080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     383625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2878200                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     718200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     391875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2847000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15819210                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 295500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 21605295                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              914.703429                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE         407500                       # Time in different power states
+system.physmem_1.actBackEnergy               15524235                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 557250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 21564240                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              912.772063                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         830500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        22446250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22027750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    7026                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3965                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1425                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5143                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     872                       # Number of BTB hits
+system.cpu.branchPred.lookups                    6978                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3979                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1366                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 5343                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     988                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             16.955085                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                    1033                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 76                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             18.491484                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                    1115                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 79                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4832                       # DTB read hits
-system.cpu.dtb.read_misses                         93                       # DTB read misses
+system.cpu.dtb.read_hits                         4756                       # DTB read hits
+system.cpu.dtb.read_misses                         94                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     4925                       # DTB read accesses
-system.cpu.dtb.write_hits                        2065                       # DTB write hits
-system.cpu.dtb.write_misses                        72                       # DTB write misses
+system.cpu.dtb.read_accesses                     4850                       # DTB read accesses
+system.cpu.dtb.write_hits                        2093                       # DTB write hits
+system.cpu.dtb.write_misses                        69                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2137                       # DTB write accesses
-system.cpu.dtb.data_hits                         6897                       # DTB hits
-system.cpu.dtb.data_misses                        165                       # DTB misses
+system.cpu.dtb.write_accesses                    2162                       # DTB write accesses
+system.cpu.dtb.data_hits                         6849                       # DTB hits
+system.cpu.dtb.data_misses                        163                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     7062                       # DTB accesses
-system.cpu.itb.fetch_hits                        5266                       # ITB hits
-system.cpu.itb.fetch_misses                        59                       # ITB misses
+system.cpu.dtb.data_accesses                     7012                       # DTB accesses
+system.cpu.itb.fetch_hits                        5404                       # ITB hits
+system.cpu.itb.fetch_misses                        57                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5325                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5461                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -294,318 +294,318 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            49521                       # number of cpu cycles simulated
+system.cpu.numCycles                            49666                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               1262                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          39496                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        7026                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1905                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         11647                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1505                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  695                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      5266                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   809                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              28518                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.384950                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.783550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               1235                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          39559                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6978                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               2103                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         10834                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1446                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  389                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      5404                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   838                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              27534                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.436733                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.801651                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    21883     76.73%     76.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      531      1.86%     78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      405      1.42%     80.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      525      1.84%     81.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      527      1.85%     83.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      419      1.47%     85.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      492      1.73%     86.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      463      1.62%     88.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     3273     11.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    20750     75.36%     75.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      584      2.12%     77.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      426      1.55%     79.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      584      2.12%     81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      571      2.07%     83.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      441      1.60%     84.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      491      1.78%     86.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      560      2.03%     88.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     3127     11.36%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                28518                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.141879                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.797561                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    38016                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 11989                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5115                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   629                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1147                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  585                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   376                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  32323                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   785                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1147                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    38621                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    5295                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1200                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      5143                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  5490                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  30197                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    57                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                    302                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                    566                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                   4493                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               22785                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 37650                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            37632                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                27534                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.140499                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.796501                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    37298                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 10659                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5112                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   613                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1127                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  528                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   328                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  32201                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   725                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   1127                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    37873                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    4968                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1226                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      5149                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  4466                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  30276                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    78                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                    324                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                    847                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                   3132                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               22817                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 37709                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            37691                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    13645                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 56                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             44                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2153                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2897                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1434                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                31                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               21                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 2813                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1365                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                 3                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    13677                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 60                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             48                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      2263                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2834                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1407                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                13                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                7                       # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads                 2862                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1462                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                 2                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      26855                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     22315                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               102                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           14161                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         7975                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             17                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         28518                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.782488                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.503369                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      27015                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  50                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     22338                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               130                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           14320                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         8141                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         27534                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.811288                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.520707                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               20180     70.76%     70.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                2624      9.20%     79.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1911      6.70%     86.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1348      4.73%     91.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1241      4.35%     95.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 673      2.36%     98.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 344      1.21%     99.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 144      0.50%     99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  53      0.19%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               19179     69.66%     69.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                2638      9.58%     79.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1919      6.97%     86.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1327      4.82%     91.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1227      4.46%     95.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 711      2.58%     98.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 354      1.29%     99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 138      0.50%     99.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  41      0.15%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           28518                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           27534                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      33      9.65%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    224     65.50%     75.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    85     24.85%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      32      9.64%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    217     65.36%     75.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    83     25.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7386     65.50%     65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2741     24.31%     89.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1144     10.15%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7321     66.01%     66.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2641     23.81%     89.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1123     10.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  11276                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  11090                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7337     66.46%     66.48% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.49% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.49% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.51% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2570     23.28%     89.79% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1127     10.21%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7446     66.20%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.24% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2645     23.52%     89.76% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1152     10.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  11039                       # Type of FU issued
-system.cpu.iq.FU_type::total                    22315      0.00%      0.00% # Type of FU issued
-system.cpu.iq.rate                           0.450617                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                      168                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                      174                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  342                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.007529                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.007797                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.015326                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              73550                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             41081                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19615                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total                  11248                       # Type of FU issued
+system.cpu.iq.FU_type::total                    22338      0.00%      0.00% # Type of FU issued
+system.cpu.iq.rate                           0.449764                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                      166                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                      166                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  332                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.007431                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.007431                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.014863                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              72630                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             41400                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19613                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  22631                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  22644                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               87                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               80                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1714                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           18                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          569                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1651                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          542                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           342                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               63                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked           309                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads               73                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1630                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           18                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          500                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1679                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           17                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          597                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked           278                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked           327                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1147                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    2841                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   538                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               27054                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               353                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  5710                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2799                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 51                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     37                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   505                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             36                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            142                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1136                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1278                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 21041                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2537                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2397                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           4934                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1274                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                   1127                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    2708                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   614                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               27211                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               237                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  5696                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2869                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 50                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     33                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   589                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             37                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            160                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1089                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1249                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 21052                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2447                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2411                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4858                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1286                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
 system.cpu.iew.exec_nop::0                         74                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         74                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    148                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3628                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3464                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  7092                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1676                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1656                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3332                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1091                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1067                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2158                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.424890                       # Inst execution rate
-system.cpu.iew.wb_sent::0                       10100                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        9901                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   20001                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9896                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       9739                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  19635                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   5244                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   5132                       # num instructions producing a value
-system.cpu.iew.wb_producers::total              10376                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   6970                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   6831                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              13801                       # num instructions consuming a value
+system.cpu.iew.exec_nop::1                         72                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    146                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3514                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3522                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  7036                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1644                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1639                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3283                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1067                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1111                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2178                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.423871                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        9939                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                       10068                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   20007                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9740                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9893                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  19633                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   5189                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   5256                       # num instructions producing a value
+system.cpu.iew.wb_producers::total              10445                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6868                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6926                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              13794                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.199834                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.196664                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.396498                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.752367                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.751281                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.751830                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.196110                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.199191                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.395301                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.755533                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.758880                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.757213                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           14269                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           14447                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1068                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        28453                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.449091                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.311891                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1048                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        27467                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465213                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.343088                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        23365     82.12%     82.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2421      8.51%     90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1102      3.87%     94.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          384      1.35%     95.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          323      1.14%     96.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          209      0.73%     97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          206      0.72%     98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7          116      0.41%     98.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          327      1.15%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        22438     81.69%     81.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2371      8.63%     90.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1089      3.96%     94.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          414      1.51%     95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          277      1.01%     96.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          199      0.72%     97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          197      0.72%     98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7          154      0.56%     98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          328      1.19%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        28453                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        27467                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts::0              6389                       # Number of instructions committed
 system.cpu.commit.committedInsts::1              6389                       # Number of instructions committed
 system.cpu.commit.committedInsts::total         12778                       # Number of instructions committed
@@ -707,25 +707,25 @@ system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_1::total              6389                       # Class of committed instruction
 system.cpu.commit.op_class::total               12778      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events                   327                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                       131668                       # The number of ROB reads
-system.cpu.rob.rob_writes                       56750                       # The number of ROB writes
-system.cpu.timesIdled                             392                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           21003                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   328                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                       129836                       # The number of ROB reads
+system.cpu.rob.rob_writes                       57114                       # The number of ROB writes
+system.cpu.timesIdled                             383                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           22132                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6372                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6372                       # Number of Instructions Simulated
 system.cpu.committedInsts::total                12744                       # Number of Instructions Simulated
 system.cpu.committedOps::0                       6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::1                       6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::total                  12744                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0                            7.771657                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            7.771657                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.885829                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.128673                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.128673                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.257345                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    26413                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14990                       # number of integer regfile writes
+system.cpu.cpi::0                            7.794413                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            7.794413                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.897207                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.128297                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.128297                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.256594                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    26491                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14992                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
@@ -733,294 +733,294 @@ system.cpu.misc_regfile_writes                      2                       # nu
 system.cpu.dcache.tags.replacements::0              0                       # number of replacements
 system.cpu.dcache.tags.replacements::1              0                       # number of replacements
 system.cpu.dcache.tags.replacements::total            0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           213.559941                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4863                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               346                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.054913                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           212.222617                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4769                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               344                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.863372                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   213.559941                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.052139                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.052139                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          346                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.084473                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             12116                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            12116                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         3840                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3840                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1023                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1023                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4863                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4863                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4863                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4863                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          707                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          707                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1022                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1022                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1022                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1022                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     24108500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     24108500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     53981926                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     53981926                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     78090426                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     78090426                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     78090426                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     78090426                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         4155                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         4155                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data   212.222617                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.051812                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.051812                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          344                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.083984                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses             11936                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            11936                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         3748                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3748                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1021                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1021                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4769                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4769                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4769                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4769                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          318                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           318                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          709                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          709                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1027                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1027                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1027                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1027                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24395500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24395500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     50809414                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     50809414                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     75204914                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     75204914                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     75204914                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     75204914                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         4066                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         4066                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5885                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5885                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5885                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5885                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075812                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.075812                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.408671                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.408671                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.173662                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.173662                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.173662                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.173662                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76534.920635                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76534.920635                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76353.502122                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76353.502122                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76409.418787                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76409.418787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76409.418787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76409.418787                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         6161                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         5796                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5796                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5796                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5796                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078210                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.078210                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.409827                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.409827                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.177191                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.177191                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.177191                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.177191                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76715.408805                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76715.408805                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71663.489422                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71663.489422                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73227.764362                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73227.764362                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73227.764362                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73227.764362                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         5829                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               133                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               135                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.323308                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.177778                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          114                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          114                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          562                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          562                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          676                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          676                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          676                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          676                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          201                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          201                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          346                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          346                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          346                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          346                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17596000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     17596000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12625989                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     12625989                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30221989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     30221989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30221989                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     30221989                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048375                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048375                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058794                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.058794                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058794                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.058794                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87542.288557                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87542.288557                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87075.786207                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87075.786207                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87346.789017                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 87346.789017                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87346.789017                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 87346.789017                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          120                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          120                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          563                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          563                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          683                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          683                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          683                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          683                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          198                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          198                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          344                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          344                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          344                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          344                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17299000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17299000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12670989                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     12670989                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     29969989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     29969989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     29969989                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     29969989                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.048697                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.048697                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059351                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059351                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.059351                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.059351                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87368.686869                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87368.686869                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86787.595890                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86787.595890                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87122.061047                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 87122.061047                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87122.061047                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 87122.061047                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements::0              8                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
 system.cpu.icache.tags.replacements::total            8                       # number of replacements
-system.cpu.icache.tags.tagsinuse           319.520873                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4318                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               636                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.789308                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           317.015033                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4463                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               634                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.039432                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   319.520873                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.156016                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.156016                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          628                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          256                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          372                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.306641                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11148                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11148                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4318                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4318                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4318                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4318                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4318                       # number of overall hits
-system.cpu.icache.overall_hits::total            4318                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          938                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           938                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          938                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            938                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          938                       # number of overall misses
-system.cpu.icache.overall_misses::total           938                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     69872996                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     69872996                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     69872996                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     69872996                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     69872996                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     69872996                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5256                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5256                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5256                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5256                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5256                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5256                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.178463                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.178463                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.178463                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.178463                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.178463                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.178463                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74491.466951                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74491.466951                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74491.466951                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74491.466951                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74491.466951                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74491.466951                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         3812                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   317.015033                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.154792                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.154792                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          626                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          260                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          366                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.305664                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11430                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11430                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4463                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4463                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4463                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4463                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4463                       # number of overall hits
+system.cpu.icache.overall_hits::total            4463                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          935                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           935                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          935                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            935                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          935                       # number of overall misses
+system.cpu.icache.overall_misses::total           935                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     70145997                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     70145997                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     70145997                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     70145997                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     70145997                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     70145997                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5398                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5398                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5398                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5398                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5398                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5398                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.173212                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.173212                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.173212                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.173212                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.173212                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.173212                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75022.456684                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75022.456684                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75022.456684                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75022.456684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75022.456684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75022.456684                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3484                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                79                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                77                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    48.253165                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    45.246753                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          302                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          302                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          302                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          302                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          302                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          302                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          636                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          636                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          636                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          636                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          636                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          636                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51565998                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     51565998                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51565998                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     51565998                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51565998                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     51565998                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.121005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.121005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.121005                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.121005                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.121005                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.121005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81078.613208                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81078.613208                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81078.613208                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 81078.613208                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81078.613208                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 81078.613208                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          301                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          301                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          301                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          301                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          301                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          301                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          634                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          634                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          634                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          634                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          634                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          634                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51559499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     51559499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51559499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     51559499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51559499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     51559499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.117451                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.117451                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.117451                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.117451                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.117451                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.117451                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81324.130915                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81324.130915                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81324.130915                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 81324.130915                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81324.130915                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 81324.130915                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          440.180388                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          436.545027                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 10                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              835                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.011976                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              830                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.012048                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   320.217581                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   119.962806                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009772                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003661                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.013433                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          835                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          322                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          513                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025482                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             8900                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            8900                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   317.712929                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   118.832098                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009696                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003626                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.013322                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          830                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          326                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          504                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025330                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8864                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8864                       # Number of data accesses
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          145                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          145                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          634                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          634                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          201                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          201                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          634                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          346                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           980                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          634                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          346                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          980                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     12401500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     12401500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     50585000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     50585000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     17285500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     17285500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     50585000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     29687000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     80272000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     50585000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     29687000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     80272000                       # number of overall miss cycles
-system.cpu.l2cache.ReadExReq_accesses::cpu.data          145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total          145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          636                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          636                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          201                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          201                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          636                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          346                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          982                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          636                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          346                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          982                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          632                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          632                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          198                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          198                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          632                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          344                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           976                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          632                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          344                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          976                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     12444500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     12444500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     50583000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     50583000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     16994000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     16994000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     50583000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     29438500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     80021500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     50583000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     29438500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     80021500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          634                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          634                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          198                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          634                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          344                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          978                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          634                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          344                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          978                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996855                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996855                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996845                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996845                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996855                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996845                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997963                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996855                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997955                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996845                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997963                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85527.586207                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85527.586207                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79787.066246                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79787.066246                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85997.512438                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85997.512438                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79787.066246                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85800.578035                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81910.204082                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79787.066246                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85800.578035                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81910.204082                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997955                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85236.301370                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85236.301370                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80036.392405                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80036.392405                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85828.282828                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85828.282828                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80036.392405                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85577.034884                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81989.241803                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80036.392405                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85577.034884                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81989.241803                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1029,107 +1029,107 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          145                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          145                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          634                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          634                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          201                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          201                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          634                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          346                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          980                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          634                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          346                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          980                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10951500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10951500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     44245000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     44245000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     15275500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     15275500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44245000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     26227000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     70472000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44245000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     26227000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     70472000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          632                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          632                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          198                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          198                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          632                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          344                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          976                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          632                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          344                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          976                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10984500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10984500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     44263000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     44263000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     15014000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     15014000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44263000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     25998500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     70261500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44263000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     25998500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     70261500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996855                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996855                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996845                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996845                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996855                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996845                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997963                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996855                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997955                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996845                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997963                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75527.586207                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75527.586207                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69787.066246                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69787.066246                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75997.512438                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75997.512438                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69787.066246                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75800.578035                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71910.204082                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69787.066246                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75800.578035                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71910.204082                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997955                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp           837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           832                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict            8                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq          145                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp          145                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          636                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          201                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1280                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          692                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1972                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              62848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq          146                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp          146                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          634                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          198                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1276                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          688                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1964                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              62592                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          990                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          986                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                990    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                986    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            990                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         495000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            986                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         493000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        954000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          3.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        519000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        951000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          3.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        516000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                835                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               145                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              145                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           835                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1960                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1960                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   62720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp                830                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               146                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              146                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           830                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1952                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1952                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   62464                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               980                       # Request fanout histogram
+system.membus.snoop_fanout::samples               976                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     980    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     976    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 980                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             1192500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 976                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             1189000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               4.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            5223750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            5195000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             20.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 85270cbb1..82d581de7 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    27401500                       # Number of ticks simulated
-final_tick                                   27401500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    26943000                       # Number of ticks simulated
+final_tick                                   26943000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  94035                       # Simulator instruction rate (inst/s)
-host_op_rate                                    94027                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              178462571                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293360                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  30305                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30304                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56555572                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288252                       # Number of bytes of host memory used
+host_seconds                                     0.48                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             22016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9472                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                31488                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        22016                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22016                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                344                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                148                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   492                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            803459665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            345674507                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1149134171                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       803459665                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          803459665                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           803459665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           345674507                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1149134171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           492                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             21888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9408                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                31296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21888                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                342                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   489                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            812381695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            349181606                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1161563300                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       812381695                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          812381695                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           812381695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           349181606                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1161563300                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           489                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         492                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         489                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    31488                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    31296                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     31488                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     31296                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 107                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  28                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  51                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  27                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  49                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  24                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  20                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  35                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  36                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   4                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                  1                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 57                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                 56                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 31                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                 61                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 39                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        27350000                       # Total gap between requests
+system.physmem.totGap                        26890000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     492                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     489                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       293                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       134                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -186,306 +186,306 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           71                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      405.633803                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     274.142926                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     337.087748                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             12     16.90%     16.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           19     26.76%     43.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            9     12.68%     56.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            7      9.86%     66.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            8     11.27%     77.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      5.63%     83.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      2.82%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     14.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             71                       # Bytes accessed per row activation
-system.physmem.totQLat                        3217000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12442000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      2460000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6538.62                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples           73                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      396.273973                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     268.840282                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.152795                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             12     16.44%     16.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           20     27.40%     43.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           11     15.07%     58.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7      9.59%     68.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6      8.22%     76.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.37%     78.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            5      6.85%     84.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.37%     86.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     13.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             73                       # Bytes accessed per row activation
+system.physmem.totQLat                        3681750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12850500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2445000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7529.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25288.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1149.13                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26279.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1161.56                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1149.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1161.56                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           8.98                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.98                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.07                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.07                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.52                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.53                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        412                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        409                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.74                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.64                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        55589.43                       # Average gap between requests
-system.physmem.pageHitRate                      83.74                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        54989.78                       # Average gap between requests
+system.physmem.pageHitRate                      83.64                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     302400                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     165000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2067000                       # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy                   2082600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               15796980                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy                 314250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 20171310                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              854.037999                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE         440750                       # Time in different power states
+system.physmem_0.actBackEnergy               15849990                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 267750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 20193420                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              854.974120                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         363750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        22411750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        22488750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     226800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     123750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                     241920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     132000                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                   1318200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               15639660                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy                 452250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 19286340                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              816.569039                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE        2456000                       # Time in different power states
+system.physmem_1.actBackEnergy               15637950                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 453750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 19309500                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              817.549616                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        2039000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        22168500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22166500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                    8543                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              5466                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1058                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5976                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                    3053                       # Number of BTB hits
+system.cpu.branchPred.lookups                    8026                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              5198                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               978                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 5876                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                    3165                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             51.087684                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     609                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             53.863172                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     554                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                166                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            54804                       # number of cpu cycles simulated
+system.cpu.numCycles                            53887                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              14234                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          40091                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        8543                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               3662                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                         15933                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2311                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1045                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      6440                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   572                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              32383                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.238026                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.380017                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles              13793                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          37180                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        8026                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               3719                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                         15451                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2149                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1088                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      6095                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   549                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              31410                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.183699                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.297330                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    20844     64.37%     64.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     5506     17.00%     81.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      683      2.11%     83.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      516      1.59%     85.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      807      2.49%     87.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      911      2.81%     90.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      334      1.03%     91.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      372      1.15%     92.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2410      7.44%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    20227     64.40%     64.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     5497     17.50%     81.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      701      2.23%     84.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      561      1.79%     85.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      758      2.41%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      907      2.89%     91.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      332      1.06%     92.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      377      1.20%     93.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2050      6.53%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                32383                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.155883                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.731534                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11354                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                 12386                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      6823                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   665                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1155                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  30509                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1155                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11949                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1145                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9839                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      6913                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1382                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  27687                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents                    986                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands               25054                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 51693                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            42839                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                31410                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.148941                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.689962                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    10981                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 12209                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      6549                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   597                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1074                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  28093                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1074                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    11557                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     929                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9876                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      6585                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1389                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  25671                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     10                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents                    994                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands               23124                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 48097                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            39637                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    11235                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                766                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            785                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      3795                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3676                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2349                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                     9305                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                731                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            747                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      3478                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3489                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2288                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      23661                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 726                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21924                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            9951                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         6530                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            251                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         32383                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.677022                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.427893                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      22031                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 704                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     20835                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                 8                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            8299                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         5262                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            229                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         31410                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.663324                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.403192                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               23977     74.04%     74.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3084      9.52%     83.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1575      4.86%     88.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1484      4.58%     93.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 922      2.85%     95.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 733      2.26%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 411      1.27%     99.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 157      0.48%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  40      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               23338     74.30%     74.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                2945      9.38%     83.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1556      4.95%     88.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1448      4.61%     93.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 938      2.99%     96.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 645      2.05%     98.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 357      1.14%     99.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 149      0.47%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  34      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           32383                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           31410                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     111     49.55%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     49.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     49     21.88%     71.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    64     28.57%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      59     33.33%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     51     28.81%     62.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    67     37.85%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 16295     74.32%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3505     15.99%     90.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2124      9.69%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 15392     73.88%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 3355     16.10%     89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2088     10.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21924                       # Type of FU issued
-system.cpu.iq.rate                           0.400044                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010217                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              76509                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             34365                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        20239                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  20835                       # Type of FU issued
+system.cpu.iq.rate                           0.386642                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         177                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008495                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              73265                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             31060                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19408                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  22148                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21012                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               34                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               30                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1451                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1264                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           27                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          901                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          840                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            30                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1155                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1144                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     9                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               25514                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               200                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3676                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2349                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                726                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1074                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     918                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    12                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               23852                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               173                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  3489                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2288                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                704                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            260                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          934                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1194                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20912                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3349                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1012                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            261                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          835                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1096                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20012                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  3241                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               823                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1127                       # number of nop insts executed
-system.cpu.iew.exec_refs                         5373                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     4424                       # Number of branches executed
-system.cpu.iew.exec_stores                       2024                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.381578                       # Inst execution rate
-system.cpu.iew.wb_sent                          20497                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         20239                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9852                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     12795                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1117                       # number of nop insts executed
+system.cpu.iew.exec_refs                         5240                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     4296                       # Number of branches executed
+system.cpu.iew.exec_stores                       1999                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.371370                       # Inst execution rate
+system.cpu.iew.wb_sent                          19648                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         19408                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      9326                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     12017                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.369298                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.769988                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.360161                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.776067                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           10294                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            8625                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1058                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        30320                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.500066                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.312560                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               978                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        29597                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.512282                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.339725                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        23779     78.43%     78.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         3460     11.41%     89.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1176      3.88%     93.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          592      1.95%     95.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          324      1.07%     96.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          261      0.86%     97.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          394      1.30%     98.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           63      0.21%     99.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          271      0.89%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        23176     78.31%     78.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3360     11.35%     89.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1108      3.74%     93.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          619      2.09%     95.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          326      1.10%     96.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          270      0.91%     97.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          381      1.29%     98.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           67      0.23%     99.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          290      0.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        30320                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        29597                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15162                       # Number of instructions committed
 system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -531,244 +531,244 @@ system.cpu.commit.op_class_0::MemWrite           1448      9.55%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total             15162                       # Class of committed instruction
-system.cpu.commit.bw_lim_events                   271                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                        54682                       # The number of ROB reads
-system.cpu.rob.rob_writes                       52990                       # The number of ROB writes
-system.cpu.timesIdled                             200                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           22421                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events                   290                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                        52271                       # The number of ROB reads
+system.cpu.rob.rob_writes                       49405                       # The number of ROB writes
+system.cpu.timesIdled                             197                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           22477                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
 system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               3.796342                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.796342                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.263411                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.263411                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    33404                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   18604                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    7136                       # number of misc regfile reads
+system.cpu.cpi                               3.732821                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.732821                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.267894                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.267894                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    32029                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   17799                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    6992                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            98.713941                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4125                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             28.061224                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            98.068517                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4030                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.602740                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    98.713941                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024100                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024100                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data    98.068517                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.023943                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.023943                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              9491                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             9491                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         3086                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3086                       # number of ReadReq hits
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              9286                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             9286                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         2991                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2991                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          4119                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4119                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4119                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4119                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          138                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           138                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          4024                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4024                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4024                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4024                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          131                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           131                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          547                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            547                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          547                       # number of overall misses
-system.cpu.dcache.overall_misses::total           547                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9332000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9332000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     27213977                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     27213977                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     36545977                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     36545977                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     36545977                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     36545977                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3224                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3224                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          540                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            540                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          540                       # number of overall misses
+system.cpu.dcache.overall_misses::total           540                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9101000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9101000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     26970477                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     26970477                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     36071477                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     36071477                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     36071477                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     36071477                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3122                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3122                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         4666                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         4666                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         4666                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         4666                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.042804                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.042804                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         4564                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         4564                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         4564                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         4564                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.041960                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.041960                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117231                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117231                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117231                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117231                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67623.188406                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67623.188406                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66537.841076                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66537.841076                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66811.658135                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66811.658135                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66811.658135                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66811.658135                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1080                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.118317                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.118317                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118317                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118317                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69473.282443                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69473.282443                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65942.486553                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65942.486553                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66799.031481                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66799.031481                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66799.031481                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66799.031481                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1282                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                26                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                27                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    41.538462                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    47.481481                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           73                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           67                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          399                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          399                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          399                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          399                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           65                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           65                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data          393                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          393                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          393                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          393                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           83                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          148                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5162500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5162500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6419500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6419500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11582000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11582000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11582000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11582000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020161                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020161                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5139000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5139000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6383500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6383500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11522500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11522500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11522500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11522500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020500                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020500                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031719                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.031719                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031719                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031719                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79423.076923                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79423.076923                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77343.373494                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77343.373494                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78256.756757                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78256.756757                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78256.756757                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78256.756757                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032209                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.032209                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032209                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032209                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80296.875000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80296.875000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76909.638554                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76909.638554                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78384.353741                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78384.353741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           191.519539                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                5908                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               346                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.075145                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           190.286110                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                5576                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               344                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             16.209302                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   191.519539                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.093515                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.093515                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          346                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.168945                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             13226                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            13226                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         5908                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5908                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5908                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5908                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5908                       # number of overall hits
-system.cpu.icache.overall_hits::total            5908                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          532                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           532                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          532                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            532                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          532                       # number of overall misses
-system.cpu.icache.overall_misses::total           532                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     36225500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     36225500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     36225500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     36225500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     36225500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     36225500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6440                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6440                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6440                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6440                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6440                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6440                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.082609                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.082609                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.082609                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.082609                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.082609                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.082609                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68093.045113                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68093.045113                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68093.045113                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68093.045113                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68093.045113                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68093.045113                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs           58                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   190.286110                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.092913                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.092913                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          344                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             12534                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            12534                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         5576                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5576                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5576                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5576                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5576                       # number of overall hits
+system.cpu.icache.overall_hits::total            5576                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          519                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           519                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          519                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            519                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          519                       # number of overall misses
+system.cpu.icache.overall_misses::total           519                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     36198500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     36198500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     36198500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     36198500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     36198500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     36198500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         6095                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6095                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6095                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6095                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6095                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6095                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.085152                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.085152                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.085152                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.085152                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.085152                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.085152                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69746.628131                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69746.628131                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69746.628131                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69746.628131                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69746.628131                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69746.628131                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          186                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          186                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          186                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          186                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          186                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          186                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          346                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          346                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          346                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          346                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          346                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          346                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26213500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26213500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26213500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26213500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26213500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26213500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.053727                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.053727                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.053727                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.053727                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.053727                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.053727                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75761.560694                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75761.560694                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75761.560694                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75761.560694                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75761.560694                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75761.560694                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          175                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          175                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          175                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          175                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          175                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          175                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          344                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          344                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          344                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          344                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26530000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26530000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26530000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     26530000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26530000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     26530000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.056440                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.056440                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.056440                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.056440                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.056440                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.056440                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77122.093023                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77122.093023                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77122.093023                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 77122.093023                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77122.093023                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 77122.093023                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          225.494304                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          223.995330                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              408                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.004902                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              405                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.004938                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   190.884921                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    34.609384                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005825                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001056                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006882                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          408                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012451                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4443                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4443                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   189.659398                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    34.335932                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005788                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001048                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006836                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          405                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012360                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4416                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4416                       # Number of data accesses
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            2                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -777,64 +777,64 @@ system.cpu.l2cache.overall_hits::cpu.inst            2                       # n
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          344                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          344                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data           65                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total           65                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          148                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           492                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          148                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          492                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6293500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6293500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25673000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     25673000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5066000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      5066000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25673000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     11359500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     37032500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25673000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     11359500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     37032500                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          342                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          342                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           64                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           64                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          342                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          147                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           489                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          342                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          147                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          489                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6258000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6258000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     25992500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     25992500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5044000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      5044000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25992500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     11302000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     37294500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25992500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11302000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     37294500                       # number of overall miss cycles
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          346                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          346                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           65                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total           65                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          346                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          148                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          494                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          346                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          148                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          494                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          344                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          344                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           64                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           64                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          344                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          147                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          491                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          344                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          147                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          491                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.994220                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.994220                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.994186                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.994186                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994220                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994186                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995951                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994220                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995927                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994186                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995951                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75825.301205                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75825.301205                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74630.813953                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74630.813953                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77938.461538                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77938.461538                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74630.813953                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76753.378378                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75269.308943                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74630.813953                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76753.378378                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75269.308943                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.995927                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75397.590361                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75397.590361                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76001.461988                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76001.461988                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78812.500000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78812.500000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76001.461988                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76884.353741                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76266.871166                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76001.461988                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76884.353741                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76266.871166                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -845,104 +845,104 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          344                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          344                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           65                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total           65                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          492                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          492                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5463500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5463500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22233000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22233000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4426000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4426000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22233000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9889500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     32122500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22233000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9889500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     32122500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          342                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          342                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           64                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           64                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          342                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          489                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          342                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          489                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5428000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5428000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     22572500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     22572500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4414000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4414000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9842000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     32414500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22572500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9842000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     32414500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.994220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.994186                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.994186                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994186                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995951                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994220                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995927                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994186                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995951                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65825.301205                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65825.301205                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64630.813953                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64630.813953                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68092.307692                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68092.307692                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64630.813953                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66820.945946                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65289.634146                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64630.813953                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66820.945946                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65289.634146                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995927                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65397.590361                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65397.590361                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66001.461988                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66001.461988                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68968.750000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68968.750000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66001.461988                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66952.380952                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66287.321063                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp           410                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           407                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           83                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          346                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq           65                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          692                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          295                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               987                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              31552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           64                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          688                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               981                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              31360                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          494                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples          491                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                494    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                491    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            494                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         247000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total            491                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         245500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        519000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        516000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        220500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        219000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp                408                       # Transaction distribution
+system.membus.trans_dist::ReadResp                405                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               83                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           409                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          983                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    983                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   31424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq           406                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          977                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    977                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   31232                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               492                       # Request fanout histogram
+system.membus.snoop_fanout::samples               489                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     492    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     489    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 492                       # Request fanout histogram
+system.membus.snoop_fanout::total                 489                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              593500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2604000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              9.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2584750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              9.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 679d3d472..9368b9f49 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  3 2015 17:16:20
-gem5 started Jul  3 2015 17:20:44
+gem5 compiled Sep 14 2015 22:05:26
+gem5 started Sep 14 2015 22:09:42
 gem5 executing on ribera.cs.wisc.edu
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 
@@ -18,33 +18,33 @@ Init done
 [Iteration 1, Thread 2] Got lock
 [Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 2 completed
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 3 completed
 [Iteration 4, Thread 3] Got lock
 [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 4 completed
 [Iteration 5, Thread 3] Got lock
 [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 5 completed
 [Iteration 6, Thread 3] Got lock
 [Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
@@ -53,33 +53,33 @@ Iteration 5 completed
 [Iteration 6, Thread 2] Got lock
 [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 7 completed
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 8 completed
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 9 completed
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 10, Thread 2] Got lock
 [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 107900000 because target called exit()
+Exiting @ tick 107049000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 37bdd5ca5..b23c645a0 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,85 +1,91 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000108                       # Number of seconds simulated
-sim_ticks                                   107900000                       # Number of ticks simulated
-final_tick                                  107900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000107                       # Number of seconds simulated
+sim_ticks                                   107049000                       # Number of ticks simulated
+final_tick                                  107049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 161691                       # Simulator instruction rate (inst/s)
-host_op_rate                                   161690                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               17527940                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308804                       # Number of bytes of host memory used
-host_seconds                                     6.16                       # Real time elapsed on the host
-sim_insts                                      995346                       # Number of instructions simulated
-sim_ops                                        995346                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  93620                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93620                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               10161795                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304708                       # Number of bytes of host memory used
+host_seconds                                    10.53                       # Real time elapsed on the host
+sim_insts                                      986230                       # Number of instructions simulated
+sim_ops                                        986230                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst            23168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst            23040                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             5440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst             5248                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst              192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                42944                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        23168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         5440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           29184                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               362                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                42560                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        23040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst         5248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst          192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           28800                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               360                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                85                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                82                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                 3                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   671                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           214717331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           100240964                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            50417053                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            11862836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             7710843                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             5338276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7710843                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               397998146                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      214717331                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       50417053                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        5338276                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          270472660                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          214717331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          100240964                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           50417053                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           11862836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            7710843                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            5338276                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7710843                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              397998146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           672                       # Number of read requests accepted
+system.physmem.num_reads::total                   665                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           215228540                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data           101037842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            49024279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            11957141                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst             1793571                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             7772142                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             2989285                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7772142                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               397574942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      215228540                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       49024279                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst        1793571                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        2989285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          269035675                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          215228540                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data          101037842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           49024279                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           11957141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst            1793571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            7772142                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            2989285                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7772142                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              397574942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           666                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         672                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         666                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    43008                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    42624                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     43008                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     42624                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             75                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs             89                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 114                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  30                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  66                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  27                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  18                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  24                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  29                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 14                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 65                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                 61                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                 38                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 17                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 18                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                 97                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -99,14 +105,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       107872000                       # Total gap between requests
+system.physmem.totGap                       107021000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     672                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     666                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -114,11 +120,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       188                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       399                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       198                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        52                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -210,966 +216,970 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          149                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      269.744966                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.953250                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     233.682770                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             43     28.86%     28.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           40     26.85%     55.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           25     16.78%     72.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           17     11.41%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            8      5.37%     89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            7      4.70%     93.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            4      2.68%     96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            2      1.34%     97.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            3      2.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            149                       # Bytes accessed per row activation
-system.physmem.totQLat                        7242000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  19842000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      3360000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10776.79                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          144                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      276.444444                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     188.969078                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     251.786617                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             43     29.86%     29.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           36     25.00%     54.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           28     19.44%     74.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           12      8.33%     82.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            7      4.86%     87.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            8      5.56%     93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      1.39%     94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      2.08%     96.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      3.47%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            144                       # Bytes accessed per row activation
+system.physmem.totQLat                        6009250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  18496750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      3330000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9022.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29526.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         398.59                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27772.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         398.17                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      398.59                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      398.17                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           3.11                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.38                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        512                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        511                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.19                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.73                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160523.81                       # Average gap between requests
-system.physmem.pageHitRate                      76.19                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                     710640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                     387750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                   2776800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                       160692.19                       # Average gap between requests
+system.physmem.pageHitRate                      76.73                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     703080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     383625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2769000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               34825860                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy               30339750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 75652080                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              745.478401                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE       52910500                       # Time in different power states
+system.physmem_0.actBackEnergy               37638810                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               27872250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 75978045                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              748.690472                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE       47858250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF         3380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        47852500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        51979250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                     385560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                     210375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                   2067000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                     355320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     193875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2028000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               31297275                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy               33426750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 73998240                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              729.280213                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE       59054500                       # Time in different power states
+system.physmem_1.actBackEnergy               32994450                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               31946250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 74129175                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              730.471639                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE       55670750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF         3380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        42666000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        45162250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups                  81516                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            78639                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1206                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               78220                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  75547                       # Number of BTB hits
+system.cpu0.branchPred.lookups                  81022                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            78376                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect             1100                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups               78355                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                  75640                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            96.582715                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                    751                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.BTBHitPct            96.535001                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                    645                       # Number of times the RAS was used to get a target.
 system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          215801                       # number of cpu cycles simulated
+system.cpu0.numCycles                          214099                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             19984                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        481810                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      81516                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             76298                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       165347                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   2711                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.icacheStallCycles             19687                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        478911                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      81022                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             76285                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       164512                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   2501                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                        96                       # Number of cycles fetch has spent waiting for tlb
 system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         2206                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     7238                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  649                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            188895                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.550676                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.226315                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles         1992                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     6733                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  617                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples            187540                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.553647                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.214546                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   31263     16.55%     16.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   77878     41.23%     57.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     817      0.43%     58.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1146      0.61%     58.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     622      0.33%     59.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   73043     38.67%     97.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     702      0.37%     98.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     447      0.24%     98.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2977      1.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   30407     16.21%     16.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   77695     41.43%     57.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     798      0.43%     58.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                    1205      0.64%     58.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     612      0.33%     59.04% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   73095     38.98%     98.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     670      0.36%     98.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     402      0.21%     98.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2656      1.42%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              188895                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.377737                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.232659                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   15795                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                18848                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   152228                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  669                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  1355                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                470263                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  1355                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   16424                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   2157                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         15249                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   152226                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                 1484                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                466822                       # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents                    20                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                     9                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents                   991                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands             319803                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               930944                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          703631                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               305659                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   14144                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               901                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           908                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     4515                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              148895                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              75333                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            72583                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           72320                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    390748                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded                967                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   387435                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued               23                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          13210                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        11146                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           408                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       188895                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.051060                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.134423                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total              187540                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.378432                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.236867                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   15435                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                18383                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   151822                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  650                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  1250                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                468409                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  1250                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   16041                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2079                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         14982                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   151818                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                 1370                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                465227                       # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents                   867                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands             318145                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               927822                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          700792                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               305063                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   13082                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               821                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           831                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     4377                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              148776                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              75241                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            72733                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           72329                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    389183                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded                889                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   385745                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued               31                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined          12312                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        11729                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           330                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       187540                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.056868                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.126403                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              34285     18.15%     18.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4265      2.26%     20.41% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              73704     39.02%     59.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              73391     38.85%     98.28% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1671      0.88%     99.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                904      0.48%     99.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                416      0.22%     99.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                183      0.10%     99.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 76      0.04%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              33477     17.85%     17.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4232      2.26%     20.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              73531     39.21%     59.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              73185     39.02%     98.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1601      0.85%     99.19% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                889      0.47%     99.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                403      0.21%     99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                147      0.08%     99.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                 75      0.04%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         188895                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         187540                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     90     32.14%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     32.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    85     30.36%     62.50% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  105     37.50%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     61     21.11%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     21.11% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                   125     43.25%     64.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  103     35.64%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               164414     42.44%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              148348     38.29%     80.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              74673     19.27%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               163127     42.29%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              148129     38.40%     80.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              74489     19.31%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                387435                       # Type of FU issued
-system.cpu0.iq.rate                          1.795335                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        280                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000723                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads            964068                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           404976                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       385522                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                385745                       # Type of FU issued
+system.cpu0.iq.rate                          1.801713                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        289                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000749                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads            959350                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           402446                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       383893                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                387715                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                386034                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           71972                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           71845                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2476                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2655                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           53                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1617                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation           63                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores         1674                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked            9                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked           22                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  1355                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   2123                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   37                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             464714                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              184                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               148895                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               75333                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               846                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  1250                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   2043                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   38                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             463105                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              243                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               148776                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               75241                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               770                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            53                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           331                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1113                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1444                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               386358                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               148024                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1077                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents            63                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect           318                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect          990                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1308                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               384734                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               147791                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts             1011                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        72999                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      222560                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   76623                       # Number of branches executed
-system.cpu0.iew.exec_stores                     74536                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.790344                       # Inst execution rate
-system.cpu0.iew.wb_sent                        385902                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       385522                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   228646                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   231982                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        73033                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      222131                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   76355                       # Number of branches executed
+system.cpu0.iew.exec_stores                     74340                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.796991                       # Inst execution rate
+system.cpu0.iew.wb_sent                        384301                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       383893                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   227714                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   230757                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.786470                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.985620                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.793063                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.986813                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts          13812                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts          13101                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1206                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       186239                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.420760                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.150366                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1100                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       185078                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.431116                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.149204                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        34563     18.56%     18.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        75593     40.59%     59.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         1959      1.05%     60.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          634      0.34%     60.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          503      0.27%     60.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        71729     38.51%     99.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          522      0.28%     99.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          250      0.13%     99.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        33718     18.22%     18.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        75423     40.75%     58.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         1935      1.05%     60.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          662      0.36%     60.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          535      0.29%     60.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        71534     38.65%     99.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          523      0.28%     99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          265      0.14%     99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          483      0.26%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       186239                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              450840                       # Number of instructions committed
-system.cpu0.commit.committedOps                450840                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       185078                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              449946                       # Number of instructions committed
+system.cpu0.commit.committedOps                449946                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        220135                       # Number of memory references committed
-system.cpu0.commit.loads                       146419                       # Number of loads committed
+system.cpu0.commit.refs                        219688                       # Number of memory references committed
+system.cpu0.commit.loads                       146121                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     75603                       # Number of branches committed
+system.cpu0.commit.branches                     75454                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   303990                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   303394                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass        72335     16.04%     16.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu          158286     35.11%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead         146503     32.50%     83.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite         73716     16.35%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass        72186     16.04%     16.04% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu          157988     35.11%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.16% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead         146205     32.49%     83.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite         73567     16.35%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total           450840                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events                  486                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                      649244                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     931981                       # The number of ROB writes
-system.cpu0.timesIdled                            314                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          26906                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     378421                       # Number of Instructions Simulated
-system.cpu0.committedOps                       378421                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.570267                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.570267                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.753565                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.753565                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  690917                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 311762                       # number of integer regfile writes
+system.cpu0.commit.op_class_0::total           449946                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events                  483                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                      646481                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     928572                       # The number of ROB writes
+system.cpu0.timesIdled                            313                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          26559                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     377676                       # Number of Instructions Simulated
+system.cpu0.committedOps                       377676                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              0.566885                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.566885                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.764025                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.764025                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  688304                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 310378                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 224455                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 223999                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          141.011743                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             148491                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          141.054653                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             148243                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              171                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           868.368421                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           866.918129                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.011743                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275414                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.275414                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.054653                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275497                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.275497                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           82                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.330078                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           599051                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          599051                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        75429                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          75429                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        73130                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         73130                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       148559                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          148559                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       148559                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         148559                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          540                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          540                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          544                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          544                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1084                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1084                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1084                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1084                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16932500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     16932500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35823993                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     35823993                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       460000                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       460000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     52756493                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     52756493                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     52756493                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     52756493                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        75969                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        75969                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        73674                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        73674                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses           598124                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          598124                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        75326                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          75326                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        72968                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         72968                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       148294                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          148294                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       148294                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         148294                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          561                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          561                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          557                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          557                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data         1118                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1118                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1118                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1118                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17156000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     17156000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     33757980                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     33757980                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       472500                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       472500                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     50913980                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     50913980                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     50913980                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     50913980                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        75887                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        75887                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        73525                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        73525                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       149643                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       149643                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       149643                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       149643                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.007108                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.007108                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007384                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007384                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007244                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.007244                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007244                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.007244                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31356.481481                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31356.481481                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65852.928309                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 65852.928309                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21904.761905                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 21904.761905                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48668.351476                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 48668.351476                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48668.351476                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 48668.351476                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1048                       # number of cycles access was blocked
+system.cpu0.dcache.demand_accesses::cpu0.data       149412                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       149412                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       149412                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       149412                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.007393                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.007393                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007576                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007576                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007483                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.007483                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007483                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.007483                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          891                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               16                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               27                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    65.500000                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs           33                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          357                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          357                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          369                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          369                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          726                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          726                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          726                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          726                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          378                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          378                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          380                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          380                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          758                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          758                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          758                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          758                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          183                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          358                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          358                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          358                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          358                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6813000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6813000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8643000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8643000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       439000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       439000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15456000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     15456000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15456000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     15456000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002409                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002409                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002375                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002375                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002392                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002392                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002392                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002392                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37229.508197                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37229.508197                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49388.571429                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 49388.571429                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20904.761905                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20904.761905                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43173.184358                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43173.184358                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43173.184358                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43173.184358                       # average overall mshr miss latency
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          177                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          177                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          360                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          360                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          360                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          360                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6883000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6883000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8240500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8240500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       446500                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       446500                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15123500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     15123500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15123500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     15123500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002411                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002411                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002407                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002407                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002409                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002409                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002409                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002409                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements              323                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          240.334366                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               6439                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              614                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.486971                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements              315                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          241.042514                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs               5949                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              607                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             9.800659                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   240.334366                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.469403                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.469403                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          291                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.568359                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             7852                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            7852                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst         6439                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           6439                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         6439                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            6439                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         6439                       # number of overall hits
-system.cpu0.icache.overall_hits::total           6439                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          799                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          799                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          799                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           799                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          799                       # number of overall misses
-system.cpu0.icache.overall_misses::total          799                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40829000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     40829000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     40829000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     40829000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     40829000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     40829000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         7238                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         7238                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         7238                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         7238                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         7238                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         7238                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110390                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.110390                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110390                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.110390                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110390                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.110390                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 51100.125156                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 51100.125156                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            2                       # number of cycles access was blocked
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.042514                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.470786                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.470786                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          292                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.570312                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses             7340                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            7340                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst         5949                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           5949                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         5949                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            5949                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         5949                       # number of overall hits
+system.cpu0.icache.overall_hits::total           5949                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          784                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          784                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          784                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           784                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          784                       # number of overall misses
+system.cpu0.icache.overall_misses::total          784                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40365000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     40365000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     40365000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     40365000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     40365000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     40365000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         6733                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         6733                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         6733                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         6733                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         6733                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         6733                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116441                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.116441                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116441                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.116441                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116441                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.116441                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 51485.969388                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 51485.969388                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs            2                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          184                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          184                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          184                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          184                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          184                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          615                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          615                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          615                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          615                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          615                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          615                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31621000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     31621000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31621000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     31621000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31621000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     31621000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084968                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084968                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084968                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.084968                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084968                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.084968                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          176                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          176                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          176                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          176                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          176                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          176                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          608                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          608                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          608                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          608                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          608                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          608                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31177000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     31177000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31177000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     31177000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31177000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     31177000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090302                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.090302                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090302                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.090302                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090302                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.090302                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  53963                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            50167                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             1346                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               46229                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  44971                       # Number of BTB hits
+system.cpu1.branchPred.lookups                  50039                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            46665                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect             1271                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups               42823                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                  41749                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            97.278764                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                    927                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct            97.492002                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                    914                       # Number of times the RAS was used to get a target.
 system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          162372                       # number of cpu cycles simulated
+system.cpu1.numCycles                          161348                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             29926                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        299894                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      53963                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             45898                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       123960                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   2845                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.icacheStallCycles             31303                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        275372                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      50039                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             42663                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       121719                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   2699                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles         1155                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    20576                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  472                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            156476                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.916550                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.231802                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.PendingTrapStallCycles         1084                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                    21928                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  442                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            155480                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.771109                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.178899                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   52995     33.87%     33.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   51987     33.22%     67.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    5834      3.73%     70.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3448      2.20%     73.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     958      0.61%     73.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   34873     22.29%     95.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1256      0.80%     96.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     838      0.54%     97.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    4287      2.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   58088     37.36%     37.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   49421     31.79%     69.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    6835      4.40%     73.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3518      2.26%     75.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     944      0.61%     76.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   30727     19.76%     96.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1228      0.79%     96.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     804      0.52%     97.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    3915      2.52%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              156476                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.332342                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.846956                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   18007                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                50929                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    83026                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 3082                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  1422                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                283749                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  1422                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   18719                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  22929                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         13387                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    84356                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                15653                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                280426                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                 13898                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total              155480                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.310131                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.706696                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   17833                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                58352                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    74506                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 3430                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  1349                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                260078                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  1349                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   18539                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  27109                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         13862                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    76429                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                18182                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                256857                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                 16651                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                    16                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.FullRegisterEvents               6                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands             198372                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               540599                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          420692                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               183271                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   15101                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1203                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1280                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    20103                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               79058                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              37890                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            37399                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           32713                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    233810                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               5671                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   234514                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               46                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          14000                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        11968                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           653                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       156476                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.498722                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.383815                       # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands             180872                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               489824                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          382391                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               167019                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   13853                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1180                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1251                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    22657                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               71171                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              33454                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            33920                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           28372                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    213121                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               6586                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   214969                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued               17                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          13076                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        10906                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           730                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       155480                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.382615                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.383057                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              56669     36.22%     36.22% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              19562     12.50%     48.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              37085     23.70%     72.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              36801     23.52%     95.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3420      2.19%     98.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1602      1.02%     99.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                884      0.56%     99.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                239      0.15%     99.86% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                214      0.14%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              61906     39.82%     39.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              21977     14.13%     53.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              32894     21.16%     75.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              32429     20.86%     95.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3365      2.16%     98.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1605      1.03%     99.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                896      0.58%     99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                208      0.13%     99.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                200      0.13%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         156476                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         155480                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     87     24.58%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     24.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    58     16.38%     40.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  209     59.04%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     79     23.72%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     23.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    45     13.51%     37.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  209     62.76%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               114757     48.93%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               82569     35.21%     84.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              37188     15.86%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               106597     49.59%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               75532     35.14%     84.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              32840     15.28%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                234514                       # Type of FU issued
-system.cpu1.iq.rate                          1.444301                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        354                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001510                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            625904                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           253521                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       232777                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                214969                       # Type of FU issued
+system.cpu1.iq.rate                          1.332331                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        333                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001549                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            585768                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           232822                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       213429                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                234868                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                215302                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           32465                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           28182                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2830                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2653                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1669                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         1503                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  1422                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   6958                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             277649                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              222                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                79058                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               37890                       # Number of dispatched store instructions
+system.cpu1.iew.iewSquashCycles                  1349                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   7989                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   73                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             254448                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              142                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                71171                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               33454                       # Number of dispatched store instructions
 system.cpu1.iew.iewDispNonSpecInsts              1130                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           481                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1587                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               233397                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                77941                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1117                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           452                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         1051                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1503                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               213962                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                70077                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             1007                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        38168                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      115010                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   47577                       # Number of branches executed
-system.cpu1.iew.exec_stores                     37069                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.437421                       # Inst execution rate
-system.cpu1.iew.wb_sent                        233106                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       232777                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   132706                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   139339                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        34741                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      102825                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   44094                       # Number of branches executed
+system.cpu1.iew.exec_stores                     32748                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.326090                       # Inst execution rate
+system.cpu1.iew.wb_sent                        213711                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       213429                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   120431                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   127039                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.433603                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.952397                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.322787                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.947984                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts          14853                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           5018                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1346                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       153761                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.708866                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.078798                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts          13922                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5856                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1271                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       152910                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.572631                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.035068                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        61362     39.91%     39.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        44235     28.77%     68.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         5219      3.39%     72.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         5854      3.81%     75.88% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1519      0.99%     76.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        32513     21.15%     98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          819      0.53%     98.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7          953      0.62%     99.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8         1287      0.84%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        67472     44.13%     44.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        40678     26.60%     70.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5251      3.43%     74.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         6680      4.37%     78.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1520      0.99%     79.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        28236     18.47%     97.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          823      0.54%     98.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          947      0.62%     99.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8         1303      0.85%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       153761                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              262757                       # Number of instructions committed
-system.cpu1.commit.committedOps                262757                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       152910                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              240471                       # Number of instructions committed
+system.cpu1.commit.committedOps                240471                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        112449                       # Number of memory references committed
-system.cpu1.commit.loads                        76228                       # Number of loads committed
-system.cpu1.commit.membars                       4303                       # Number of memory barriers committed
-system.cpu1.commit.branches                     46487                       # Number of branches committed
+system.cpu1.commit.refs                        100469                       # Number of memory references committed
+system.cpu1.commit.loads                        68518                       # Number of loads committed
+system.cpu1.commit.membars                       5139                       # Number of memory barriers committed
+system.cpu1.commit.branches                     43053                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   181057                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   165641                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass        37276     14.19%     14.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu          108729     41.38%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead          80531     30.65%     86.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite         36221     13.78%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass        33840     14.07%     14.07% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu          101023     42.01%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult              0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead          73657     30.63%     86.71% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite         31951     13.29%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total           262757                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events                 1287                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                      429498                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     557934                       # The number of ROB writes
-system.cpu1.timesIdled                            216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           5896                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       46085                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     221178                       # Number of Instructions Simulated
-system.cpu1.committedOps                       221178                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.734124                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.734124                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.362168                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.362168                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  405088                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 189742                       # number of integer regfile writes
+system.cpu1.commit.op_class_0::total           240471                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events                 1303                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                      405414                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     511356                       # The number of ROB writes
+system.cpu1.timesIdled                            220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           5868                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       45259                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     201492                       # Number of Instructions Simulated
+system.cpu1.committedOps                       201492                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              0.800766                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.800766                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.248804                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.248804                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  368266                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 172947                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 116634                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 104453                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           25.592984                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              42361                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1512.892857                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           25.714463                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              38066                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1312.620690                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.592984                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.049986                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.049986                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.714463                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050224                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.050224                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           326938                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          326938                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        44990                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          44990                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        35982                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         35982                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        80972                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           80972                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        80972                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          80972                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          461                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          461                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          170                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          170                       # number of WriteReq misses
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           295559                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          295559                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        41369                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          41369                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        31720                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         31720                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           15                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        73089                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           73089                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        73089                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          73089                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          504                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          504                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          160                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          160                       # number of WriteReq misses
 system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
 system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          631                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           631                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          631                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          631                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      8707500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      8707500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      4222000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      4222000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       652500                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       652500                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     12929500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     12929500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     12929500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     12929500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        45451                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        45451                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        36152                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        36152                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           69                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        81603                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        81603                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        81603                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        81603                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.010143                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.010143                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004702                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004702                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.811594                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.811594                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007733                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.007733                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007733                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.007733                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18888.286334                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24835.294118                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11651.785714                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20490.491284                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20490.491284                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20490.491284                       # average overall miss latency
+system.cpu1.dcache.demand_misses::cpu1.data          664                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           664                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          664                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          664                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      9769000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      9769000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3369500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      3369500                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       693500                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       693500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     13138500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     13138500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     13138500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     13138500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        41873                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        41873                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        31880                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        31880                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        73753                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        73753                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        73753                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        73753                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.012036                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.012036                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.005019                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.005019                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.788732                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.788732                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.009003                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.009003                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.009003                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.009003                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1178,518 +1188,517 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          303                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          303                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           62                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           62                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          365                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          365                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          365                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          365                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          158                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          332                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          332                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           53                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           53                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          385                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          385                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          385                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          385                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          172                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          172                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
 system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
 system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1924500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1924500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1959500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1959500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       596500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       596500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3884000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3884000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3884000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3884000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003476                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003476                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002987                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002987                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.811594                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.811594                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003260                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003260                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003260                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003260                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.379747                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18143.518519                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18143.518519                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10651.785714                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10651.785714                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14601.503759                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14601.503759                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14601.503759                       # average overall mshr miss latency
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          279                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          279                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          279                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2195000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2195000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1746000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1746000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       637500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       637500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3941000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      3941000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3941000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      3941000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004108                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.004108                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003356                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003356                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.788732                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.788732                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003783                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003783                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003783                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003783                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements              385                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           85.488179                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              19990                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs              500                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.980000                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements              383                       # number of replacements
+system.cpu1.icache.tags.tagsinuse           84.275379                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              21349                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              496                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            43.042339                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    85.488179                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.166969                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.166969                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          115                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    84.275379                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.164600                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.164600                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          113                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.224609                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            21076                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           21076                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        19990                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          19990                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        19990                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           19990                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        19990                       # number of overall hits
-system.cpu1.icache.overall_hits::total          19990                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          586                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          586                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          586                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           586                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          586                       # number of overall misses
-system.cpu1.icache.overall_misses::total          586                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     14253000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     14253000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     14253000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     14253000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     14253000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     14253000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        20576                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        20576                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        20576                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        20576                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        20576                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        20576                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028480                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.028480                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028480                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.028480                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028480                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.028480                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 24322.525597                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 24322.525597                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          114                       # number of cycles access was blocked
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.220703                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses            22424                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           22424                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst        21349                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          21349                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        21349                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           21349                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        21349                       # number of overall hits
+system.cpu1.icache.overall_hits::total          21349                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          579                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          579                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          579                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           579                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          579                       # number of overall misses
+system.cpu1.icache.overall_misses::total          579                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     13955500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     13955500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     13955500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     13955500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     13955500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     13955500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        21928                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        21928                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        21928                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        21928                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        21928                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        21928                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.026405                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.026405                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.026405                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.026405                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.026405                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.026405                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24102.763385                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24102.763385                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          125                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs           57                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    62.500000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           86                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           86                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           86                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          500                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total          500                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst          500                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total          500                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst          500                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total          500                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11778500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     11778500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11778500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     11778500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11778500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     11778500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024300                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024300                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024300                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024300                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024300                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024300                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst        23557                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total        23557                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst        23557                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total        23557                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst        23557                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total        23557                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           83                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           83                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           83                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           83                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           83                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          496                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          496                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          496                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          496                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          496                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          496                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11502500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total     11502500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11502500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total     11502500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11502500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total     11502500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022619                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022619                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022619                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.022619                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022619                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.022619                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  40179                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            36730                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             1284                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               32851                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  31814                       # Number of BTB hits
+system.cpu2.branchPred.lookups                  42880                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            39445                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect             1259                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups               35521                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                  34492                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            96.843323                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                    891                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct            97.103122                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                    904                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          162000                       # number of cpu cycles simulated
+system.cpu2.numCycles                          160976                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             38502                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        208114                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      40179                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             32705                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       119095                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   2725                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles             36449                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        226588                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      42880                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             35396                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       120624                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   2677                       # Number of cycles fetch has spent squashing
 system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         1151                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    29772                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  430                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            160123                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.299713                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            1.967894                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles         1157                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    27680                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  445                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            159581                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.419893                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.036694                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   78817     49.22%     49.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   43234     27.00%     76.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                   10666      6.66%     82.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3447      2.15%     85.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                    1063      0.66%     85.70% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   17019     10.63%     96.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1193      0.75%     97.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     770      0.48%     97.56% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3914      2.44%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   73772     46.23%     46.23% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   45044     28.23%     74.45% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    9695      6.08%     80.53% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3476      2.18%     82.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     968      0.61%     83.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   20661     12.95%     96.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1186      0.74%     97.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     799      0.50%     97.51% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    3980      2.49%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              160123                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.248019                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.284654                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   17927                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                88037                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    47537                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 5250                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  1362                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                193193                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  1362                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   18611                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  44936                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         13295                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    49321                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                32588                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                189743                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                 29082                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                    12                       # Number of times rename has blocked due to LQ full
+system.cpu2.fetch.rateDist::total              159581                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.266375                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.407589                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   17760                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                80804                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    54882                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 4787                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  1338                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                211151                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  1338                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   18439                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  40468                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         13548                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    56825                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                28953                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                208031                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                 26065                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                    14                       # Number of times rename has blocked due to LQ full
 system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands             129905                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               340650                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          270570                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               115581                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   14324                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1221                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1285                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    37412                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               47453                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              19802                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            23979                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           14667                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    152040                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded              10334                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   157175                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued               54                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          13577                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        11994                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.rename.RenamedOperands             143630                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               381000                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          300757                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               129882                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   13748                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1193                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1262                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    33404                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               53977                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              23458                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            26723                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           18373                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    168634                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               9408                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   173236                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued               15                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          12983                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        10808                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu2.iq.iqSquashedNonSpecRemoved           781                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       160123                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.981589                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.305622                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::samples       159581                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.085568                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.335871                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              83163     51.94%     51.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              32837     20.51%     72.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              19129     11.95%     84.39% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              18742     11.70%     96.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3350      2.09%     98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1588      0.99%     99.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                888      0.55%     99.73% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                222      0.14%     99.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                204      0.13%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              77748     48.72%     48.72% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              30232     18.94%     67.66% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              22868     14.33%     81.99% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              22470     14.08%     96.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3364      2.11%     98.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1606      1.01%     99.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                879      0.55%     99.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                214      0.13%     99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                200      0.13%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         160123                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         159581                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     85     23.42%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     23.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    69     19.01%     42.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  209     57.58%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     79     23.94%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     23.94% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    42     12.73%     36.67% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  209     63.33%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu                82729     52.63%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     52.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               55347     35.21%     87.85% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              19099     12.15%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu                89318     51.56%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     51.56% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               61054     35.24%     86.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              22864     13.20%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                157175                       # Type of FU issued
-system.cpu2.iq.rate                          0.970216                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        363                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.002310                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            474890                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           175995                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       155491                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                173236                       # Type of FU issued
+system.cpu2.iq.rate                          1.076160                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        330                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001905                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            506398                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           191064                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       171727                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                157538                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                173566                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           14398                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           18193                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2822                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2642                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1616                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1482                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  1362                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                  11555                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   80                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             187117                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              206                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                47453                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               19802                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1131                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    44                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  1338                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                  10563                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   81                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             205567                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              184                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                53977                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               23458                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1137                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            44                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           462                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         1028                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1490                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               156065                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                46210                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1110                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            39                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           430                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect         1053                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1483                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               172231                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                52840                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1005                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        24743                       # number of nop insts executed
-system.cpu2.iew.exec_refs                       65197                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   33975                       # Number of branches executed
-system.cpu2.iew.exec_stores                     18987                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.963364                       # Inst execution rate
-system.cpu2.iew.wb_sent                        155796                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       155491                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                    82775                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                    89322                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        27525                       # number of nop insts executed
+system.cpu2.iew.exec_refs                       75615                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   36863                       # Number of branches executed
+system.cpu2.iew.exec_stores                     22775                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.069917                       # Inst execution rate
+system.cpu2.iew.wb_sent                        171997                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       171727                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                    93200                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                    99800                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.959821                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.926703                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.066786                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.933868                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts          14525                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           9553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1284                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       157478                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.095639                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.783689                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts          13823                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           8627                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1259                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       157016                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.220837                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.865055                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        92218     58.56%     58.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        30640     19.46%     78.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         5207      3.31%     81.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3        10311      6.55%     87.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1532      0.97%     88.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        14554      9.24%     98.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          759      0.48%     98.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7          956      0.61%     99.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8         1301      0.83%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        86039     54.80%     54.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        33434     21.29%     76.09% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         5238      3.34%     79.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         9429      6.01%     85.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1533      0.98%     86.41% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        18255     11.63%     98.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          831      0.53%     98.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          955      0.61%     99.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8         1302      0.83%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       157478                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              172539                       # Number of instructions committed
-system.cpu2.commit.committedOps                172539                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       157016                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              191691                       # Number of instructions committed
+system.cpu2.commit.committedOps                191691                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                         62817                       # Number of memory references committed
-system.cpu2.commit.loads                        44631                       # Number of loads committed
-system.cpu2.commit.membars                       8825                       # Number of memory barriers committed
-system.cpu2.commit.branches                     32966                       # Number of branches committed
+system.cpu2.commit.refs                         73311                       # Number of memory references committed
+system.cpu2.commit.loads                        51335                       # Number of loads committed
+system.cpu2.commit.membars                       7910                       # Number of memory barriers committed
+system.cpu2.commit.branches                     35845                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   117894                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   131277                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        23742     13.76%     13.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu           77155     44.72%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult              0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     58.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead          53456     30.98%     89.46% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite         18186     10.54%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass        26632     13.89%     13.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu           83838     43.74%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult              0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     57.63% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead          59245     30.91%     88.54% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite         21976     11.46%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total           172539                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events                 1301                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                      342655                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     376773                       # The number of ROB writes
-system.cpu2.timesIdled                            206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           1877                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       46457                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     139972                       # Number of Instructions Simulated
-system.cpu2.committedOps                       139972                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.157374                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.157374                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.864025                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.864025                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  255225                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 121437                       # number of integer regfile writes
+system.cpu2.commit.op_class_0::total           191691                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events                 1302                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                      360642                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     413593                       # The number of ROB writes
+system.cpu2.timesIdled                            204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           1395                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       45631                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     157149                       # Number of Instructions Simulated
+system.cpu2.committedOps                       157149                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.024353                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.024353                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.976226                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.976226                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  286558                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 135654                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                  66781                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                  77226                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           23.055357                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              24315                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs           838.448276                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           23.071332                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              27978                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs           999.214286                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    23.055357                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.045030                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.045030                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    23.071332                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.045061                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.045061                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           200189                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          200189                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        31354                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          31354                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        17953                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         17953                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           17                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             17                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        49307                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           49307                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        49307                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          49307                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          441                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          441                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          151                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          151                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           65                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           65                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          592                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           592                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          592                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          592                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      6519500                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      6519500                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3142000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3142000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       710000                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       710000                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      9661500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      9661500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      9661500                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      9661500                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        31795                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        31795                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        18104                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        18104                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           82                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           82                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        49899                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        49899                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        49899                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        49899                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.013870                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.013870                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.008341                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.008341                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.792683                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.792683                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.011864                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.011864                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.011864                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.011864                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14783.446712                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 14783.446712                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20807.947020                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 20807.947020                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10923.076923                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 10923.076923                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 16320.101351                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 16320.101351                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 16320.101351                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 16320.101351                       # average overall miss latency
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           226658                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          226658                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        34141                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          34141                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        21749                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         21749                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           19                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        55890                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           55890                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        55890                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          55890                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          483                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          483                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          156                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          156                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           52                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          639                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           639                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          639                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          639                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      7783500                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      7783500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3187000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3187000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       671500                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       671500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     10970500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     10970500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     10970500                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     10970500                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        34624                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        34624                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        21905                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        21905                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        56529                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        56529                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        56529                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        56529                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.013950                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.013950                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.007122                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.007122                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.732394                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.732394                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.011304                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.011304                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.011304                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.011304                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16114.906832                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 16114.906832                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20429.487179                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 20429.487179                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12913.461538                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 12913.461538                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17168.231612                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 17168.231612                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17168.231612                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1698,517 +1707,517 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          267                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          267                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           54                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           54                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          321                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          321                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          321                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          321                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          174                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data           97                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total           97                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           65                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           65                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1675000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1675000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1750000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1750000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       645000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       645000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3425000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3425000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3425000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3425000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.005473                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.005473                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.005358                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.005358                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.792683                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.792683                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.005431                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.005431                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.005431                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.005431                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9626.436782                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9626.436782                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18041.237113                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18041.237113                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  9923.076923                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  9923.076923                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12638.376384                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12638.376384                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12638.376384                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12638.376384                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          311                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          311                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           53                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           53                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          364                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          364                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          364                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          364                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          172                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          172                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          103                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           52                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          275                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          275                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          275                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          275                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1811500                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1811500                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1702500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1702500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       619500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       619500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3514000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3514000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3514000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3514000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004968                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004968                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.004702                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.004702                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.732394                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.732394                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004865                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.004865                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004865                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.004865                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.tags.replacements              387                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           74.683777                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              29208                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs              496                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            58.887097                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.replacements              386                       # number of replacements
+system.cpu2.icache.tags.tagsinuse           77.667456                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs              27109                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              500                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs            54.218000                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.683777                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.145867                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.145867                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024          109                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    77.667456                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.151694                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.151694                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          114                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024     0.212891                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            30268                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           30268                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst        29208                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          29208                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        29208                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           29208                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        29208                       # number of overall hits
-system.cpu2.icache.overall_hits::total          29208                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          564                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          564                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          564                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           564                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          564                       # number of overall misses
-system.cpu2.icache.overall_misses::total          564                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7822000                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      7822000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      7822000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      7822000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      7822000                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      7822000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        29772                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        29772                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        29772                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        29772                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        29772                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        29772                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.018944                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.018944                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.018944                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.018944                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.018944                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.018944                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.794326                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 13868.794326                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13868.794326                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 13868.794326                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13868.794326                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 13868.794326                       # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.222656                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses            28180                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           28180                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst        27109                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          27109                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        27109                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           27109                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        27109                       # number of overall hits
+system.cpu2.icache.overall_hits::total          27109                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          571                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          571                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          571                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           571                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          571                       # number of overall misses
+system.cpu2.icache.overall_misses::total          571                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7541500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      7541500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      7541500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      7541500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      7541500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      7541500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        27680                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        27680                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        27680                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        27680                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        27680                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        27680                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.020629                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.020629                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.020629                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.020629                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.020629                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.020629                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 13207.530648                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 13207.530648                       # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          496                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          496                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          496                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          496                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          496                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          496                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6709500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      6709500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6709500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      6709500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6709500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      6709500                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.016660                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.016660                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.016660                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.016660                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.016660                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.016660                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           71                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           71                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           71                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           71                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          500                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          500                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          500                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          500                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          500                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          500                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6543500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      6543500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6543500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      6543500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6543500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      6543500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.018064                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.018064                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.018064                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.018064                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.018064                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.018064                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst        13087                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total        13087                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst        13087                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total        13087                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst        13087                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total        13087                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  59537                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            56113                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             1261                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               52336                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  51268                       # Number of BTB hits
+system.cpu3.branchPred.lookups                  58611                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            55067                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect             1279                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups               51125                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                  50131                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            97.959340                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                    894                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct            98.055746                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                    906                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          161647                       # number of cpu cycles simulated
+system.cpu3.numCycles                          160611                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             26901                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        335954                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      59537                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             52162                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       130682                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   2681                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.icacheStallCycles             27021                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        330369                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      58611                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             51037                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       129883                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   2715                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles         1202                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                    18139                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  423                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            160153                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             2.097707                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.240976                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.PendingTrapStallCycles         1165                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines                    18269                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  450                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            159439                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             2.072071                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.246890                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   45773     28.58%     28.58% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   56940     35.55%     64.13% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    4846      3.03%     67.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3496      2.18%     69.34% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                    1060      0.66%     70.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   42180     26.34%     96.34% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1201      0.75%     97.09% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     768      0.48%     97.57% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3889      2.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   47077     29.53%     29.53% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   55913     35.07%     64.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    4932      3.09%     67.69% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3522      2.21%     69.90% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     934      0.59%     70.48% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   40952     25.69%     96.17% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1272      0.80%     96.97% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     798      0.50%     97.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    4039      2.53%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              160153                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.368315                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       2.078319                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   16971                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                42083                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    97172                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 2577                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  1340                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                322134                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  1340                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   17645                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  17747                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         12855                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    98257                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                12299                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                318864                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                 10783                       # Number of times rename has blocked due to IQ full
+system.cpu3.fetch.rateDist::total              159439                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.364925                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       2.056951                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   16993                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                43740                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    94729                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 2610                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  1357                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                315004                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  1357                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   17735                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  17944                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         14128                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    95562                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                12703                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                311495                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                 10931                       # Number of times rename has blocked due to IQ full
 system.cpu3.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
 system.cpu3.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands             225541                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               621446                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          481213                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               211532                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   14009                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1171                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1234                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    16730                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               92339                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              45060                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            43467                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           39931                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    267326                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               4600                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   267770                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          12807                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        10139                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           551                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       160153                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.671964                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.354316                       # Number of insts issued each cycle
+system.cpu3.rename.RenamedOperands             220426                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               606441                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          469854                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               206787                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   13639                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1207                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1278                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    17457                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               89942                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              43802                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            42282                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           38692                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    261084                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               4750                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   261694                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued                1                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          12498                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined         9712                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           614                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       159439                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.641342                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.359128                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              48755     30.44%     30.44% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              16655     10.40%     40.84% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              44376     27.71%     68.55% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              43948     27.44%     95.99% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3484      2.18%     98.17% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1651      1.03%     99.20% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                861      0.54%     99.74% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                222      0.14%     99.87% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                201      0.13%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              50249     31.52%     31.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              16842     10.56%     42.08% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              43259     27.13%     69.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              42799     26.84%     96.05% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3393      2.13%     98.18% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1616      1.01%     99.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                876      0.55%     99.75% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                211      0.13%     99.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                194      0.12%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         160153                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         159439                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     86     25.67%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.67% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    40     11.94%     37.61% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  209     62.39%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     81     26.21%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.21% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    19      6.15%     32.36% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  209     67.64%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               128178     47.87%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               95149     35.53%     83.40% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              44443     16.60%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               125700     48.03%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               92778     35.45%     83.49% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              43216     16.51%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                267770                       # Type of FU issued
-system.cpu3.iq.rate                          1.656511                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        335                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001251                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            696028                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           284773                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       266078                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                261694                       # Type of FU issued
+system.cpu3.iq.rate                          1.629365                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        309                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001181                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            683137                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           278366                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       260191                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                268105                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                262003                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           39763                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           38539                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2450                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2394                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1547                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           34                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1484                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  1340                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                   5357                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   49                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             316296                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              170                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                92339                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               45060                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1094                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  1357                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   5389                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   51                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             309030                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              159                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                89942                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               43802                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1148                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    37                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            40                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           466                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         1001                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1467                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               266621                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                91475                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1149                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           441                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect         1075                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1516                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               260676                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                89042                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             1018                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        44370                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      135810                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   53906                       # Number of branches executed
-system.cpu3.iew.exec_stores                     44335                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.649403                       # Inst execution rate
-system.cpu3.iew.wb_sent                        266372                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       266078                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   153535                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   160065                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        43196                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      132177                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   52784                       # Number of branches executed
+system.cpu3.iew.exec_stores                     43135                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.623027                       # Inst execution rate
+system.cpu3.iew.wb_sent                        260451                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       260191                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   149829                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   156442                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.646044                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.959204                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.620007                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.957729                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts          13497                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           4049                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1261                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       157643                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.920440                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.127029                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts          13144                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           4136                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1279                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       156952                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.884863                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     2.121598                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        52663     33.41%     33.41% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        50442     32.00%     65.40% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         5240      3.32%     68.73% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         4903      3.11%     71.84% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1534      0.97%     72.81% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        39716     25.19%     98.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          903      0.57%     98.58% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7          957      0.61%     99.18% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8         1285      0.82%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        54210     34.54%     34.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        49323     31.43%     65.96% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         5280      3.36%     69.33% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         4930      3.14%     72.47% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1531      0.98%     73.45% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        38585     24.58%     98.03% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          839      0.53%     98.56% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          955      0.61%     99.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8         1299      0.83%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       157643                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              302744                       # Number of instructions committed
-system.cpu3.commit.committedOps                302744                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       156952                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              295833                       # Number of instructions committed
+system.cpu3.commit.committedOps                295833                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        133402                       # Number of memory references committed
-system.cpu3.commit.loads                        89889                       # Number of loads committed
-system.cpu3.commit.membars                       3344                       # Number of memory barriers committed
-system.cpu3.commit.branches                     52826                       # Number of branches committed
+system.cpu3.commit.refs                        129866                       # Number of memory references committed
+system.cpu3.commit.loads                        87548                       # Number of loads committed
+system.cpu3.commit.membars                       3423                       # Number of memory barriers committed
+system.cpu3.commit.branches                     51706                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   208356                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   203693                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass        43625     14.41%     14.41% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu          122373     40.42%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult              0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.83% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead          93233     30.80%     85.63% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite         43513     14.37%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass        42497     14.37%     14.37% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu          120047     40.58%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult              0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.94% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead          90971     30.75%     85.70% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite         42318     14.30%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total           302744                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events                 1285                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                      472013                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     634991                       # The number of ROB writes
-system.cpu3.timesIdled                            206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1494                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       46809                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     255775                       # Number of Instructions Simulated
-system.cpu3.committedOps                       255775                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              0.631989                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.631989                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.582306                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.582306                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  467282                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 217631                       # number of integer regfile writes
+system.cpu3.commit.op_class_0::total           295833                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events                 1299                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                      464044                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     620441                       # The number of ROB writes
+system.cpu3.timesIdled                            203                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           1172                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       45995                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     249913                       # Number of Instructions Simulated
+system.cpu3.committedOps                       249913                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              0.642668                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.642668                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.556014                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.556014                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  456401                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 212686                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 137439                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 133817                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           24.171664                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              49547                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           24.217896                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              48316                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1769.535714                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1725.571429                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.171664                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047210                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.047210                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.217896                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047301                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.047301                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           381069                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          381069                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        51168                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          51168                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        43290                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         43290                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           10                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        94458                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           94458                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        94458                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          94458                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          527                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          527                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          164                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          164                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           49                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           49                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          691                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           691                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          691                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          691                       # number of overall misses
+system.cpu3.dcache.tags.tag_accesses           371433                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          371433                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        49959                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          49959                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        42098                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         42098                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           13                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        92057                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           92057                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        92057                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          92057                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          521                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          521                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          153                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          153                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           54                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          674                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           674                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          674                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          674                       # number of overall misses
 system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      8076500                       # number of ReadReq miss cycles
 system.cpu3.dcache.ReadReq_miss_latency::total      8076500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3222500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3222500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       607500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       607500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     11299000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     11299000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     11299000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     11299000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        51695                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        51695                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        43454                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        43454                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           59                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           59                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        95149                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        95149                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        95149                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        95149                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010194                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.010194                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003774                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.003774                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.830508                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.830508                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007262                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.007262                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007262                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.007262                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15325.426945                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 15325.426945                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19649.390244                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 19649.390244                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12397.959184                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 12397.959184                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16351.664255                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 16351.664255                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16351.664255                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 16351.664255                       # average overall miss latency
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3408500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3408500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       574500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       574500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     11485000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     11485000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     11485000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     11485000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        50480                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        50480                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        42251                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        42251                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           67                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        92731                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        92731                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        92731                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        92731                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010321                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.010321                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003621                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.003621                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.805970                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.805970                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007268                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.007268                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007268                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.007268                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2217,389 +2226,391 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          382                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          382                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           52                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          434                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          434                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          434                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          434                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          145                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          145                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          112                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          112                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           49                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           49                       # number of SwapReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          369                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          369                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           48                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           48                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          417                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          417                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          417                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          417                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          152                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           54                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
 system.cpu3.dcache.demand_mshr_misses::cpu3.data          257                       # number of demand (read+write) MSHR misses
 system.cpu3.dcache.demand_mshr_misses::total          257                       # number of demand (read+write) MSHR misses
 system.cpu3.dcache.overall_mshr_misses::cpu3.data          257                       # number of overall MSHR misses
 system.cpu3.dcache.overall_mshr_misses::total          257                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1368000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1368000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1719500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1719500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       558500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       558500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3087500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      3087500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3087500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      3087500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002805                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002805                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002577                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002577                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.830508                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.830508                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002701                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.002701                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002701                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.002701                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9434.482759                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9434.482759                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15352.678571                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15352.678571                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11397.959184                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11397.959184                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12013.618677                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12013.618677                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12013.618677                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12013.618677                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1413000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1413000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      2020500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      2020500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       520500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       520500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3433500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      3433500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3433500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      3433500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003011                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003011                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002485                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002485                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.805970                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.805970                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002771                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.002771                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002771                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.002771                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9296.052632                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9296.052632                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  9638.888889                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  9638.888889                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.tags.replacements              388                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           77.972544                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              17573                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.replacements              384                       # number of replacements
+system.cpu3.icache.tags.tagsinuse           80.866510                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              17696                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              498                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            35.287149                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            35.534137                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.972544                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.152290                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.152290                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    80.866510                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.157942                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.157942                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          114                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            18637                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           18637                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        17573                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          17573                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        17573                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           17573                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        17573                       # number of overall hits
-system.cpu3.icache.overall_hits::total          17573                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          566                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          566                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          566                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           566                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          566                       # number of overall misses
-system.cpu3.icache.overall_misses::total          566                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7887000                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      7887000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      7887000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      7887000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      7887000                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      7887000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        18139                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        18139                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        18139                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        18139                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        18139                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        18139                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.031203                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.031203                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.031203                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.031203                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.031203                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.031203                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13934.628975                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13934.628975                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13934.628975                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13934.628975                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13934.628975                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13934.628975                       # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
+system.cpu3.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.222656                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses            18767                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           18767                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst        17696                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          17696                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        17696                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           17696                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        17696                       # number of overall hits
+system.cpu3.icache.overall_hits::total          17696                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          573                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          573                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          573                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           573                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          573                       # number of overall misses
+system.cpu3.icache.overall_misses::total          573                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7430000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      7430000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      7430000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      7430000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      7430000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      7430000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        18269                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        18269                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        18269                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        18269                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        18269                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        18269                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.031365                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.031365                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.031365                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.031365                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.031365                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.031365                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12966.841187                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 12966.841187                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12966.841187                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 12966.841187                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 12966.841187                       # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs           24                       # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           68                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           68                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           68                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           75                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           75                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           75                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           75                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           75                       # number of overall MSHR hits
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          498                       # number of ReadReq MSHR misses
 system.cpu3.icache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
 system.cpu3.icache.demand_mshr_misses::cpu3.inst          498                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.demand_mshr_misses::total          498                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          498                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          498                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6839000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      6839000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6839000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      6839000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6839000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      6839000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.027455                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.027455                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.027455                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.027455                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.027455                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.027455                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13732.931727                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13732.931727                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13732.931727                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 13732.931727                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13732.931727                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 13732.931727                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6421000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      6421000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6421000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      6421000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6421000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      6421000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.027259                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.027259                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.027259                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.027259                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.027259                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.027259                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12893.574297                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12893.574297                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12893.574297                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  422.903421                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       2336                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      538                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.342007                       # Average number of references to valid blocks.
+system.l2c.tags.tagsinuse                  418.779018                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       2347                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                      532                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.411654                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.784815                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      289.208824                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       58.009977                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       62.701446                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        5.295227                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        0.676960                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        5.511844                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.714328                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.786962                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      287.801372                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       58.040061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst       61.655177                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        5.312296                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst        2.346047                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        0.677363                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        1.443236                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.716504                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.004413                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000885                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000957                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.004392                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.000886                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000941                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000081                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000036                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.000010                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000084                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000022                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.006453                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          538                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::total           0.006390                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          532                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          139                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.008209                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    25512                       # Number of tag accesses
-system.l2c.tags.data_accesses                   25512                       # Number of data accesses
+system.l2c.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          130                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.008118                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    25618                       # Number of tag accesses
+system.l2c.tags.data_accesses                   25618                       # Number of data accesses
 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst           251                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst           412                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst           486                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst           485                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total              1634                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst           246                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst           410                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst           491                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst           491                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total              1638                       # number of ReadCleanReq hits
 system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst                 251                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 246                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 410                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 486                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 491                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 485                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 491                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1666                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                251                       # number of overall hits
+system.l2c.demand_hits::total                    1670                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                246                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                410                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                486                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                491                       # number of overall hits
 system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                485                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                491                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   1666                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data            22                       # number of UpgradeReq misses
+system.l2c.overall_hits::total                   1670                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data            27                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            14                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                75                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            21                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                89                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst          364                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst           88                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst           10                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst           13                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total             475                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          362                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst           86                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst            9                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst            7                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total             464                       # number of ReadCleanReq misses
 system.l2c.ReadSharedReq_misses::cpu0.data           75                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu1.data            7                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu2.data            1                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu3.data            1                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::total             84                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst               364                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst               362                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                88                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                86                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                10                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                 9                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 7                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   690                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              364                       # number of overall misses
+system.l2c.demand_misses::total                   679                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              362                       # number of overall misses
 system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               88                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               86                       # number of overall misses
 system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst               10                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst                9                       # number of overall misses
 system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst               13                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                7                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  690                       # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data      7927500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data      1298500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      1175000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data      1075000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     11476000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst     28062500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6697000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst       853500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst       993000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     36606000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data      5987000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data       551500                       # number of ReadSharedReq miss cycles
+system.l2c.overall_misses::total                  679                       # number of overall misses
+system.l2c.ReadExReq_miss_latency::cpu0.data      7390000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data      1059000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       956500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data      1308500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total     10714000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     27682000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6449000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst       632000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst       514000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     35277000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data      5980500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data       540500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu2.data        82500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu3.data        96500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total      6717500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     28062500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     13914500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      6697000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1850000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       853500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1257500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       993000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data      1171500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        54799500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     28062500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     13914500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      6697000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1850000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       853500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1257500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       993000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data      1171500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       54799500                       # number of overall miss cycles
+system.l2c.ReadSharedReq_miss_latency::total      6700000                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     27682000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data     13370500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      6449000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data      1599500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst       632000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1039000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       514000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data      1405000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        52691000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     27682000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data     13370500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      6449000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data      1599500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst       632000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1039000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       514000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data      1405000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       52691000                       # number of overall miss cycles
 system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           25                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           14                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              92                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst          615                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst          500                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst          496                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          608                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          496                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          500                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadCleanReq_accesses::cpu3.inst          498                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total          2109                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          2102                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu0.data           80                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu1.data           12                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu2.data           12                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu3.data           12                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::total          116                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             615                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst             608                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             500                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             496                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             496                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             500                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.inst             498                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                2356                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            615                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total                2349                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            608                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            500                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            496                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            496                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            500                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.inst            498                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2356                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.880000                       # miss rate for UpgradeReq accesses
+system.l2c.overall_accesses::total               2349                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.900000                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.961538                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.967391                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.591870                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.176000                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.020161                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.026104                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.225225                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.595395                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.173387                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.018000                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.014056                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.220742                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.937500                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.583333                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.083333                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.083333                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::total     0.724138                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.591870                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.595395                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.176000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.173387                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.020161                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.018000                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.026104                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.014056                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.292869                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.591870                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::total           0.289059                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.595395                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.176000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.173387                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.020161                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.018000                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.026104                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.014056                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.292869                       # miss rate for overall accesses
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84335.106383                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 99884.615385                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 97916.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 89583.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 87603.053435                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77094.780220                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 76102.272727                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst        85350                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 76384.615385                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 77065.263158                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79826.666667                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 78785.714286                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_rate::total          0.289059                       # miss rate for overall accesses
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78617.021277                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79708.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 109041.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 81786.259542                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76469.613260                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74988.372093                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70222.222222                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73428.571429                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 76028.017241                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data        79740                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77214.285714                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        82500                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        96500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 79970.238095                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 77094.780220                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 82334.319527                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 76102.272727                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data        92500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst        85350                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 96730.769231                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 76384.615385                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 90115.384615                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 79419.565217                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 77094.780220                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 82334.319527                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 76102.272727                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data        92500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst        85350                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 96730.769231                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 76384.615385                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 90115.384615                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 79419.565217                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 79761.904762                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 76469.613260                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 79115.384615                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74988.372093                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data        79975                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 70222.222222                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 79923.076923                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 73428.571429                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 108076.923077                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 77600.883652                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 76469.613260                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 79115.384615                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74988.372093                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data        79975                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 70222.222222                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 79923.076923                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 73428.571429                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 108076.923077                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 77600.883652                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2609,215 +2620,227 @@ system.l2c.avg_blocked_cycles::no_targets          nan                       # a
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst           10                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            4                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            6                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            2                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              6                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           22                       # number of UpgradeReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             6                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             2                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
+system.l2c.UpgradeReq_mshr_misses::cpu0.data           27                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu1.data           19                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           14                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           75                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           21                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           22                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           89                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          363                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           85                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            9                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total          457                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          361                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           82                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst            3                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            5                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total          451                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.data           75                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.data            7                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu2.data            1                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu3.data            1                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::total           84                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          363                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          361                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           85                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           82                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst            3                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            9                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            5                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              672                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          363                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::total              666                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          361                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           85                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           82                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst            3                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            9                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            5                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             672                       # number of overall MSHR misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       456500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       395500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       290997                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       417000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      1559997                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6987500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      1168500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1055000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       955000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total     10166000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     24396000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5728000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       584500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     30708500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5237000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       481500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.overall_mshr_misses::total             666                       # number of overall MSHR misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       560500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       396000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       438496                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       459499                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      1854495                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6450000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       929000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       836500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      1188500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      9404000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     23878500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5430000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst       217000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       364000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     29889500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5230500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       470500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data        72500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        86500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total      5877500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     24396000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     12224500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      5728000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data      1650000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1127500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       584500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data      1041500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     46752000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     24396000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     12224500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      5728000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data      1650000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1127500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       584500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data      1041500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     46752000                       # number of overall MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.880000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadSharedReq_mshr_miss_latency::total      5860000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     23878500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     11680500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      5430000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data      1399500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst       217000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data       909000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       364000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data      1275000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     45153500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     23878500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     11680500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      5430000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data      1399500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst       217000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data       909000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       364000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data      1275000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     45153500                       # number of overall MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.900000                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.961538                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.967391                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.170000                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.018072                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.216690                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.165323                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.010040                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.214558                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::total     0.724138                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.170000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.165323                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.018072                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010040                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.285229                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.590244                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::total      0.283525                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.170000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.165323                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.018072                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010040                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.285229                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        20750                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20815.789474                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20785.500000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        20850                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.960000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74335.106383                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89884.615385                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 87916.666667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 79583.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 77603.053435                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67206.611570                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 67388.235294                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 64944.444444                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67195.842451                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69826.666667                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 68785.714286                       # average ReadSharedReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::total     0.283525                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        72800                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data        69740                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        72500                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        86500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69970.238095                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67206.611570                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72334.319527                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67388.235294                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data        82500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86730.769231                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64944.444444                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 80115.384615                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69571.428571                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67206.611570                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72334.319527                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67388.235294                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        82500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86730.769231                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64944.444444                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 80115.384615                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69571.428571                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        69975                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        72800                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 67798.048048                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        69975                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        72800                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 67798.048048                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadResp                540                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              281                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              75                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               168                       # Transaction distribution
+system.membus.trans_dist::ReadResp                534                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              292                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              89                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               161                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq           541                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1736                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1736                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        42944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   42944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              243                       # Total snoops (count)
-system.membus.snoop_fanout::samples               990                       # Request fanout histogram
+system.membus.trans_dist::ReadSharedReq           535                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1742                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1742                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        42560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   42560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              233                       # Total snoops (count)
+system.membus.snoop_fanout::samples               988                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     990    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     988    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 990                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              926003                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 988                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              929005                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3714925                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.4                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadResp              2768                       # Transaction distribution
+system.membus.respLayer1.occupancy            3712661                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              3.5                       # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadResp              2782                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict             670                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             284                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            284                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              403                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             403                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq          2109                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq          660                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1469                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          583                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1144                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          366                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          375                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1136                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          350                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  6560                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39296                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::CleanEvict             677                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             295                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            295                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              389                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             389                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          2102                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq          681                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1448                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          595                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1141                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          380                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          374                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1141                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          357                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  6585                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        38848                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        32000                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        31744                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        31744                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        32000                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        31872                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 150784                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1022                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             4941                       # Request fanout histogram
+system.toL2Bus.pkt_size::total                 150336                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                            1026                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             4937                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
@@ -2828,29 +2851,29 @@ system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Re
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                   4941    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   4937    100.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               4941                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            2489462                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total               4937                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            2487961                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              2.3                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy            921499                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy            910999                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.9                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            506002                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy            509492                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            751497                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy            745995                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            425967                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy            443468                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            748987                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy            752993                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            449462                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy            440464                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            748992                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy            747998                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            400481                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy            407479                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
index 5bb91ca76..d98aa0788 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=8
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index 38ddcde63..78111ddb3 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
 warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu3: completed 10000 read, 5348 write accesses @992702
-system.cpu6: completed 10000 read, 5382 write accesses @999346
-system.cpu1: completed 10000 read, 5624 write accesses @1005749
-system.cpu7: completed 10000 read, 5532 write accesses @1010533
-system.cpu2: completed 10000 read, 5663 write accesses @1013622
-system.cpu0: completed 10000 read, 5506 write accesses @1016642
-system.cpu4: completed 10000 read, 5607 write accesses @1016852
-system.cpu5: completed 10000 read, 5639 write accesses @1018259
-system.cpu6: completed 20000 read, 10715 write accesses @1997205
-system.cpu3: completed 20000 read, 10977 write accesses @1998029
-system.cpu0: completed 20000 read, 11023 write accesses @2011456
-system.cpu1: completed 20000 read, 11145 write accesses @2015637
-system.cpu5: completed 20000 read, 11208 write accesses @2025366
-system.cpu2: completed 20000 read, 11366 write accesses @2025566
-system.cpu4: completed 20000 read, 11146 write accesses @2028120
-system.cpu7: completed 20000 read, 11121 write accesses @2045222
-system.cpu6: completed 30000 read, 16197 write accesses @2978950
-system.cpu3: completed 30000 read, 16504 write accesses @2996143
-system.cpu5: completed 30000 read, 16638 write accesses @3014669
-system.cpu2: completed 30000 read, 16960 write accesses @3020410
-system.cpu1: completed 30000 read, 16646 write accesses @3022510
-system.cpu0: completed 30000 read, 16578 write accesses @3036538
-system.cpu4: completed 30000 read, 16862 write accesses @3064327
-system.cpu7: completed 30000 read, 16883 write accesses @3094105
-system.cpu6: completed 40000 read, 21871 write accesses @3965015
-system.cpu3: completed 40000 read, 22121 write accesses @4005328
-system.cpu1: completed 40000 read, 22099 write accesses @4020080
-system.cpu0: completed 40000 read, 21993 write accesses @4023329
-system.cpu5: completed 40000 read, 22121 write accesses @4034804
-system.cpu2: completed 40000 read, 22585 write accesses @4048347
-system.cpu4: completed 40000 read, 22400 write accesses @4056884
-system.cpu7: completed 40000 read, 22529 write accesses @4115622
-system.cpu6: completed 50000 read, 27583 write accesses @4990697
-system.cpu3: completed 50000 read, 27753 write accesses @5007438
-system.cpu0: completed 50000 read, 27487 write accesses @5025428
-system.cpu5: completed 50000 read, 27656 write accesses @5027517
-system.cpu1: completed 50000 read, 27616 write accesses @5030165
-system.cpu2: completed 50000 read, 28090 write accesses @5055177
-system.cpu4: completed 50000 read, 27929 write accesses @5090891
-system.cpu7: completed 50000 read, 27992 write accesses @5110188
-system.cpu6: completed 60000 read, 32899 write accesses @5986136
-system.cpu3: completed 60000 read, 33406 write accesses @6022857
-system.cpu0: completed 60000 read, 33044 write accesses @6031653
-system.cpu1: completed 60000 read, 33212 write accesses @6041161
-system.cpu5: completed 60000 read, 33442 write accesses @6056413
-system.cpu2: completed 60000 read, 33657 write accesses @6078013
-system.cpu4: completed 60000 read, 33587 write accesses @6112419
-system.cpu7: completed 60000 read, 33576 write accesses @6115149
-system.cpu6: completed 70000 read, 38416 write accesses @6987907
-system.cpu3: completed 70000 read, 38845 write accesses @7046740
-system.cpu1: completed 70000 read, 38729 write accesses @7054748
-system.cpu0: completed 70000 read, 38718 write accesses @7054971
-system.cpu5: completed 70000 read, 39001 write accesses @7079629
-system.cpu2: completed 70000 read, 39269 write accesses @7096675
-system.cpu7: completed 70000 read, 39115 write accesses @7118065
-system.cpu4: completed 70000 read, 39088 write accesses @7118300
-system.cpu6: completed 80000 read, 43855 write accesses @7989172
-system.cpu3: completed 80000 read, 44347 write accesses @8044375
-system.cpu1: completed 80000 read, 44281 write accesses @8052426
-system.cpu0: completed 80000 read, 44306 write accesses @8066104
-system.cpu5: completed 80000 read, 44603 write accesses @8080810
-system.cpu7: completed 80000 read, 44480 write accesses @8104479
-system.cpu4: completed 80000 read, 44600 write accesses @8110552
-system.cpu2: completed 80000 read, 44822 write accesses @8120410
-system.cpu6: completed 90000 read, 49504 write accesses @8982438
-system.cpu3: completed 90000 read, 49941 write accesses @9055578
-system.cpu0: completed 90000 read, 49850 write accesses @9059967
-system.cpu1: completed 90000 read, 49940 write accesses @9064061
-system.cpu5: completed 90000 read, 50040 write accesses @9082907
-system.cpu4: completed 90000 read, 50137 write accesses @9101079
-system.cpu7: completed 90000 read, 50039 write accesses @9112455
-system.cpu2: completed 90000 read, 50353 write accesses @9135660
-system.cpu6: completed 100000 read, 55063 write accesses @9995319
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu0: completed 10000 read, 5465 write accesses @998393
+system.cpu1: completed 10000 read, 5568 write accesses @998560
+system.cpu6: completed 10000 read, 5642 write accesses @998656
+system.cpu2: completed 10000 read, 5573 write accesses @1004841
+system.cpu3: completed 10000 read, 5476 write accesses @1010347
+system.cpu4: completed 10000 read, 5603 write accesses @1011379
+system.cpu5: completed 10000 read, 5505 write accesses @1015197
+system.cpu7: completed 10000 read, 5844 write accesses @1020892
+system.cpu5: completed 20000 read, 10826 write accesses @1988283
+system.cpu0: completed 20000 read, 10919 write accesses @1991296
+system.cpu2: completed 20000 read, 11214 write accesses @2016414
+system.cpu4: completed 20000 read, 11078 write accesses @2020999
+system.cpu3: completed 20000 read, 10973 write accesses @2024874
+system.cpu7: completed 20000 read, 11506 write accesses @2025376
+system.cpu1: completed 20000 read, 11280 write accesses @2034256
+system.cpu6: completed 20000 read, 11147 write accesses @2037670
+system.cpu0: completed 30000 read, 16492 write accesses @3003033
+system.cpu5: completed 30000 read, 16298 write accesses @3011465
+system.cpu2: completed 30000 read, 16727 write accesses @3021562
+system.cpu7: completed 30000 read, 17173 write accesses @3033070
+system.cpu4: completed 30000 read, 16630 write accesses @3037868
+system.cpu6: completed 30000 read, 16672 write accesses @3038113
+system.cpu1: completed 30000 read, 16762 write accesses @3039811
+system.cpu3: completed 30000 read, 16588 write accesses @3051868
+system.cpu0: completed 40000 read, 21857 write accesses @4007879
+system.cpu2: completed 40000 read, 22234 write accesses @4028507
+system.cpu5: completed 40000 read, 21876 write accesses @4029649
+system.cpu6: completed 40000 read, 22097 write accesses @4032969
+system.cpu7: completed 40000 read, 22955 write accesses @4041622
+system.cpu1: completed 40000 read, 22471 write accesses @4049342
+system.cpu4: completed 40000 read, 22226 write accesses @4049383
+system.cpu3: completed 40000 read, 22078 write accesses @4062017
+system.cpu0: completed 50000 read, 27390 write accesses @5007193
+system.cpu7: completed 50000 read, 28594 write accesses @5029095
+system.cpu6: completed 50000 read, 27699 write accesses @5034544
+system.cpu5: completed 50000 read, 27508 write accesses @5037357
+system.cpu2: completed 50000 read, 27805 write accesses @5056032
+system.cpu1: completed 50000 read, 27932 write accesses @5062407
+system.cpu4: completed 50000 read, 27727 write accesses @5066868
+system.cpu3: completed 50000 read, 27598 write accesses @5095158
+system.cpu0: completed 60000 read, 33008 write accesses @6027788
+system.cpu7: completed 60000 read, 34229 write accesses @6038886
+system.cpu2: completed 60000 read, 33270 write accesses @6041019
+system.cpu5: completed 60000 read, 33038 write accesses @6044214
+system.cpu6: completed 60000 read, 33158 write accesses @6056522
+system.cpu1: completed 60000 read, 33437 write accesses @6060012
+system.cpu4: completed 60000 read, 33093 write accesses @6067283
+system.cpu3: completed 60000 read, 33046 write accesses @6099437
+system.cpu5: completed 70000 read, 38476 write accesses @7038412
+system.cpu0: completed 70000 read, 38672 write accesses @7049839
+system.cpu1: completed 70000 read, 38910 write accesses @7056694
+system.cpu2: completed 70000 read, 38729 write accesses @7056805
+system.cpu7: completed 70000 read, 39799 write accesses @7060220
+system.cpu4: completed 70000 read, 38525 write accesses @7063727
+system.cpu6: completed 70000 read, 38777 write accesses @7087878
+system.cpu3: completed 70000 read, 38653 write accesses @7104531
+system.cpu1: completed 80000 read, 44180 write accesses @8052473
+system.cpu4: completed 80000 read, 44107 write accesses @8058206
+system.cpu5: completed 80000 read, 44043 write accesses @8061949
+system.cpu2: completed 80000 read, 44449 write accesses @8062064
+system.cpu0: completed 80000 read, 44315 write accesses @8063955
+system.cpu7: completed 80000 read, 45316 write accesses @8089150
+system.cpu6: completed 80000 read, 44501 write accesses @8102611
+system.cpu3: completed 80000 read, 44234 write accesses @8131712
+system.cpu0: completed 90000 read, 49836 write accesses @9060237
+system.cpu1: completed 90000 read, 49611 write accesses @9070183
+system.cpu5: completed 90000 read, 49612 write accesses @9081515
+system.cpu4: completed 90000 read, 49785 write accesses @9092029
+system.cpu2: completed 90000 read, 50012 write accesses @9093129
+system.cpu6: completed 90000 read, 50151 write accesses @9110021
+system.cpu7: completed 90000 read, 50786 write accesses @9110647
+system.cpu3: completed 90000 read, 49787 write accesses @9134229
+system.cpu0: completed 100000 read, 55281 write accesses @10063247
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index b71684a15..dc6e8bffa 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=8
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 614ba1c08..ec7781619 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
 warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu6: completed 10000 read, 5570 write accesses @748299
-system.cpu5: completed 10000 read, 5647 write accesses @748339
-system.cpu7: completed 10000 read, 5495 write accesses @748944
-system.cpu1: completed 10000 read, 5568 write accesses @750499
-system.cpu0: completed 10000 read, 5483 write accesses @751080
-system.cpu3: completed 10000 read, 5619 write accesses @755896
-system.cpu4: completed 10000 read, 5746 write accesses @761190
-system.cpu2: completed 10000 read, 5739 write accesses @761633
-system.cpu7: completed 20000 read, 11020 write accesses @1491203
-system.cpu1: completed 20000 read, 11119 write accesses @1491567
-system.cpu0: completed 20000 read, 11060 write accesses @1496113
-system.cpu5: completed 20000 read, 11192 write accesses @1498026
-system.cpu2: completed 20000 read, 11268 write accesses @1499402
-system.cpu6: completed 20000 read, 11125 write accesses @1500210
-system.cpu4: completed 20000 read, 11177 write accesses @1507742
-system.cpu3: completed 20000 read, 11198 write accesses @1508349
-system.cpu1: completed 30000 read, 16685 write accesses @2235920
-system.cpu7: completed 30000 read, 16570 write accesses @2243071
-system.cpu3: completed 30000 read, 16661 write accesses @2246169
-system.cpu5: completed 30000 read, 16817 write accesses @2247226
-system.cpu6: completed 30000 read, 16630 write accesses @2251239
-system.cpu2: completed 30000 read, 17073 write accesses @2253746
-system.cpu0: completed 30000 read, 16607 write accesses @2257900
-system.cpu4: completed 30000 read, 16751 write accesses @2259082
-system.cpu1: completed 40000 read, 22443 write accesses @2985201
-system.cpu6: completed 40000 read, 22171 write accesses @2988819
-system.cpu5: completed 40000 read, 22360 write accesses @2994816
-system.cpu3: completed 40000 read, 22299 write accesses @2995156
-system.cpu2: completed 40000 read, 22516 write accesses @2995179
-system.cpu0: completed 40000 read, 22114 write accesses @2997980
-system.cpu4: completed 40000 read, 22133 write accesses @3004731
-system.cpu7: completed 40000 read, 22279 write accesses @3009795
-system.cpu1: completed 50000 read, 27939 write accesses @3723980
-system.cpu5: completed 50000 read, 27866 write accesses @3732543
-system.cpu2: completed 50000 read, 28007 write accesses @3736276
-system.cpu0: completed 50000 read, 27557 write accesses @3741693
-system.cpu6: completed 50000 read, 27758 write accesses @3746907
-system.cpu3: completed 50000 read, 28063 write accesses @3754651
-system.cpu4: completed 50000 read, 27711 write accesses @3755367
-system.cpu7: completed 50000 read, 27794 write accesses @3759179
-system.cpu1: completed 60000 read, 33413 write accesses @4481770
-system.cpu2: completed 60000 read, 33545 write accesses @4483814
-system.cpu5: completed 60000 read, 33400 write accesses @4486225
-system.cpu6: completed 60000 read, 33358 write accesses @4489305
-system.cpu0: completed 60000 read, 33272 write accesses @4495744
-system.cpu7: completed 60000 read, 33388 write accesses @4502600
-system.cpu3: completed 60000 read, 33518 write accesses @4505507
-system.cpu4: completed 60000 read, 33246 write accesses @4507884
-system.cpu6: completed 70000 read, 38763 write accesses @5228140
-system.cpu1: completed 70000 read, 38950 write accesses @5234719
-system.cpu5: completed 70000 read, 39075 write accesses @5237913
-system.cpu7: completed 70000 read, 38837 write accesses @5239204
-system.cpu2: completed 70000 read, 39142 write accesses @5242564
-system.cpu3: completed 70000 read, 39128 write accesses @5249855
-system.cpu0: completed 70000 read, 38875 write accesses @5253251
-system.cpu4: completed 70000 read, 38862 write accesses @5255205
-system.cpu6: completed 80000 read, 44316 write accesses @5978847
-system.cpu1: completed 80000 read, 44524 write accesses @5980771
-system.cpu5: completed 80000 read, 44534 write accesses @5982466
-system.cpu7: completed 80000 read, 44358 write accesses @5986610
-system.cpu0: completed 80000 read, 44270 write accesses @5996151
-system.cpu2: completed 80000 read, 44750 write accesses @6000893
-system.cpu3: completed 80000 read, 44691 write accesses @6004535
-system.cpu4: completed 80000 read, 44602 write accesses @6010875
-system.cpu6: completed 90000 read, 49845 write accesses @6717920
-system.cpu7: completed 90000 read, 50000 write accesses @6722062
-system.cpu1: completed 90000 read, 50241 write accesses @6726859
-system.cpu5: completed 90000 read, 50114 write accesses @6731510
-system.cpu0: completed 90000 read, 49747 write accesses @6741713
-system.cpu2: completed 90000 read, 50307 write accesses @6746697
-system.cpu3: completed 90000 read, 50421 write accesses @6748141
-system.cpu4: completed 90000 read, 50184 write accesses @6762059
-system.cpu1: completed 100000 read, 56005 write accesses @7477743
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu7: completed 10000 read, 5629 write accesses @741490
+system.cpu2: completed 10000 read, 5483 write accesses @742929
+system.cpu5: completed 10000 read, 5467 write accesses @745712
+system.cpu6: completed 10000 read, 5704 write accesses @746130
+system.cpu1: completed 10000 read, 5548 write accesses @750324
+system.cpu3: completed 10000 read, 5605 write accesses @759134
+system.cpu4: completed 10000 read, 5617 write accesses @761737
+system.cpu0: completed 10000 read, 5610 write accesses @763525
+system.cpu6: completed 20000 read, 11106 write accesses @1481450
+system.cpu1: completed 20000 read, 11101 write accesses @1481864
+system.cpu2: completed 20000 read, 11175 write accesses @1493928
+system.cpu5: completed 20000 read, 11075 write accesses @1494219
+system.cpu7: completed 20000 read, 11191 write accesses @1494602
+system.cpu3: completed 20000 read, 11025 write accesses @1510005
+system.cpu4: completed 20000 read, 11155 write accesses @1515394
+system.cpu0: completed 20000 read, 11262 write accesses @1521161
+system.cpu1: completed 30000 read, 16596 write accesses @2213794
+system.cpu7: completed 30000 read, 16886 write accesses @2238208
+system.cpu2: completed 30000 read, 16749 write accesses @2249468
+system.cpu6: completed 30000 read, 16669 write accesses @2250299
+system.cpu5: completed 30000 read, 16592 write accesses @2250650
+system.cpu4: completed 30000 read, 16824 write accesses @2255563
+system.cpu3: completed 30000 read, 16603 write accesses @2258409
+system.cpu0: completed 30000 read, 16741 write accesses @2271167
+system.cpu1: completed 40000 read, 22131 write accesses @2952037
+system.cpu7: completed 40000 read, 22258 write accesses @2971365
+system.cpu4: completed 40000 read, 22385 write accesses @2992340
+system.cpu6: completed 40000 read, 22195 write accesses @2994415
+system.cpu2: completed 40000 read, 22365 write accesses @2995127
+system.cpu5: completed 40000 read, 22189 write accesses @2998059
+system.cpu0: completed 40000 read, 22190 write accesses @3008067
+system.cpu3: completed 40000 read, 22193 write accesses @3026200
+system.cpu1: completed 50000 read, 27565 write accesses @3685675
+system.cpu7: completed 50000 read, 27746 write accesses @3722444
+system.cpu4: completed 50000 read, 27966 write accesses @3737210
+system.cpu6: completed 50000 read, 27651 write accesses @3741340
+system.cpu2: completed 50000 read, 28025 write accesses @3751350
+system.cpu5: completed 50000 read, 27824 write accesses @3753408
+system.cpu0: completed 50000 read, 27788 write accesses @3764354
+system.cpu3: completed 50000 read, 27801 write accesses @3780460
+system.cpu1: completed 60000 read, 33120 write accesses @4430711
+system.cpu7: completed 60000 read, 33190 write accesses @4467208
+system.cpu4: completed 60000 read, 33493 write accesses @4471542
+system.cpu6: completed 60000 read, 33060 write accesses @4489453
+system.cpu0: completed 60000 read, 33163 write accesses @4498105
+system.cpu2: completed 60000 read, 33785 write accesses @4501427
+system.cpu5: completed 60000 read, 33616 write accesses @4507211
+system.cpu3: completed 60000 read, 33449 write accesses @4535522
+system.cpu1: completed 70000 read, 38615 write accesses @5182293
+system.cpu4: completed 70000 read, 39172 write accesses @5218522
+system.cpu7: completed 70000 read, 38708 write accesses @5235601
+system.cpu0: completed 70000 read, 38698 write accesses @5238798
+system.cpu6: completed 70000 read, 38663 write accesses @5239196
+system.cpu2: completed 70000 read, 39373 write accesses @5249164
+system.cpu5: completed 70000 read, 39147 write accesses @5262073
+system.cpu3: completed 70000 read, 38967 write accesses @5264376
+system.cpu1: completed 80000 read, 44079 write accesses @5932822
+system.cpu4: completed 80000 read, 44608 write accesses @5965802
+system.cpu0: completed 80000 read, 44082 write accesses @5973833
+system.cpu6: completed 80000 read, 44113 write accesses @5993004
+system.cpu7: completed 80000 read, 44313 write accesses @5994643
+system.cpu2: completed 80000 read, 44913 write accesses @5996066
+system.cpu5: completed 80000 read, 44640 write accesses @6007836
+system.cpu3: completed 80000 read, 44574 write accesses @6019565
+system.cpu1: completed 90000 read, 49658 write accesses @6686890
+system.cpu4: completed 90000 read, 50184 write accesses @6709227
+system.cpu0: completed 90000 read, 49596 write accesses @6710987
+system.cpu7: completed 90000 read, 49959 write accesses @6740828
+system.cpu2: completed 90000 read, 50425 write accesses @6744606
+system.cpu6: completed 90000 read, 49767 write accesses @6747581
+system.cpu3: completed 90000 read, 49994 write accesses @6761894
+system.cpu5: completed 90000 read, 50371 write accesses @6774603
+system.cpu4: completed 100000 read, 55545 write accesses @7450335
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index f35fc603f..902cf6245 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=8
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 4efa8f799..7f8bac20f 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
 warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu0: completed 10000 read, 5438 write accesses @570769
-system.cpu3: completed 10000 read, 5486 write accesses @571889
-system.cpu7: completed 10000 read, 5573 write accesses @579188
-system.cpu1: completed 10000 read, 5608 write accesses @581011
-system.cpu6: completed 10000 read, 5567 write accesses @582686
-system.cpu4: completed 10000 read, 5591 write accesses @584722
-system.cpu2: completed 10000 read, 5557 write accesses @586208
-system.cpu5: completed 10000 read, 5736 write accesses @589352
-system.cpu0: completed 20000 read, 11059 write accesses @1157243
-system.cpu6: completed 20000 read, 11078 write accesses @1162403
-system.cpu3: completed 20000 read, 10981 write accesses @1164669
-system.cpu1: completed 20000 read, 11264 write accesses @1166168
-system.cpu7: completed 20000 read, 11196 write accesses @1167284
-system.cpu4: completed 20000 read, 11109 write accesses @1177371
-system.cpu2: completed 20000 read, 11057 write accesses @1180619
-system.cpu5: completed 20000 read, 11381 write accesses @1181888
-system.cpu3: completed 30000 read, 16437 write accesses @1737096
-system.cpu6: completed 30000 read, 16668 write accesses @1737657
-system.cpu0: completed 30000 read, 16583 write accesses @1744758
-system.cpu7: completed 30000 read, 16677 write accesses @1750821
-system.cpu1: completed 30000 read, 16900 write accesses @1758970
-system.cpu4: completed 30000 read, 16637 write accesses @1759061
-system.cpu2: completed 30000 read, 16692 write accesses @1764462
-system.cpu5: completed 30000 read, 17012 write accesses @1766901
-system.cpu3: completed 40000 read, 21900 write accesses @2318433
-system.cpu6: completed 40000 read, 22213 write accesses @2326183
-system.cpu0: completed 40000 read, 22100 write accesses @2330415
-system.cpu7: completed 40000 read, 22210 write accesses @2340974
-system.cpu1: completed 40000 read, 22520 write accesses @2342642
-system.cpu4: completed 40000 read, 22243 write accesses @2344379
-system.cpu2: completed 40000 read, 22366 write accesses @2353655
-system.cpu5: completed 40000 read, 22618 write accesses @2355311
-system.cpu3: completed 50000 read, 27430 write accesses @2905853
-system.cpu0: completed 50000 read, 27644 write accesses @2909589
-system.cpu6: completed 50000 read, 27833 write accesses @2914500
-system.cpu1: completed 50000 read, 28151 write accesses @2927131
-system.cpu7: completed 50000 read, 27858 write accesses @2932955
-system.cpu5: completed 50000 read, 28068 write accesses @2933318
-system.cpu4: completed 50000 read, 27863 write accesses @2935763
-system.cpu2: completed 50000 read, 27944 write accesses @2939029
-system.cpu3: completed 60000 read, 33085 write accesses @3485958
-system.cpu0: completed 60000 read, 33127 write accesses @3493381
-system.cpu6: completed 60000 read, 33377 write accesses @3507979
-system.cpu2: completed 60000 read, 33438 write accesses @3515468
-system.cpu4: completed 60000 read, 33417 write accesses @3516729
-system.cpu1: completed 60000 read, 33739 write accesses @3518747
-system.cpu5: completed 60000 read, 33740 write accesses @3526984
-system.cpu7: completed 60000 read, 33559 write accesses @3532034
-system.cpu3: completed 70000 read, 38725 write accesses @4062982
-system.cpu0: completed 70000 read, 38646 write accesses @4078763
-system.cpu2: completed 70000 read, 39080 write accesses @4090901
-system.cpu6: completed 70000 read, 38952 write accesses @4094520
-system.cpu5: completed 70000 read, 39225 write accesses @4095937
-system.cpu4: completed 70000 read, 39045 write accesses @4099573
-system.cpu1: completed 70000 read, 39252 write accesses @4107563
-system.cpu7: completed 70000 read, 39300 write accesses @4124546
-system.cpu3: completed 80000 read, 44295 write accesses @4644973
-system.cpu0: completed 80000 read, 44378 write accesses @4658860
-system.cpu6: completed 80000 read, 44423 write accesses @4666482
-system.cpu2: completed 80000 read, 44600 write accesses @4677073
-system.cpu5: completed 80000 read, 44978 write accesses @4678763
-system.cpu4: completed 80000 read, 44603 write accesses @4687972
-system.cpu1: completed 80000 read, 44846 write accesses @4689031
-system.cpu7: completed 80000 read, 44628 write accesses @4707929
-system.cpu3: completed 90000 read, 49800 write accesses @5223450
-system.cpu6: completed 90000 read, 49915 write accesses @5243962
-system.cpu0: completed 90000 read, 50068 write accesses @5252685
-system.cpu2: completed 90000 read, 50165 write accesses @5258561
-system.cpu5: completed 90000 read, 50552 write accesses @5261845
-system.cpu1: completed 90000 read, 50370 write accesses @5279905
-system.cpu4: completed 90000 read, 50291 write accesses @5283589
-system.cpu7: completed 90000 read, 50405 write accesses @5296282
-system.cpu3: completed 100000 read, 55379 write accesses @5815635
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu2: completed 10000 read, 5534 write accesses @569178
+system.cpu4: completed 10000 read, 5465 write accesses @574915
+system.cpu3: completed 10000 read, 5497 write accesses @574937
+system.cpu0: completed 10000 read, 5565 write accesses @574960
+system.cpu5: completed 10000 read, 5652 write accesses @581034
+system.cpu1: completed 10000 read, 5555 write accesses @582035
+system.cpu6: completed 10000 read, 5449 write accesses @585160
+system.cpu7: completed 10000 read, 5566 write accesses @590115
+system.cpu2: completed 20000 read, 11022 write accesses @1126531
+system.cpu4: completed 20000 read, 10939 write accesses @1142499
+system.cpu0: completed 20000 read, 11310 write accesses @1159134
+system.cpu1: completed 20000 read, 11166 write accesses @1161343
+system.cpu6: completed 20000 read, 10890 write accesses @1161677
+system.cpu5: completed 20000 read, 11181 write accesses @1166462
+system.cpu3: completed 20000 read, 11040 write accesses @1167366
+system.cpu7: completed 20000 read, 11027 write accesses @1170049
+system.cpu2: completed 30000 read, 16703 write accesses @1710014
+system.cpu4: completed 30000 read, 16637 write accesses @1736174
+system.cpu6: completed 30000 read, 16254 write accesses @1736781
+system.cpu0: completed 30000 read, 16824 write accesses @1741663
+system.cpu1: completed 30000 read, 16729 write accesses @1746318
+system.cpu3: completed 30000 read, 16380 write accesses @1746864
+system.cpu5: completed 30000 read, 16699 write accesses @1749543
+system.cpu7: completed 30000 read, 16593 write accesses @1755317
+system.cpu2: completed 40000 read, 22220 write accesses @2299827
+system.cpu4: completed 40000 read, 22137 write accesses @2310891
+system.cpu0: completed 40000 read, 22226 write accesses @2313874
+system.cpu3: completed 40000 read, 21851 write accesses @2325087
+system.cpu1: completed 40000 read, 22363 write accesses @2328426
+system.cpu6: completed 40000 read, 21890 write accesses @2332432
+system.cpu5: completed 40000 read, 22240 write accesses @2338721
+system.cpu7: completed 40000 read, 22061 write accesses @2344897
+system.cpu2: completed 50000 read, 27819 write accesses @2881934
+system.cpu4: completed 50000 read, 27895 write accesses @2900734
+system.cpu0: completed 50000 read, 27815 write accesses @2900790
+system.cpu3: completed 50000 read, 27422 write accesses @2903532
+system.cpu6: completed 50000 read, 27382 write accesses @2918034
+system.cpu1: completed 50000 read, 27840 write accesses @2920513
+system.cpu5: completed 50000 read, 27748 write accesses @2927060
+system.cpu7: completed 50000 read, 27652 write accesses @2929759
+system.cpu2: completed 60000 read, 33490 write accesses @3464091
+system.cpu0: completed 60000 read, 33375 write accesses @3480817
+system.cpu4: completed 60000 read, 33517 write accesses @3486603
+system.cpu3: completed 60000 read, 33057 write accesses @3493116
+system.cpu6: completed 60000 read, 33095 write accesses @3508756
+system.cpu1: completed 60000 read, 33334 write accesses @3509528
+system.cpu5: completed 60000 read, 33334 write accesses @3510074
+system.cpu7: completed 60000 read, 33249 write accesses @3510130
+system.cpu2: completed 70000 read, 38895 write accesses @4051519
+system.cpu0: completed 70000 read, 39000 write accesses @4061632
+system.cpu4: completed 70000 read, 39030 write accesses @4069905
+system.cpu3: completed 70000 read, 38509 write accesses @4083701
+system.cpu1: completed 70000 read, 38918 write accesses @4095424
+system.cpu7: completed 70000 read, 38836 write accesses @4097039
+system.cpu5: completed 70000 read, 38933 write accesses @4099052
+system.cpu6: completed 70000 read, 38530 write accesses @4100439
+system.cpu2: completed 80000 read, 44484 write accesses @4637728
+system.cpu0: completed 80000 read, 44611 write accesses @4638049
+system.cpu4: completed 80000 read, 44541 write accesses @4643818
+system.cpu3: completed 80000 read, 44193 write accesses @4673647
+system.cpu5: completed 80000 read, 44336 write accesses @4673863
+system.cpu7: completed 80000 read, 44217 write accesses @4679114
+system.cpu1: completed 80000 read, 44372 write accesses @4685942
+system.cpu6: completed 80000 read, 44195 write accesses @4694933
+system.cpu2: completed 90000 read, 50176 write accesses @5226302
+system.cpu4: completed 90000 read, 50158 write accesses @5229556
+system.cpu0: completed 90000 read, 50290 write accesses @5238793
+system.cpu5: completed 90000 read, 49829 write accesses @5251555
+system.cpu3: completed 90000 read, 49657 write accesses @5262428
+system.cpu1: completed 90000 read, 49892 write accesses @5268645
+system.cpu7: completed 90000 read, 49892 write accesses @5270670
+system.cpu6: completed 90000 read, 49840 write accesses @5284950
+system.cpu4: completed 100000 read, 55681 write accesses @5804619
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 71ed7021a..dfaa8805c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=8
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index fb4f3b04a..54948ce1e 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
 warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu2: completed 10000 read, 5682 write accesses @468618
-system.cpu0: completed 10000 read, 5397 write accesses @470518
-system.cpu4: completed 10000 read, 5666 write accesses @470555
-system.cpu7: completed 10000 read, 5549 write accesses @473660
-system.cpu1: completed 10000 read, 5645 write accesses @474596
-system.cpu6: completed 10000 read, 5628 write accesses @480303
-system.cpu5: completed 10000 read, 5664 write accesses @480328
-system.cpu3: completed 10000 read, 5553 write accesses @482516
-system.cpu1: completed 20000 read, 11276 write accesses @941108
-system.cpu0: completed 20000 read, 10999 write accesses @944640
-system.cpu2: completed 20000 read, 11272 write accesses @946991
-system.cpu7: completed 20000 read, 10999 write accesses @947826
-system.cpu4: completed 20000 read, 11411 write accesses @948779
-system.cpu6: completed 20000 read, 11144 write accesses @953193
-system.cpu5: completed 20000 read, 11173 write accesses @954235
-system.cpu3: completed 20000 read, 11228 write accesses @961631
-system.cpu1: completed 30000 read, 16818 write accesses @1419188
-system.cpu0: completed 30000 read, 16479 write accesses @1420336
-system.cpu5: completed 30000 read, 16548 write accesses @1421142
-system.cpu2: completed 30000 read, 16790 write accesses @1421818
-system.cpu7: completed 30000 read, 16464 write accesses @1422123
-system.cpu4: completed 30000 read, 17005 write accesses @1422259
-system.cpu6: completed 30000 read, 16812 write accesses @1431146
-system.cpu3: completed 30000 read, 16876 write accesses @1437656
-system.cpu2: completed 40000 read, 22285 write accesses @1891081
-system.cpu5: completed 40000 read, 22160 write accesses @1896261
-system.cpu7: completed 40000 read, 21953 write accesses @1897179
-system.cpu1: completed 40000 read, 22536 write accesses @1897207
-system.cpu0: completed 40000 read, 21989 write accesses @1898643
-system.cpu6: completed 40000 read, 22334 write accesses @1898811
-system.cpu4: completed 40000 read, 22788 write accesses @1906823
-system.cpu3: completed 40000 read, 22523 write accesses @1907448
-system.cpu2: completed 50000 read, 27730 write accesses @2357928
-system.cpu5: completed 50000 read, 27750 write accesses @2363043
-system.cpu1: completed 50000 read, 28041 write accesses @2368230
-system.cpu6: completed 50000 read, 27966 write accesses @2376268
-system.cpu0: completed 50000 read, 27789 write accesses @2380452
-system.cpu3: completed 50000 read, 27901 write accesses @2382173
-system.cpu7: completed 50000 read, 27437 write accesses @2383988
-system.cpu4: completed 50000 read, 28553 write accesses @2384309
-system.cpu2: completed 60000 read, 33436 write accesses @2836829
-system.cpu5: completed 60000 read, 33223 write accesses @2839619
-system.cpu6: completed 60000 read, 33442 write accesses @2843227
-system.cpu1: completed 60000 read, 33632 write accesses @2850331
-system.cpu3: completed 60000 read, 33335 write accesses @2850932
-system.cpu0: completed 60000 read, 33499 write accesses @2853510
-system.cpu7: completed 60000 read, 33083 write accesses @2863799
-system.cpu4: completed 60000 read, 34211 write accesses @2865957
-system.cpu5: completed 70000 read, 38796 write accesses @3309970
-system.cpu2: completed 70000 read, 39076 write accesses @3312829
-system.cpu6: completed 70000 read, 38982 write accesses @3317982
-system.cpu3: completed 70000 read, 38893 write accesses @3320658
-system.cpu1: completed 70000 read, 39042 write accesses @3326984
-system.cpu0: completed 70000 read, 39160 write accesses @3330466
-system.cpu4: completed 70000 read, 39705 write accesses @3336097
-system.cpu7: completed 70000 read, 38681 write accesses @3351133
-system.cpu2: completed 80000 read, 44448 write accesses @3784665
-system.cpu5: completed 80000 read, 44282 write accesses @3786578
-system.cpu6: completed 80000 read, 44649 write accesses @3794509
-system.cpu3: completed 80000 read, 44408 write accesses @3795252
-system.cpu1: completed 80000 read, 44488 write accesses @3798206
-system.cpu0: completed 80000 read, 44824 write accesses @3800842
-system.cpu4: completed 80000 read, 45327 write accesses @3814610
-system.cpu7: completed 80000 read, 44370 write accesses @3836498
-system.cpu2: completed 90000 read, 50112 write accesses @4258356
-system.cpu5: completed 90000 read, 49726 write accesses @4263981
-system.cpu1: completed 90000 read, 49878 write accesses @4270068
-system.cpu6: completed 90000 read, 50189 write accesses @4270506
-system.cpu3: completed 90000 read, 50062 write accesses @4274971
-system.cpu0: completed 90000 read, 50500 write accesses @4278576
-system.cpu4: completed 90000 read, 51009 write accesses @4290694
-system.cpu7: completed 90000 read, 50035 write accesses @4314863
-system.cpu5: completed 100000 read, 55296 write accesses @4735173
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu0: completed 10000 read, 5501 write accesses @467078
+system.cpu7: completed 10000 read, 5585 write accesses @472925
+system.cpu6: completed 10000 read, 5702 write accesses @473859
+system.cpu2: completed 10000 read, 5570 write accesses @475598
+system.cpu5: completed 10000 read, 5606 write accesses @476119
+system.cpu1: completed 10000 read, 5578 write accesses @479229
+system.cpu4: completed 10000 read, 5573 write accesses @479674
+system.cpu3: completed 10000 read, 5640 write accesses @487499
+system.cpu0: completed 20000 read, 10981 write accesses @938964
+system.cpu7: completed 20000 read, 11056 write accesses @947871
+system.cpu6: completed 20000 read, 11411 write accesses @949459
+system.cpu2: completed 20000 read, 11228 write accesses @952214
+system.cpu1: completed 20000 read, 11065 write accesses @953211
+system.cpu3: completed 20000 read, 11304 write accesses @953777
+system.cpu4: completed 20000 read, 11256 write accesses @958238
+system.cpu5: completed 20000 read, 11225 write accesses @963838
+system.cpu0: completed 30000 read, 16484 write accesses @1401349
+system.cpu7: completed 30000 read, 16587 write accesses @1415642
+system.cpu6: completed 30000 read, 17110 write accesses @1421193
+system.cpu2: completed 30000 read, 16781 write accesses @1426752
+system.cpu4: completed 30000 read, 16747 write accesses @1427872
+system.cpu3: completed 30000 read, 16939 write accesses @1428046
+system.cpu5: completed 30000 read, 16611 write accesses @1429067
+system.cpu1: completed 30000 read, 16662 write accesses @1439258
+system.cpu0: completed 40000 read, 22150 write accesses @1869298
+system.cpu7: completed 40000 read, 22057 write accesses @1896002
+system.cpu5: completed 40000 read, 22232 write accesses @1898974
+system.cpu3: completed 40000 read, 22443 write accesses @1899719
+system.cpu4: completed 40000 read, 22301 write accesses @1902954
+system.cpu2: completed 40000 read, 22327 write accesses @1903835
+system.cpu6: completed 40000 read, 22829 write accesses @1906722
+system.cpu1: completed 40000 read, 22218 write accesses @1911204
+system.cpu0: completed 50000 read, 27765 write accesses @2351180
+system.cpu7: completed 50000 read, 27538 write accesses @2370464
+system.cpu5: completed 50000 read, 27786 write accesses @2373992
+system.cpu6: completed 50000 read, 28263 write accesses @2376222
+system.cpu4: completed 50000 read, 27975 write accesses @2380027
+system.cpu2: completed 50000 read, 28023 write accesses @2381328
+system.cpu3: completed 50000 read, 27880 write accesses @2381446
+system.cpu1: completed 50000 read, 27838 write accesses @2385886
+system.cpu0: completed 60000 read, 33279 write accesses @2819366
+system.cpu5: completed 60000 read, 33244 write accesses @2835967
+system.cpu7: completed 60000 read, 32998 write accesses @2836623
+system.cpu6: completed 60000 read, 33822 write accesses @2850173
+system.cpu4: completed 60000 read, 33518 write accesses @2855957
+system.cpu3: completed 60000 read, 33583 write accesses @2858859
+system.cpu2: completed 60000 read, 33714 write accesses @2861156
+system.cpu1: completed 60000 read, 33518 write accesses @2869518
+system.cpu0: completed 70000 read, 38798 write accesses @3293451
+system.cpu7: completed 70000 read, 38547 write accesses @3309641
+system.cpu5: completed 70000 read, 38890 write accesses @3314464
+system.cpu6: completed 70000 read, 39365 write accesses @3323971
+system.cpu3: completed 70000 read, 39171 write accesses @3326960
+system.cpu2: completed 70000 read, 39322 write accesses @3333015
+system.cpu4: completed 70000 read, 39148 write accesses @3335631
+system.cpu1: completed 70000 read, 39115 write accesses @3343424
+system.cpu0: completed 80000 read, 44502 write accesses @3773676
+system.cpu7: completed 80000 read, 44178 write accesses @3784689
+system.cpu5: completed 80000 read, 44522 write accesses @3798601
+system.cpu6: completed 80000 read, 45044 write accesses @3801812
+system.cpu2: completed 80000 read, 44852 write accesses @3805475
+system.cpu3: completed 80000 read, 44704 write accesses @3805485
+system.cpu4: completed 80000 read, 44724 write accesses @3811165
+system.cpu1: completed 80000 read, 44691 write accesses @3816230
+system.cpu0: completed 90000 read, 50144 write accesses @4257479
+system.cpu7: completed 90000 read, 49707 write accesses @4267140
+system.cpu3: completed 90000 read, 50073 write accesses @4274290
+system.cpu2: completed 90000 read, 50440 write accesses @4275160
+system.cpu6: completed 90000 read, 50729 write accesses @4275803
+system.cpu5: completed 90000 read, 50235 write accesses @4277870
+system.cpu4: completed 90000 read, 50337 write accesses @4285144
+system.cpu1: completed 90000 read, 50416 write accesses @4290707
+system.cpu0: completed 100000 read, 55755 write accesses @4723747
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index ac16b5115..f67ca278f 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -277,7 +277,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=8
 phys_mem=Null
-random_seed=1234
 randomization=false
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index d407a62fd..76ce9faa1 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -5,76 +5,77 @@ warn: rounding error > tolerance
 warn: rounding error > tolerance
     1.250000 rounded to 1
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-system.cpu3: completed 10000 read, 5525 write accesses @760625
-system.cpu5: completed 10000 read, 5663 write accesses @765664
-system.cpu1: completed 10000 read, 5656 write accesses @767292
-system.cpu4: completed 10000 read, 5509 write accesses @775011
-system.cpu6: completed 10000 read, 5563 write accesses @775672
-system.cpu0: completed 10000 read, 5617 write accesses @776185
-system.cpu2: completed 10000 read, 5515 write accesses @776720
-system.cpu7: completed 10000 read, 5487 write accesses @777568
-system.cpu3: completed 20000 read, 11028 write accesses @1517020
-system.cpu4: completed 20000 read, 10944 write accesses @1530984
-system.cpu6: completed 20000 read, 11090 write accesses @1531354
-system.cpu1: completed 20000 read, 11154 write accesses @1539725
-system.cpu2: completed 20000 read, 10831 write accesses @1540287
-system.cpu7: completed 20000 read, 11114 write accesses @1543700
-system.cpu5: completed 20000 read, 11175 write accesses @1554030
-system.cpu0: completed 20000 read, 11186 write accesses @1559187
-system.cpu3: completed 30000 read, 16598 write accesses @2283007
-system.cpu1: completed 30000 read, 16605 write accesses @2291164
-system.cpu4: completed 30000 read, 16704 write accesses @2303776
-system.cpu6: completed 30000 read, 16727 write accesses @2310983
-system.cpu5: completed 30000 read, 16800 write accesses @2319374
-system.cpu0: completed 30000 read, 16827 write accesses @2322838
-system.cpu2: completed 30000 read, 16435 write accesses @2325373
-system.cpu7: completed 30000 read, 16664 write accesses @2329585
-system.cpu3: completed 40000 read, 22203 write accesses @3054702
-system.cpu1: completed 40000 read, 22271 write accesses @3064092
-system.cpu4: completed 40000 read, 22104 write accesses @3064313
-system.cpu0: completed 40000 read, 22287 write accesses @3078243
-system.cpu2: completed 40000 read, 22034 write accesses @3081341
-system.cpu6: completed 40000 read, 22288 write accesses @3087106
-system.cpu7: completed 40000 read, 22139 write accesses @3090483
-system.cpu5: completed 40000 read, 22456 write accesses @3115167
-system.cpu3: completed 50000 read, 27685 write accesses @3816500
-system.cpu0: completed 50000 read, 27819 write accesses @3832053
-system.cpu4: completed 50000 read, 27741 write accesses @3843043
-system.cpu6: completed 50000 read, 27737 write accesses @3846249
-system.cpu1: completed 50000 read, 27853 write accesses @3847483
-system.cpu2: completed 50000 read, 27474 write accesses @3847984
-system.cpu7: completed 50000 read, 27784 write accesses @3859638
-system.cpu5: completed 50000 read, 27985 write accesses @3881373
-system.cpu3: completed 60000 read, 33240 write accesses @4586843
-system.cpu0: completed 60000 read, 33283 write accesses @4597223
-system.cpu4: completed 60000 read, 33280 write accesses @4612495
-system.cpu6: completed 60000 read, 33333 write accesses @4617744
-system.cpu7: completed 60000 read, 33161 write accesses @4621422
-system.cpu1: completed 60000 read, 33491 write accesses @4624484
-system.cpu2: completed 60000 read, 33073 write accesses @4629780
-system.cpu5: completed 60000 read, 33544 write accesses @4644282
-system.cpu4: completed 70000 read, 38779 write accesses @5369467
-system.cpu0: completed 70000 read, 38963 write accesses @5378485
-system.cpu3: completed 70000 read, 38978 write accesses @5379251
-system.cpu6: completed 70000 read, 38932 write accesses @5401655
-system.cpu1: completed 70000 read, 39086 write accesses @5406571
-system.cpu2: completed 70000 read, 38592 write accesses @5406836
-system.cpu5: completed 70000 read, 39048 write accesses @5413732
-system.cpu7: completed 70000 read, 38996 write accesses @5416693
-system.cpu4: completed 80000 read, 44330 write accesses @6131353
-system.cpu3: completed 80000 read, 44590 write accesses @6147147
-system.cpu0: completed 80000 read, 44469 write accesses @6155707
-system.cpu2: completed 80000 read, 44132 write accesses @6161312
-system.cpu1: completed 80000 read, 44704 write accesses @6173967
-system.cpu6: completed 80000 read, 44443 write accesses @6181977
-system.cpu5: completed 80000 read, 44606 write accesses @6182931
-system.cpu7: completed 80000 read, 44440 write accesses @6186571
-system.cpu4: completed 90000 read, 49946 write accesses @6904148
-system.cpu3: completed 90000 read, 50248 write accesses @6916525
-system.cpu0: completed 90000 read, 49962 write accesses @6927054
-system.cpu2: completed 90000 read, 49754 write accesses @6935410
-system.cpu6: completed 90000 read, 49929 write accesses @6947145
-system.cpu1: completed 90000 read, 50385 write accesses @6951341
-system.cpu5: completed 90000 read, 50139 write accesses @6962538
-system.cpu7: completed 90000 read, 50280 write accesses @6972720
-system.cpu4: completed 100000 read, 55350 write accesses @7662866
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+system.cpu0: completed 10000 read, 5584 write accesses @762508
+system.cpu4: completed 10000 read, 5574 write accesses @764238
+system.cpu2: completed 10000 read, 5499 write accesses @766606
+system.cpu3: completed 10000 read, 5407 write accesses @769966
+system.cpu6: completed 10000 read, 5627 write accesses @771429
+system.cpu7: completed 10000 read, 5581 write accesses @773439
+system.cpu5: completed 10000 read, 5758 write accesses @783372
+system.cpu1: completed 10000 read, 5719 write accesses @784929
+system.cpu0: completed 20000 read, 11047 write accesses @1530543
+system.cpu7: completed 20000 read, 11107 write accesses @1533180
+system.cpu3: completed 20000 read, 10950 write accesses @1534683
+system.cpu6: completed 20000 read, 11194 write accesses @1535502
+system.cpu2: completed 20000 read, 11001 write accesses @1542405
+system.cpu5: completed 20000 read, 11318 write accesses @1544896
+system.cpu4: completed 20000 read, 11200 write accesses @1550910
+system.cpu1: completed 20000 read, 11300 write accesses @1556665
+system.cpu3: completed 30000 read, 16397 write accesses @2295657
+system.cpu2: completed 30000 read, 16594 write accesses @2305853
+system.cpu6: completed 30000 read, 16817 write accesses @2307161
+system.cpu0: completed 30000 read, 16652 write accesses @2307391
+system.cpu4: completed 30000 read, 16735 write accesses @2311189
+system.cpu7: completed 30000 read, 16751 write accesses @2314182
+system.cpu5: completed 30000 read, 16940 write accesses @2314755
+system.cpu1: completed 30000 read, 16881 write accesses @2333727
+system.cpu3: completed 40000 read, 22068 write accesses @3066226
+system.cpu4: completed 40000 read, 22266 write accesses @3071105
+system.cpu2: completed 40000 read, 22243 write accesses @3071593
+system.cpu5: completed 40000 read, 22338 write accesses @3072991
+system.cpu0: completed 40000 read, 22234 write accesses @3074112
+system.cpu6: completed 40000 read, 22357 write accesses @3078814
+system.cpu7: completed 40000 read, 22306 write accesses @3082874
+system.cpu1: completed 40000 read, 22431 write accesses @3111031
+system.cpu6: completed 50000 read, 27886 write accesses @3834085
+system.cpu3: completed 50000 read, 27514 write accesses @3834389
+system.cpu4: completed 50000 read, 27846 write accesses @3838179
+system.cpu2: completed 50000 read, 27730 write accesses @3839105
+system.cpu7: completed 50000 read, 27761 write accesses @3841365
+system.cpu5: completed 50000 read, 28029 write accesses @3855011
+system.cpu0: completed 50000 read, 27884 write accesses @3855221
+system.cpu1: completed 50000 read, 28029 write accesses @3872616
+system.cpu3: completed 60000 read, 32929 write accesses @4596558
+system.cpu4: completed 60000 read, 33251 write accesses @4604359
+system.cpu2: completed 60000 read, 33251 write accesses @4609070
+system.cpu6: completed 60000 read, 33602 write accesses @4611658
+system.cpu5: completed 60000 read, 33552 write accesses @4623475
+system.cpu7: completed 60000 read, 33412 write accesses @4626557
+system.cpu0: completed 60000 read, 33422 write accesses @4628259
+system.cpu1: completed 60000 read, 33486 write accesses @4645474
+system.cpu4: completed 70000 read, 38743 write accesses @5365823
+system.cpu3: completed 70000 read, 38597 write accesses @5375393
+system.cpu2: completed 70000 read, 38711 write accesses @5386294
+system.cpu6: completed 70000 read, 39263 write accesses @5390216
+system.cpu5: completed 70000 read, 39043 write accesses @5395080
+system.cpu7: completed 70000 read, 38983 write accesses @5398310
+system.cpu0: completed 70000 read, 38989 write accesses @5399705
+system.cpu1: completed 70000 read, 39150 write accesses @5425218
+system.cpu4: completed 80000 read, 44094 write accesses @6130494
+system.cpu3: completed 80000 read, 44230 write accesses @6148777
+system.cpu6: completed 80000 read, 44684 write accesses @6157555
+system.cpu5: completed 80000 read, 44551 write accesses @6161202
+system.cpu2: completed 80000 read, 44139 write accesses @6164119
+system.cpu0: completed 80000 read, 44724 write accesses @6175294
+system.cpu7: completed 80000 read, 44671 write accesses @6179013
+system.cpu1: completed 80000 read, 44749 write accesses @6192724
+system.cpu4: completed 90000 read, 49488 write accesses @6869712
+system.cpu6: completed 90000 read, 50150 write accesses @6920477
+system.cpu2: completed 90000 read, 49757 write accesses @6931420
+system.cpu3: completed 90000 read, 50041 write accesses @6935428
+system.cpu0: completed 90000 read, 50304 write accesses @6951052
+system.cpu5: completed 90000 read, 50260 write accesses @6951232
+system.cpu7: completed 90000 read, 50274 write accesses @6961816
+system.cpu1: completed 90000 read, 50419 write accesses @6968220
+system.cpu4: completed 100000 read, 54873 write accesses @7628407
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
index b3780e14b..8c46bff97 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=true
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index df3120f37..95197b990 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=true
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 9c27c2144..fa6d969d1 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=true
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 4dcf159bb..3e7f75c5f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=true
 
 [system.ruby.clk_domain]
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 45a39afd9..a8da47f38 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -154,7 +154,6 @@ hot_lines=false
 memory_size_bits=48
 num_of_sequencers=1
 phys_mem=Null
-random_seed=1234
 randomization=true
 
 [system.ruby.clk_domain]